This fixes the following sparse build warning:
mach-rockchip/platsmp.c:68:43: Using plain integer as NULL pointer
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Merge in cleanup to avoid internal conflicts with newly added code.
* treewide/cleanup:
ARM: use "depends on" for SoC configs instead of "if" after prompt
ARM/clocksource: use automatic DT probing for ux500 PRCMU
ARM: use const and __initconst for smp_operations
ARM: hisi: do not export smp_operations structures
Signed-off-by: Olof Johansson <olof@lixom.net>
The newly added rk3036 smp operations missed the wholesale fixup from
Masahiro Yamada. So fix that now.
Reported-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The dual-core Cortex A7 rk3036 is a bit special in that it does not allow
to control the actual powerdomain of the cpu cores, while the rest of the
smp-bringup like reset control and entry address handling stays the same.
Its bigger sibling, the quad-core rk3128 again allows powerdomain control.
So allow that case by introducing a separate smp-enable-method, that simply
disables powerdomain handling in the common code.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Xing Zheng <zhengxing@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
The following was seen in branch[0] build.
arch/arm/mach-rockchip/platsmp.c:154:23: error:
'rockchip_secondary_startup' undeclared (first use in this function)
branch[0]:
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.3-armsoc/soc
The broken build is caused by the commit fe4407c0dc
("ARM: rockchip: fix the CPU soft reset").
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
The breakage was a result of it being wrongly merged in my branch with
the cache invalidation rework from Russell 02b4e2756e
("ARM: v7 setup function should invalidate L1 cache").
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Use the below scripts to check:
scripts/checkpatch.pl -f --subject arch/arm/mach-rockchip/platsmp.c
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The patch can ensure that v7_exit_coherency_flush() in rockchip_cpu_die()
executed in time.
The mdelay(1) has enough time to fix the problem of CPU offlining.
That's a workaround way in rockchip hotplug code,
At least, we haven't a better way to solve it. Who know,
that maybe fixed by chip (hardware) in the future.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We need different orderings when turning a core on and turning a core
off. In one case we need to assert reset before turning power off.
In ther other case we need to turn power on and the deassert reset.
In general, the correct flow is:
CPU off:
reset_control_assert
regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), BIT(pd))
wait_for_power_domain_to_turn_off
CPU on:
regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), 0)
wait_for_power_domain_to_turn_on
reset_control_deassert
This is needed for stressing CPU up/down, as per:
cd /sys/devices/system/cpu/
for i in $(seq 10000); do
echo "================= $i ============"
for j in $(seq 100); do
while [[ "$(cat cpu1/online)$(cat cpu2/online)$(cat cpu3/online)" != "000"" ]]
echo 0 > cpu1/online
echo 0 > cpu2/online
echo 0 > cpu3/online
done
while [[ "$(cat cpu1/online)$(cat cpu2/online)$(cat cpu3/online)" != "111" ]]; do
echo 1 > cpu1/online
echo 1 > cpu2/online
echo 1 > cpu3/online
done
done
done
The following is reproducable log:
[34466.186812] PM: noirq suspend of devices complete after 0.669 msecs
[34466.186824] Disabling non-boot CPUs ...
[34466.187509] CPU1: shutdown
[34466.188672] CPU2: shutdown
[34473.736627] Kernel panic - not syncing:Watchdog detected hard LOCKUP on cpu 0
.......
or others similar log:
.......
[ 4072.454453] CPU1: shutdown
[ 4072.504436] CPU2: shutdown
[ 4072.554426] CPU3: shutdown
[ 4072.577827] CPU1: Booted secondary processor
[ 4072.582611] CPU2: Booted secondary processor
<hang>
Tested by cpu up/down scripts, the results told us need delay more time
before write the sram. The wait time is affected by many aspects
(e.g: cpu frequency, bootrom frequency, sram frequency, bus speed, ...).
Although the cpus other than cpu0 will write the sram, the speedy is
no the same as cpu0, if the cpu0 early wake up, perhaps the other cpus
can't startup. As we know, the cpu0 can wake up when the cpu1/2/3 write
the 'sram+4/8' and send the sev.
Anyway.....
At the moment, 1ms delay will be happy work for cpu up/down scripts test.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Fixes: 3ee851e212 ("ARM: rockchip: add basic smp support for rk3288")
Cc: stable@vger.kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Merge tag 'cpuinit-v4.1-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/paulg/linux
Pull __cpuinit removal from Paul Gortmaker:
"Remove __cpuinit macros and users.
We removed the __cpuinit stuff in 3.11-rc1 with commit 22f0a27367
("init.h: remove __cpuinit sections from the kernel") but we left some
no-op stubs as a courtesy to unmerged code.
Here we get rid of the stubs as well, since (as can be seen in these
changes) they are enabling use cases to sneak back in, primarily from
older BSP code that has been living out of tree for some time prior to
getting mainlined. So we get rid of these "new" users 1st and then
get rid of the stubs.
Obviously, getting rid of the stubs can't happen until all the users
are gone, so I had to keep this together as a series, even though some
of these commits since got picked up into maintainers trees as well.
The nature of this change is such that it should have zero impact on
the generated runtime.
This is one of several independent cleanup branches aimed at enabling
better organization in the init.h and module.h code. They have been
getting coverage in the linux-next tree for the last month, in
addition to my local testing, which also covers approximately a half
dozen or more architectures"
* tag 'cpuinit-v4.1-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/paulg/linux:
init: delete the __cpuinit related stubs
kernel/cpu.c: remove new instance of __cpuinit that crept back in
sched/core: remove __cpuinit section tag that crept back in.
mips/mm/tlbex: remove new instance of __cpuinit that crept back in
mips/c-r4k: remove legacy __cpuinit section that crept in
mips/bcm77xx: remove legacy __cpuinit sections that crept in
mips/ath25: remove legacy __cpuinit section that crept in
arm/mach-hisi: remove legacy __CPUINIT section that crept in
arm/mach-rockchip: remove legacy __cpuinit section that crept in
arm/mach-mvebu: remove legacy __cpuinit sections that crept in
arm/mach-keystone: remove legacy __cpuinit sections that crept in
We removed __cpuinit support (leaving no-op stubs) quite some time ago.
However this one crept back in as of commit a7a2b3118b
("ARM: rockchip: add smp bringup code").
Since we want to clobber the stubs soon, get this removed now.
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
All ARMv5 and older CPUs invalidate their caches in the early assembly
setup function, prior to enabling the MMU. This is because the L1
cache should not contain any data relevant to the execution of the
kernel at this point; all data should have been flushed out to memory.
This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed,
these typically do not search their caches when caching is disabled (as
it needs to be when the MMU is disabled) so this change should be safe.
ARMv7 allows there to be CPUs which search their caches while caching is
disabled, and it's permitted that the cache is uninitialised at boot;
for these, the architecture reference manual requires that an
implementation specific code sequence is used immediately after reset
to ensure that the cache is placed into a sane state. Such
functionality is definitely outside the remit of the Linux kernel, and
must be done by the SoC's firmware before _any_ CPU gets to the Linux
kernel.
Changing the data cache clean+invalidate to a mere invalidate allows us
to get rid of a lot of platform specific hacks around this issue for
their secondary CPU bringup paths - some of which were buggy.
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Tested-by: Florian Fainelli <f.fainelli@gmail.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The regmap_config struct may be const because it is not modified by the
driver and regmap_init() accepts pointer to const.
Make function rockchip_get_core_reset() static because it is not used
outside of the platsmp.c file.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch add basic rk3288 smp support.
Only cortex-A9 need invalid L1, A7/A12/A15/A17 should not invalid L1, since
for A7/A12/A15, the invalidation would be taken as clean and invalidate.
If you use the software manual invalidation instead of hardware invalidation
(assert l1/l2rstdisable during reset) after reset, there is tiny change that
some cachelines would be in dirty and valid state after reset(since the ram
content would be random value after reset), then the unexpected clean might
lead to system crash.
It is a known issue for the A12/A17 MPCore multiprocessor that the active
processors might be stalled when the individual processor is powered down,
we can avoid this prolbem by softreset the processor before power it down.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Makes it possible to define a rockchip,pmu phandle in the cpus node directly
referencing the pmu syscon instead of searching for specific compatible.
The old way of finding the pmu stays of course available.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The pmu register space is - like the GRF - shared by quite some peripherals.
On the rk3188 and rk3288 even parts of the pinctrl are living there.
Therefore we normally shouldn't map it a second time when the syscon
does this already.
Therefore convert the cpu power-domain handling to access the pmu via a
regmap and at first try to get it via the syscon interface.
Getting this syscon will only fail if the pmu node does not have the
"syscon" compatible and thus does not get shared with other drivers.
In this case we map it like before and create the necessary regmap on
top of it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Adds ability to shutdown all CPUs except the first one
(since it might be special for a lot of platforms).
It is now possible to use kexec which requires such a feature.
Signed-off-by: Romain Perier <romain.perier@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
With the newly introduced CPU_METHOD_OF_DECLARE is not necessary anymore
to reference the relevant smp_ops in the board file, but instead it can
simply be set by the enable-method property of the cpu nodes.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
The error emitted when mapping the pmu failed, wrongly mentions the sram.
Reported-by: Kent Borg <kentborg@borg.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This adds the necessary smp-operations and startup code to use
additional cores on Rockchip SoCs.
We currently hog the power management unit in the smp code, as it is
necessary to control the power to the cpu core and nothing else is
currently using it, so a generic implementation can be done later.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Ulrich Prinz <ulrich.prinz@googlemail.com>
Peter Griffin