Commit Graph

20 Commits

Author SHA1 Message Date
Takashi Iwai 786e1c3719 ASoC: intel: Replace kthread with work
The usage pattern of kthread worker in Intel SST drivers can be
replaced gracefully with the normal workqueue, which is more light-
weight and easier to manage in general.  Let's do it.

While in the replacement, move the schedule_work() call inside the
spinlock for excluding the race, too.

Signed-off-by: Takashi Iwai <tiwai@suse.de>
Acked-by: Vinod Koul <vinod.koul@intel.com>
Tested-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-30 17:41:13 +00:00
Vinod Koul a83e3b4c44 ASoC: Intel: Skylake: Add D0i3 mode ref counting
For device opened/closed, we check the D0i3 capability for the device
and invoke skl_tplg_d0i3_get/put, which counts the use case based on the
mode supported.

These counters are then used to decide if the device can enter D0i3 mode
of streaming or non-streaming or no D0i3.

Signed-off-by: Jayachandran B <jayachandran.b@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-03 11:14:42 -06:00
Vinod Koul 8a0cb2360d ASoC: Intel: Skylake: Add support for LPMode
For D0i3, we need to tell DSP to run the pipelines in LP mode. This
information is kept in topology and passed to driver as an attribute
for pipe.

So add a new tuple for lpmode and program the pipe based on value set.

Signed-off-by: Jayachandran B <jayachandran.b@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-03 11:14:22 -06:00
Jayachandran B 5bb4cd46ac ASoC: Intel: Skylake: Add D0iX callbacks
The driver needs two DSP callback, one to set D0i0 (active) and D0i3
(low-power) states.

Add these callbacks in dsp ops and implement them for broxton platforms.

Signed-off-by: Jayachandran B <jayachandran.b@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-03 11:14:22 -06:00
Pardha Saradhi K a26a3f53e3 ASoC: Intel: Skylake: Add support for programming D0i3C
To set the controller in D0i3 mode, the driver needs to set D0i3C
register after DSP is quiesced. Since the D0iX entry/exit is done by IPC,
add this as callback so that it can be invoked from IPC module.

Signed-off-by: Pardha Saradhi K <pardha.saradhi.kesapragada@intel.com>
Signed-off-by: Jayachandran B <jayachandran.b@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-03 11:14:22 -06:00
Pardha Saradhi K 41b7523f19 ASoC: Intel: Skylake: Add D0iX IPCs
The audio DSP supports intermediate power states between D0 and D3
states. These states are D0i0 and D0i3 states.

Collectively we refer these two states as D0iX states.

To set or wake up from these states, driver also needs to send an IPC "Set D0iX
IPC" before doing anything else.

Add support for this new IPC messages.

Signed-off-by: Pardha Saradhi K <pardha.saradhi.kesapragada@intel.com>
Signed-off-by: Jayachandran B <jayachandran.b@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-03 11:14:10 -06:00
Senthilnathan Veppur 3d4006cd50 ASoC: Intel: Skylake: Add module processing domain support
A module can be scheduled in deferent processing domains in DSP. Topology
specifies the module domain.

Signed-off-by: Senthilnathan Veppur <senthilnathanx.veppur@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-08-08 11:54:59 +01:00
Vinod Koul 8d983be820 ASoC: Intel: Skylake: Fix a comment style
While changing code notice bad comment style, so fix it up.

Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-08-08 11:54:59 +01:00
Ramesh Babu 20fb2fbdfc ASoC: Intel: Skylake: Add library loading IPCs
DSP fw can have additional firmwares as libs. These libs can be
loaded using message IPC_GLB_LOAD_LIBRARY.

Signed-off-by: Ramesh Babu <ramesh.babu@intel.com>
Signed-off-by: Kranthi G <gudishax.kranthikumar@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-08-08 11:54:59 +01:00
Kranthi G 15ecaba914 ASoC: Intel: Skylake: add support for tplg manifest load
Topology manifest gives information about the libraries to be
loaded. Implement the topology manifest load callback to get
this.

Signed-off-by: Kranthi G <gudishax.kranthikumar@intel.com>
Signed-off-by: Senthilnathan Veppur <senthilnathanx.veppur@intel.com>
Signed-off-by: Ramesh Babu <ramesh.babu@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-08-08 11:54:59 +01:00
Vinod Koul 78cdbbdac0 ASoC: Intel: Skylake: split fw and dsp initialization
The DSP instance creation also loads the firmware on DSPs. For library load
the firmware names come from topology so can't be loaded at object creation.

So split the firmware load and object creation. FW load is now called after
topology init in platform probe.

Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-08-08 11:54:59 +01:00
Jayachandran B 052f103c89 ASoC: Intel: Skylake: Add DSP muti-core infrastructure
The DSP can have more than one cores. In that case the secondary
core has to be managed by the driver. This patch adds the changes
to driver infrastructure to support multiple core.

A new object skl_dsp_cores is introduced to support multiple
core. Helpers skl_dsp_get_core() skl_dsp_put_core() help to
managed the cores.

Many of the power_up/down and DSP APIs take additional argument
of core_id. The primary core, 0 is always powered up first and
then on demand second core.

Signed-off-by: Jayachandran B <jayachandran.b@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-06-22 16:13:12 +01:00
Jayachandran B 1665c177ab ASoC: Intel: Skylake: Enable firmware reload in suspend
Broxton DSP needs retains code loaded during runtime_pm cycles.
But it looses that on suspend cycle, so on resume we need to
download the firmware again.

This is done by adding a new flag and based on flag status, we
download the firmware.

Signed-off-by: Jayachandran B <jayachandran.b@intel.com>
Signed-off-by: Senthilnathan Veppur <senthilnathanx.veppur@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-06-14 14:59:33 +01:00
Dharageswari R fe3f4442e2 ASoC: Intel: Skylake: Clean up of driver resources in suspend
On suspend firmware is re-initialized so resources are reset inside
firmware. Driver should also clear the firmware counters at this time.

Signed-off-by: Dharageswari R <dharageswari.r@intel.com>
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-06-07 14:19:11 +01:00
Shreyas NC ea6b3e9437 ASoC: Intel: Skylake: Add DSP firmware manifest parsing
Module params like module_id and loadable flag can be changed
in the DSP Firmware. These are kept in the firmware manifest
and driver should read these values from this manifest.

So, add support to parse the DSP firmware manifest and
read these module params.

Signed-off-by: Shreyas NC <shreyas.nc@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-05-30 18:24:41 +01:00
Jayachandran B 0c8ba9d285 ASoC: Intel: Skylake: fix reset controller sequencing
MISCBDCGE is a new register for Misc Backbone clock gate control
which is useful to control while resetting the link and ensuring
controller is in required state so add API to control it

HW recommends that we reset with CGCTL.MISCBDCGE disabled, so add
that while doing init chip and reset sequence.

Signed-off-by: Jayachandran B <jayachandran.b@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-01-10 12:19:01 +00:00
Mousami Jana cce1c7f383 ASoC: Intel: Skylake: add LARGE_CONFIG_GET IPC support
For messages which have larger payload than mailbox data, we need
to split the payload using set of messages containing mailbox
size as payload.

For sending such payload we already support LARGE_CONFIG_SET
IPCs and now to query such payload add LARGE_CONFIG_GET IPC

Signed-off-by: Mousami Jana <mousami.janax@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-12-08 17:57:51 +00:00
Dharageswari R 6c5768b3aa ASoC: Intel: Skylake: Add support for Loadable modules
A module is loaded when the path consisting the module is opened.
The module binary(ies) is loaded from file system and cached in
kernel memory for future use. This is downloaded to DSP using DMA
and invoking Load module IPCs

This patch adds support for load/unload module IPCs, DMAing
modules and manging the modules

Signed-off-by: Dharageswari R <dharageswari.r@intel.com>
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-12-08 17:57:51 +00:00
Jeeja KP 84c9e2836a ASoC: Intel: Skylake: Correct the runtime handler behaviour
On runtime pm resume, we need to download the firmware, also on
suspend we need to ensure all the interrupts from controller and
DSP are disabled.

Also since we download the firmware on resume, we don't need to do
so on init, so remove that bit

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-10-09 11:19:00 +01:00
Subhransu S. Prusty b81fd26359 ASoC: Intel: Add Skylake IPC library
This adds base SKL IPC library which uses common SST IPC lib.
Here we add definition for IPC types, sending and receiving IPC messages
from aDSP, handling interrupt, sending different types of messages etc

Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-07-09 18:33:23 +01:00