5f3a432a44
clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()
...
Pass the mode pin states from the SoC-specific CPG/MSSR driver to the
R-Car Gen3 CPG driver core, as their state will be needed to make some
core clock configuration decisions.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-21 11:12:23 +01:00
c013fc7d23
clk: renesas: r8a7796: Reformat core clock table
...
For easier comparison with other clock drivers.
No functional changes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-21 11:12:22 +01:00
89aa58a395
clk: renesas: r8a7796: Correct name of watchdog clock
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There's only a single watchdog clock, and it's named "rwdt".
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-21 11:12:21 +01:00
6c8a931294
clk: renesas: r8a7796: Add IMR clocks
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Add the IMR[0-1] clocks to the R8A7796 CPG/MSSR driver.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
[geert: Correct parent clocks]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-06 11:48:33 +01:00
d963654e10
clk: renesas: r8a7796: Add IIC-DVFS clock
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This patch adds DVFS clock for R8A7796 SoC.
Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com>
Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-01-27 08:59:24 +01:00
e6bdf28eff
clk: renesas: r8a7796: Add MSIOF controller clocks
...
This patch adds MSIOF{0,1,2,3} clocks for R8A7796 SoC.
Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27 10:56:08 +01:00
0ece46c24f
clk: renesas: r8a7796: Add CAN FD peripheral clock
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Based on a patch for r8a7795 by Ramesh Shanmugasundaram.
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27 10:56:08 +01:00
9e620beecd
clk: renesas: r8a7796: Add CANFD clock
...
Based on a patch for r8a7795 by Ramesh Shanmugasundaram.
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27 10:56:07 +01:00
e00d20c99d
clk: renesas: r8a7796: Add CAN peripheral clock
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Based on a patch for r8a7795 by Ramesh Shanmugasundaram.
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27 10:56:07 +01:00
e6e3558626
clk: renesas: r8a7796: Add VIN clocks
...
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-07 15:16:18 +01:00
5fccac6d94
clk: renesas: r8a7796: Add CSI2 clocks
...
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-07 15:16:17 +01:00
a05de66ea6
Merge branch 'rcar-rst' into clk-renesas-for-v4.10
...
soc: renesas: Add R-Car RST driver for obtaining mode pin state
2016-11-02 20:53:26 +01:00
05972d48d2
clk: renesas: r8a7796: Obtain mode pin values from R-Car RST driver
...
Obtain the values of the mode pins from the R-Car RST driver, which
relies on the presence in DT of a device node for the RST module.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2016-11-02 20:43:56 +01:00
dbdcc4f996
clk: renesas: r8a7796: Add DU and LVDS clocks
...
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-02 20:40:08 +01:00
88ddc1f8e3
clk: renesas: r8a7796: Add VSP clocks
...
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-02 20:40:07 +01:00
f4407a6e26
clk: renesas: r8a7796: Add FCP clocks
...
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-02 20:40:07 +01:00
cf31bc71c0
clk: renesas: r8a7796: Add DRIF clock
...
This patch adds DRIF module clocks for r8a7796 SoC.
Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-02 20:39:55 +01:00
878f8baa02
clk: renesas: r8a7796: Add I2C clocks
...
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-10-17 15:56:21 +02:00
28aa831949
clk: renesas: r8a7796: Add HSCIF clocks
...
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-10-17 15:56:21 +02:00
951456c37d
clk: renesas: r8a7796: Add SCIF clocks
...
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-10-17 15:56:20 +02:00
cf8fe97cad
clk: renesas: r8a7796: Add SYS-DMAC clocks
...
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-10-17 15:56:20 +02:00
5fad71f58f
clk: renesas: r8a7796: Add CMT clocks
...
This patch adds CMT module clocks for r8a7796 SoC.
Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-12 11:08:01 +02:00
5576df81d2
clk: renesas: r8a7796: Add RAVB clock
...
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-12 11:08:00 +02:00
5086b0d6ce
clk: renesas: r8a7796: Add THS/TSC clock
...
Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-05 14:16:25 +02:00
0749698133
clk: renesas: r8a7796: Add SDIF clocks
...
This patch adds SDIF clocks for R8A7796 SoC.
Based on work by Ai Kyuse and Yoshihiro Shimoda for the r8a7795 SoC.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-08-23 10:30:41 +02:00
4e09508a89
clk: renesas: r8a7796: Add GPIO clocks
...
Add GPIO clocks for the R8A7796 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-08-19 09:38:40 +02:00
b51d527501
clk: renesas: r8a7796: Add watchdog module clock
...
Add the module clock for the Watchdog Timer (WDT) controller on the
Renesas R-Car M3-W (r8a7796) SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-08-09 09:53:47 +02:00
2570d4005d
clk: renesas: r8a7796: Add watchdog core clocks
...
Add all core clocks related to the Watchdog Timer (WDT) controller on
the Renesas R-Car M3-W (r8a7796) SoC: OSC, Internal RCLK, and RCLK.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-08-09 09:53:47 +02:00
e4e2d7c388
clk: renesas: cpg-mssr: Add support for R-Car M3-W
...
Initial support for R-Car M3-W (r8a7796), including basic core clocks,
and SCIF2 (console) and INTC-AP (GIC) module clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
2016-06-06 11:58:35 +02:00
Geert Uytterhoeven