Commit "ARM: pxa: arbitrarily set first interrupt number" broke viper
and zeus boards which still refer to PXA_ISA_IRQ() macro. Redefine
the macro, which declares the legacy interrupts from 0 to 15.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Olof Johansson <olof@lixom.net>
As IRQ0, the legacy timer interrupt should not be used as an interrupt
number, shift the interrupts by a fixed number.
As we had in a special case a shift of 16 when ISA bus was used on a
PXA, use that value as the first interrupt number, regardless of ISA or
not.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
PXA95x isn't widely used. And it adds the effort on supporting
multiple platform. So remove it.
The assumption is that nobody will miss this support. If you are
reading this text because you actually require pxa95x support on
a new kernel, we can work out a way to revert this patch or add
support to the mmp platform.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
NR_BUILTIN_GPIO is both defined in arch-pxa and arch-mmp. Now replace it
with PXA_NR_BUILTIN_GPIO and MMP_NR_BUILTIN_GPIO.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
GPIO0 and GPIO1 are linked to unique interrupt line in PXA series,
others are linked to another interrupt line. All GPIO are linked to one
interrupt line in MMP series.
Since gpio driver is shared between PXA series and MMP series, define
GPIO0 and GPIO1 as chained interrupt chip. So we can move out gpio code
from irq.c to gpio-pxa.c.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Avoid potential naming confliction since multiple architecture will be built
in a single kernel.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Thanks Dmitry for providing a fix to the original code.
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
This fixes the failure to register the IRQ_RTCAlrm alarm as a wakeup
event. It is misinterpreted as a gpio irq not a PWER bitmask. Fixed
this by converting the incorrect IRQ_TO_IRQ() to a correct version of
irq_to_gpio().
Reported-by: Nick Bane <nickbane1@gmail.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
The core of PXA955 is PJ4. Add new PJ4 support. And add new macro
CONFIG_PXA95x.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Define all IRQs in irqs.h. If some IRQs are sharing one IRQ number, define
them together. If some IRQs are sharing same name with different IRQ number,
define different IRQ.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Cc: Eric Miao <eric.y.miao@gmail.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
IRQ_LOCOMO_* are never used elsewhere, remove these definitions. As well
as the cascade of these IRQs. IRQ_LOCOMO_*_BASE changed to IRQ_LOCOMO_*.
IRQ_LOCOMO_LT and IRQ_LOCOMO_SPI are likely to be used in a same way as
IRQ_LOCOMO_KEY.
IRQ_LOCOMO_GPIO and the demultiplex handler should really be living
somewhere else.
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
It is not necessary and is over-complicated for IRQ_LOCOMO_KEY to
be a cascaded IRQ of IRQ_LOCOMO_KEY_BASE. Removed and introduced
locomokbd_{open,close} for masking/unmasking of the keyboard IRQ.
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
So, again against latest pxa-linux-2.6/devel, with the following
changes:
* Move to __raw_readl/__raw_writel for FPGA/CPLD register access
* Change Toppoly LCD config to be selectable at run time rather than
compile time.
* Remove currently unused irq device suspend/resume functions.
* Strip out unnecessary/duplicated #includes.
* Some code style cleanups.
Balloon3 (http://balloonboard.org/) base machine support
Signed-off-by: Jonathan McDowell <noodles@earth.li>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
PXA93x/950 has additional 64 GPIOs, each is a secondary interrupt
source for IRQ_GPIO_2_x, extend PXA_GPIO_IRQ_{BASE,NUM}.
PXA93x/950 specific IRQ definitions are added as well.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
The default value is 16 IRQs. Zylonite needs 32, ASIC3 based boards need 70.
My problem is still that due to the way IRQ_GPIO is hardcoded, ASIC3 based boards
need 70 IRQs starting at IRQ_BOARD_START. If I define ASIC3 IRQs similar to LoCoMo
or SA1111, things break as soon as something selects PXA_HAVE_BOARD_IRQS.
Increasing the default number of board IRQs to 70 instead doesn't seem very nice.
Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: Eric Miao <eric.miao@marvell.com>
arch/arm/mach-pxa/include/mach/irqs.h:193:1: warning: "NR_IRQS" redefined
arch/arm/mach-pxa/include/mach/irqs.h:263:1: warning: this is the location of the previous definition
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Allow PXA IRQs to be numbered starting at 16, leaving 0 to 15 for the
ISA IRQs, if needed.
This patch depends on RMK's PXA_HAVE_BOARD_IRQS patch.
Signed-off-by: Marc Zyngier <marc.zyngier@altran.com>
Acked-by: Russel King <linux@arm.linux.org.uk>
Acked-by: Eric Miao <eric.y.miao@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Robert Jarzmik