3 Commits

Author	SHA1	Message	Date
Chen-Yu Tsai	c4be8c68e6	clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM ... The PRCM takes PLL_PERIPH0 as one of its parents for the AR100 clock. As such we need to be able to describe this relationship in the device tree. Export the PLL_PERIPH0 clock so we can reference it in the PRCM node. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>	2017-05-31 21:57:27 +02:00
Icenowy Zheng	9be1c8afb4	clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver ... Allwinner H5 is a SoC that features a design which keeps the peripheral compatible with H3, so that it have also a CCU like the one on H3 -- only one bus gate/reset is added, and the mmc sample/output phases are removed because of MMC controller update. Add its support in our existing H3 CCU driver. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>	2017-03-06 10:25:56 +01:00
Maxime Ripard	0577e4853b	clk: sunxi-ng: Add H3 clocks ... Add the list of clocks and resets found in the H3 CCU. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-14-maxime.ripard@free-electrons.com	2016-07-08 18:05:12 -07:00