Use the virtual address of the memory hardware uses, not the address for
the container of that memory.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Cc: stable <stable@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Adds support for controllers that use 64-byte contexts. The following context
data structures are affected by this: Device, Input, Input Control, Endpoint,
and Slot. To accommodate the use of either 32 or 64-byte contexts, a Device or
Input context can only be accessed through functions which look-up and return
pointers to their contained contexts.
Signed-off-by: John Youn <johnyoun@synopsys.com>
Acked-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Make sure the xHCI output device context is 64-byte aligned. Previous
code was using the same structure for both the output device context and
the input control context. Since the structure had 32 bytes of flags
before the device context, the output device context wouldn't be 64-byte
aligned. Define a new structure to use for the output device context and
clean up the debugging for these two structures.
The copy of the device context in the input control context does *not*
need to be 64-byte aligned.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
There are several xHCI data structures that use two 32-bit fields to
represent a 64-bit address. Since some architectures don't support 64-bit
PCI writes, the fields need to be written in two 32-bit writes. The xHCI
specification says that if a platform is incapable of generating 64-bit
writes, software must write the low 32-bits first, then the high 32-bits.
Hardware that supports 64-bit addressing will wait for the high 32-bit
write before reading the revised value, and hardware that only supports
32-bit writes will ignore the high 32-bit write.
Previous xHCI code represented 64-bit addresses with two u32 values. This
lead to buggy code that would write the 32-bits in the wrong order, or
forget to write the upper 32-bits. Change the two u32s to one u64 and
create a function call to write all 64-bit addresses in the proper order.
This new function could be modified in the future if all platforms support
64-bit writes.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Without this change the loops won't start
Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Cc: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
The packed attribute allows gcc to muck with the alignment of data
structures, which may lead to byte-wise writes that break atomicity of
writes. Packed should only be used when the compile may add undesired
padding to the structure. Each element of the structure will be aligned
by C based on its size and the size of the elements around it. E.g. a u64
would be aligned on an 8 byte boundary, the next u32 would be aligned on a
four byte boundary, etc.
Since most of the xHCI structures contain only u32 bit values, removing
the packed attribute for them should be harmless. (A future patch will
change some of the twin 32-bit address fields to one 64-bit field, but all
those places have an even number of 32-bit fields before them, so the
alignment should be correct.) Add BUILD_BUG_ON statements to check that
the compiler doesn't add padding to the data structures that have a
hardware-defined layout.
While we're modifying the registers, change the name of intr_reg to
xhci_intr_reg to avoid global conflicts.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Make all globally visible functions start with xhci_ and mark functions as
static if they're only called within the same C file. Fix some long lines
while we're at it.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Turns out someone never built this code on a 64bit platform.
Someone owes me a beer...
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
xHCI needs to get a "Slot ID" from the host controller and allocate other
data structures for every USB device. Make usb_alloc_dev() and
usb_release_dev() allocate and free these device structures. After
setting up the xHC device structures, usb_alloc_dev() must wait for the
hardware to respond to an Enable Slot command. usb_alloc_dev() fires off
a Disable Slot command and does not wait for it to complete.
When the USB core wants to choose an address for the device, the xHCI
driver must issue a Set Address command and wait for an event for that
command.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Add functionality for getting port status and hub descriptor for xHCI root
hubs. This is WIP because the USB 3.0 hub descriptor is different from
the USB 2.0 hub descriptor. For now, we lie about the root hub descriptor
because the changes won't effect how the core talks to the root hub.
Later we will need to add the USB 3.0 hub descriptor for real hubs, and
this code might change.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
xHCI host controllers can optionally implement a no-op test. This
simple test ensures the OS has correctly setup all basic data structures
and can correctly respond to interrupts from the host controller
hardware.
There are two rings exercised by the no-op test: the command ring, and
the event ring.
The host controller driver writes a no-op command TRB to the command
ring, and rings the doorbell for the command ring (the first entry in
the doorbell array). The hardware receives this event, places a command
completion event on the event ring, and fires an interrupt.
The host controller driver sees the interrupt, and checks the event ring
for TRBs it can process, and sees the command completion event. (See
the rules in xhci-ring.c for who "owns" a TRB. This is a simplified set
of rules, and may not contain all the details that are in the xHCI 0.95
spec.)
A timer fires every 60 seconds to debug the state of the hardware and
command and event rings. This timer only runs if
CONFIG_USB_XHCI_HCD_DEBUGGING is 'y'.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Allocate basic xHCI host controller data structures. For every xHC, there
is a command ring, an event ring, and a doorbell array.
The doorbell array is used to notify the host controller that work has
been enqueued onto one of the rings. The host controller driver enqueues
commands on the command ring. The HW enqueues command completion events
on the event ring and interrupts the system (currently using PCI
interrupts, although the xHCI HW will use MSI interrupts eventually).
All rings and the doorbell array must be allocated by the xHCI host
controller driver.
Each ring is comprised of one or more segments, which consists of 16-byte
Transfer Request Blocks (TRBs) that can be chained to form a Transfer
Descriptor (TD) that represents a multiple-buffer request. Segments are
linked into a ring using Link TRBs, which means they are dynamically
growable.
The producer of the ring enqueues a TD by writing one or more TRBs in the
ring and toggling the TRB cycle bit for each TRB. The consumer knows it
can process the TRB when the cycle bit matches its internal consumer cycle
state for the ring. The consumer cycle state is toggled an odd amount of
times in the ring.
An example ring (a ring must have a minimum of 16 TRBs on it, but that's
too big to draw in ASCII art):
chain cycle
bit bit
------------------------
| TD A TRB 1 | 1 | 1 |<------------- <-- consumer dequeue ptr
------------------------ | consumer cycle state = 1
| TD A TRB 2 | 1 | 1 | |
------------------------ |
| TD A TRB 3 | 0 | 1 | segment 1 |
------------------------ |
| TD B TRB 1 | 1 | 1 | |
------------------------ |
| TD B TRB 2 | 0 | 1 | |
------------------------ |
| Link TRB | 0 | 1 |----- |
------------------------ | |
| |
chain cycle | |
bit bit | |
------------------------ | |
| TD C TRB 1 | 0 | 1 |<---- |
------------------------ |
| TD D TRB 1 | 1 | 1 | |
------------------------ |
| TD D TRB 2 | 1 | 1 | segment 2 |
------------------------ |
| TD D TRB 3 | 1 | 1 | |
------------------------ |
| TD D TRB 4 | 1 | 1 | |
------------------------ |
| Link TRB | 1 | 1 |----- |
------------------------ | |
| |
chain cycle | |
bit bit | |
------------------------ | |
| TD D TRB 5 | 1 | 1 |<---- |
------------------------ |
| TD D TRB 6 | 0 | 1 | |
------------------------ |
| TD E TRB 1 | 0 | 1 | segment 3 |
------------------------ |
| | 0 | 0 | | <-- producer enqueue ptr
------------------------ |
| | 0 | 0 | |
------------------------ |
| Link TRB | 0 | 0 |---------------
------------------------
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This is the first of many patches to add support for USB 3.0 devices and
the hardware that implements the eXtensible Host Controller Interface
(xHCI) 0.95 specification. This specification is not yet publicly
available, but companies can receive a copy by becoming an xHCI
Contributor (see http://www.intel.com/technology/usb/xhcispec.htm).
No xHCI hardware has made it onto the market yet, but these patches have
been tested under the Fresco Logic host controller prototype.
This patch adds the xHCI register sets, which are grouped into five sets:
- Generic PCI registers
- Host controller "capabilities" registers (cap_regs) short
- Host controller "operational" registers (op_regs)
- Host controller "runtime" registers (run_regs)
- Host controller "doorbell" registers
These some of these registers may be virtualized if the Linux driver is
running under a VM. Virtualization has not been tested for this patch.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Sarah Sharp