/*
 * Device Tree Source for Renesas r8a7779
 *
 * Copyright (C) 2013 Renesas Solutions Corp.
 * Copyright (C) 2013 Simon Horman
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

/include/ "skeleton.dtsi"

#include <dt-bindings/clock/r8a7779-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "renesas,r8a7779";
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clock-frequency = <1000000000>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			clock-frequency = <1000000000>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <2>;
			clock-frequency = <1000000000>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <3>;
			clock-frequency = <1000000000>;
		};
	};

	aliases {
		spi0 = &hspi0;
		spi1 = &hspi1;
		spi2 = &hspi2;
	};

	gic: interrupt-controller@f0001000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0xf0001000 0x1000>,
		      <0xf0000100 0x100>;
	};

	timer@f0000600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0xf0000600 0x20>;
		interrupts = <GIC_PPI 13
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
		clocks = <&cpg_clocks R8A7779_CLK_ZS>;
	};

	gpio0: gpio@ffc40000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc40000 0x2c>;
		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 0 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio1: gpio@ffc41000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc41000 0x2c>;
		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 32 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio2: gpio@ffc42000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc42000 0x2c>;
		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 64 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio3: gpio@ffc43000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc43000 0x2c>;
		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 96 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio4: gpio@ffc44000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc44000 0x2c>;
		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 128 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio5: gpio@ffc45000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc45000 0x2c>;
		interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 160 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio6: gpio@ffc46000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc46000 0x2c>;
		interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 192 9>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	irqpin0: interrupt-controller@fe78001c {
		compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
		#interrupt-cells = <2>;
		status = "disabled";
		interrupt-controller;
		reg = <0xfe78001c 4>,
			<0xfe780010 4>,
			<0xfe780024 4>,
			<0xfe780044 4>,
			<0xfe780064 4>,
			<0xfe780000 4>;
		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
		sense-bitfield-width = <2>;
	};

	i2c0: i2c@ffc70000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7779";
		reg = <0xffc70000 0x1000>;
		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	i2c1: i2c@ffc71000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7779";
		reg = <0xffc71000 0x1000>;
		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	i2c2: i2c@ffc72000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7779";
		reg = <0xffc72000 0x1000>;
		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	i2c3: i2c@ffc73000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7779";
		reg = <0xffc73000 0x1000>;
		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif0: serial@ffe40000 {
		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe40000 0x100>;
		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif1: serial@ffe41000 {
		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe41000 0x100>;
		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif2: serial@ffe42000 {
		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe42000 0x100>;
		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif3: serial@ffe43000 {
		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe43000 0x100>;
		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif4: serial@ffe44000 {
		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe44000 0x100>;
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif5: serial@ffe45000 {
		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe45000 0x100>;
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	pfc: pfc@fffc0000 {
		compatible = "renesas,pfc-r8a7779";
		reg = <0xfffc0000 0x23c>;
	};

	thermal@ffc48000 {
		compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
		reg = <0xffc48000 0x38>;
	};

	tmu0: timer@ffd80000 {
		compatible = "renesas,tmu-r8a7779", "renesas,tmu";
		reg = <0xffd80000 0x30>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;

		#renesas,channels = <3>;

		status = "disabled";
	};

	tmu1: timer@ffd81000 {
		compatible = "renesas,tmu-r8a7779", "renesas,tmu";
		reg = <0xffd81000 0x30>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;

		#renesas,channels = <3>;

		status = "disabled";
	};

	tmu2: timer@ffd82000 {
		compatible = "renesas,tmu-r8a7779", "renesas,tmu";
		reg = <0xffd82000 0x30>;
		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;

		#renesas,channels = <3>;

		status = "disabled";
	};

	sata: sata@fc600000 {
		compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
		reg = <0xfc600000 0x2000>;
		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp1_clks R8A7779_CLK_SATA>;
		power-domains = <&cpg_clocks>;
	};

	sdhi0: sd@ffe4c000 {
		compatible = "renesas,sdhi-r8a7779";
		reg = <0xffe4c000 0x100>;
		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	sdhi1: sd@ffe4d000 {
		compatible = "renesas,sdhi-r8a7779";
		reg = <0xffe4d000 0x100>;
		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	sdhi2: sd@ffe4e000 {
		compatible = "renesas,sdhi-r8a7779";
		reg = <0xffe4e000 0x100>;
		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	sdhi3: sd@ffe4f000 {
		compatible = "renesas,sdhi-r8a7779";
		reg = <0xffe4f000 0x100>;
		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	hspi0: spi@fffc7000 {
		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
		reg = <0xfffc7000 0x18>;
		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	hspi1: spi@fffc8000 {
		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
		reg = <0xfffc8000 0x18>;
		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	hspi2: spi@fffc6000 {
		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
		reg = <0xfffc6000 0x18>;
		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	du: display@fff80000 {
		compatible = "renesas,du-r8a7779";
		reg = <0 0xfff80000 0 0x40000>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp1_clks R8A7779_CLK_DU>;
		power-domains = <&cpg_clocks>;
		status = "disabled";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				du_out_rgb0: endpoint {
				};
			};
			port@1 {
				reg = <1>;
				du_out_rgb1: endpoint {
				};
			};
		};
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* External root clock */
		extal_clk: extal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			/* This value must be overriden by the board. */
			clock-frequency = <0>;
		};

		/* External SCIF clock */
		scif_clk: scif {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			/* This value must be overridden by the board. */
			clock-frequency = <0>;
			status = "disabled";
		};

		/* Special CPG clocks */
		cpg_clocks: clocks@ffc80000 {
			compatible = "renesas,r8a7779-cpg-clocks";
			reg = <0xffc80000 0x30>;
			clocks = <&extal_clk>;
			#clock-cells = <1>;
			clock-output-names = "plla", "z", "zs", "s",
					     "s1", "p", "b", "out";
			#power-domain-cells = <0>;
		};

		/* Fixed factor clocks */
		i_clk: i {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
		};
		s3_clk: s3 {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <8>;
			clock-mult = <1>;
		};
		s4_clk: s4 {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <16>;
			clock-mult = <1>;
		};
		g_clk: g {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <24>;
			clock-mult = <1>;
		};

		/* Gate clocks */
		mstp0_clks: clocks@ffc80030 {
			compatible = "renesas,r8a7779-mstp-clocks",
				     "renesas,cpg-mstp-clocks";
			reg = <0xffc80030 4>;
			clocks = <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7779_CLK_HSPI R8A7779_CLK_TMU2
				R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
				R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
				R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
				R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
				R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
				R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
				R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
			>;
			clock-output-names =
				"hspi", "tmu2", "tmu1", "tmu0", "hscif1",
				"hscif0", "scif5", "scif4", "scif3", "scif2",
				"scif1", "scif0", "i2c3", "i2c2", "i2c1",
				"i2c0";
		};
		mstp1_clks: clocks@ffc80034 {
			compatible = "renesas,r8a7779-mstp-clocks",
				     "renesas,cpg-mstp-clocks";
			reg = <0xffc80034 4>, <0xffc80044 4>;
			clocks = <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_S>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7779_CLK_USB01 R8A7779_CLK_USB2
				R8A7779_CLK_DU R8A7779_CLK_VIN2
				R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
				R8A7779_CLK_ETHER R8A7779_CLK_SATA
				R8A7779_CLK_PCIE R8A7779_CLK_VIN3
			>;
			clock-output-names =
				"usb01", "usb2",
				"du", "vin2",
				"vin1", "vin0",
				"ether", "sata",
				"pcie", "vin3";
		};
		mstp3_clks: clocks@ffc8003c {
			compatible = "renesas,r8a7779-mstp-clocks",
				     "renesas,cpg-mstp-clocks";
			reg = <0xffc8003c 4>;
			clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
				 <&s4_clk>, <&s4_clk>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
				R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
				R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
			>;
			clock-output-names =
				"sdhi3", "sdhi2", "sdhi1", "sdhi0",
				"mmc1", "mmc0";
		};
	};
};