/* * Device Tree Include file for Marvell Armada XP family SoC * * Copyright (C) 2012 Marvell * * Lior Amsalem * Gregory CLEMENT * Thomas Petazzoni * Ben Dooks * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This file is distributed in the hope that it will be useful * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Or, alternatively * * b) Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use * copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following * conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Contains definitions specific to the Armada XP SoC that are not * common to all Armada SoCs. */ #include "armada-370-xp.dtsi" / { #address-cells = <2>; #size-cells = <2>; model = "Marvell Armada XP family SoC"; compatible = "marvell,armadaxp", "marvell,armada-370-xp"; aliases { serial2 = &uart2; serial3 = &uart3; }; soc { compatible = "marvell,armadaxp-mbus", "simple-bus"; bootrom { compatible = "marvell,bootrom"; reg = ; }; internal-regs { sdramc@1400 { compatible = "marvell,armada-xp-sdram-controller"; reg = <0x1400 0x500>; }; L2: l2-cache { compatible = "marvell,aurora-system-cache"; reg = <0x08000 0x1000>; cache-id-part = <0x100>; cache-level = <2>; cache-unified; wt-override; }; uart2: serial@12200 { compatible = "snps,dw-apb-uart"; pinctrl-0 = <&uart2_pins>; pinctrl-names = "default"; reg = <0x12200 0x100>; reg-shift = <2>; interrupts = <43>; reg-io-width = <1>; clocks = <&coreclk 0>; status = "disabled"; }; uart3: serial@12300 { compatible = "snps,dw-apb-uart"; pinctrl-0 = <&uart3_pins>; pinctrl-names = "default"; reg = <0x12300 0x100>; reg-shift = <2>; interrupts = <44>; reg-io-width = <1>; clocks = <&coreclk 0>; status = "disabled"; }; systemc: system-controller@18200 { compatible = "marvell,armada-370-xp-system-controller"; reg = <0x18200 0x500>; }; gateclk: clock-gating-control@18220 { compatible = "marvell,armada-xp-gating-clock"; reg = <0x18220 0x4>; clocks = <&coreclk 0>; #clock-cells = <1>; }; coreclk: mvebu-sar@18230 { compatible = "marvell,armada-xp-core-clock"; reg = <0x18230 0x08>; #clock-cells = <1>; }; thermal: thermal@182b0 { compatible = "marvell,armadaxp-thermal"; reg = <0x182b0 0x4 0x184d0 0x4>; status = "okay"; }; cpuclk: clock-complex@18700 { #clock-cells = <1>; compatible = "marvell,armada-xp-cpu-clock"; reg = <0x18700 0x24>, <0x1c054 0x10>; clocks = <&coreclk 1>; }; cpu-config@21000 { compatible = "marvell,armada-xp-cpu-config"; reg = <0x21000 0x8>; }; eth2: ethernet@30000 { compatible = "marvell,armada-xp-neta"; reg = <0x30000 0x4000>; interrupts = <12>; clocks = <&gateclk 2>; status = "disabled"; }; usb2: usb@52000 { compatible = "marvell,orion-ehci"; reg = <0x52000 0x500>; interrupts = <47>; clocks = <&gateclk 20>; status = "disabled"; }; xor1: xor@60900 { compatible = "marvell,orion-xor"; reg = <0x60900 0x100 0x60b00 0x100>; clocks = <&gateclk 22>; status = "okay"; xor10 { interrupts = <51>; dmacap,memcpy; dmacap,xor; }; xor11 { interrupts = <52>; dmacap,memcpy; dmacap,xor; dmacap,memset; }; }; ethernet@70000 { compatible = "marvell,armada-xp-neta"; }; ethernet@74000 { compatible = "marvell,armada-xp-neta"; }; cesa: crypto@90000 { compatible = "marvell,armada-xp-crypto"; reg = <0x90000 0x10000>; reg-names = "regs"; interrupts = <48>, <49>; clocks = <&gateclk 23>, <&gateclk 23>; clock-names = "cesa0", "cesa1"; marvell,crypto-srams = <&crypto_sram0>, <&crypto_sram1>; marvell,crypto-sram-size = <0x800>; }; bm: bm@c0000 { compatible = "marvell,armada-380-neta-bm"; reg = <0xc0000 0xac>; clocks = <&gateclk 13>; internal-mem = <&bm_bppi>; status = "disabled"; }; xor0: xor@f0900 { compatible = "marvell,orion-xor"; reg = <0xF0900 0x100 0xF0B00 0x100>; clocks = <&gateclk 28>; status = "okay"; xor00 { interrupts = <94>; dmacap,memcpy; dmacap,xor; }; xor01 { interrupts = <95>; dmacap,memcpy; dmacap,xor; dmacap,memset; }; }; }; crypto_sram0: sa-sram0 { compatible = "mmio-sram"; reg = ; clocks = <&gateclk 23>; #address-cells = <1>; #size-cells = <1>; ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>; }; crypto_sram1: sa-sram1 { compatible = "mmio-sram"; reg = ; clocks = <&gateclk 23>; #address-cells = <1>; #size-cells = <1>; ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>; }; bm_bppi: bm-bppi { compatible = "mmio-sram"; reg = ; ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; #address-cells = <1>; #size-cells = <1>; clocks = <&gateclk 13>; no-memory-wc; status = "disabled"; }; }; clocks { /* 25 MHz reference crystal */ refclk: oscillator { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; }; }; &i2c0 { compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; reg = <0x11000 0x100>; }; &i2c1 { compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; reg = <0x11100 0x100>; }; &mpic { reg = <0x20a00 0x2d0>, <0x21070 0x58>; }; &timer { compatible = "marvell,armada-xp-timer"; clocks = <&coreclk 2>, <&refclk>; clock-names = "nbclk", "fixed"; }; &watchdog { compatible = "marvell,armada-xp-wdt"; clocks = <&coreclk 2>, <&refclk>; clock-names = "nbclk", "fixed"; }; &cpurst { reg = <0x20800 0x20>; }; &usb0 { clocks = <&gateclk 18>; }; &usb1 { clocks = <&gateclk 19>; }; &pinctrl { ge0_gmii_pins: ge0-gmii-pins { marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp11", "mpp12", "mpp13", "mpp14", "mpp15", "mpp16", "mpp17", "mpp18", "mpp19", "mpp20", "mpp21", "mpp22", "mpp23"; marvell,function = "ge0"; }; ge0_rgmii_pins: ge0-rgmii-pins { marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp11"; marvell,function = "ge0"; }; ge1_rgmii_pins: ge1-rgmii-pins { marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16", "mpp17", "mpp18", "mpp19", "mpp20", "mpp21", "mpp22", "mpp23"; marvell,function = "ge1"; }; sdio_pins: sdio-pins { marvell,pins = "mpp30", "mpp31", "mpp32", "mpp33", "mpp34", "mpp35"; marvell,function = "sd0"; }; spi0_pins: spi0-pins { marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39"; marvell,function = "spi0"; }; spi1_pins: spi1-pins { marvell,pins = "mpp13", "mpp14", "mpp16", "mpp17"; marvell,function = "spi1"; }; uart2_pins: uart2-pins { marvell,pins = "mpp42", "mpp43"; marvell,function = "uart2"; }; uart3_pins: uart3-pins { marvell,pins = "mpp44", "mpp45"; marvell,function = "uart3"; }; }; &spi0 { compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; pinctrl-0 = <&spi0_pins>; pinctrl-names = "default"; }; &spi1 { compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; pinctrl-0 = <&spi1_pins>; pinctrl-names = "default"; };