/* * Copyright 2013 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. */ #include "skeleton.dtsi" #include "vf610-pinfunc.h" #include / { aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; serial3 = &uart3; serial4 = &uart4; serial5 = &uart5; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; gpio3 = &gpio4; gpio4 = &gpio5; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a5"; device_type = "cpu"; reg = <0x0>; next-level-cache = <&L2>; }; }; clocks { #address-cells = <1>; #size-cells = <0>; sxosc { compatible = "fixed-clock"; clock-frequency = <32768>; }; fxosc { compatible = "fixed-clock"; clock-frequency = <24000000>; }; }; soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; interrupt-parent = <&intc>; ranges; aips0: aips-bus@40000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; reg = <0x40000000 0x70000>; ranges; intc: interrupt-controller@40002000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; #address-cells = <1>; #size-cells = <1>; interrupt-controller; reg = <0x40003000 0x1000>, <0x40002100 0x100>; }; L2: l2-cache@40006000 { compatible = "arm,pl310-cache"; reg = <0x40006000 0x1000>; cache-unified; cache-level = <2>; arm,data-latency = <1 1 1>; arm,tag-latency = <2 2 2>; }; uart0: serial@40027000 { compatible = "fsl,vf610-lpuart"; reg = <0x40027000 0x1000>; interrupts = <0 61 0x00>; clocks = <&clks VF610_CLK_UART0>; clock-names = "ipg"; status = "disabled"; }; uart1: serial@40028000 { compatible = "fsl,vf610-lpuart"; reg = <0x40028000 0x1000>; interrupts = <0 62 0x04>; clocks = <&clks VF610_CLK_UART1>; clock-names = "ipg"; status = "disabled"; }; uart2: serial@40029000 { compatible = "fsl,vf610-lpuart"; reg = <0x40029000 0x1000>; interrupts = <0 63 0x04>; clocks = <&clks VF610_CLK_UART2>; clock-names = "ipg"; status = "disabled"; }; uart3: serial@4002a000 { compatible = "fsl,vf610-lpuart"; reg = <0x4002a000 0x1000>; interrupts = <0 64 0x04>; clocks = <&clks VF610_CLK_UART3>; clock-names = "ipg"; status = "disabled"; }; dspi0: dspi0@4002c000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,vf610-dspi"; reg = <0x4002c000 0x1000>; interrupts = <0 67 0x04>; clocks = <&clks VF610_CLK_DSPI0>; clock-names = "dspi"; spi-num-chipselects = <5>; status = "disabled"; }; sai2: sai@40031000 { compatible = "fsl,vf610-sai"; reg = <0x40031000 0x1000>; interrupts = <0 86 0x04>; clocks = <&clks VF610_CLK_SAI2>; clock-names = "sai"; status = "disabled"; }; pit: pit@40037000 { compatible = "fsl,vf610-pit"; reg = <0x40037000 0x1000>; interrupts = <0 39 0x04>; clocks = <&clks VF610_CLK_PIT>; clock-names = "pit"; }; wdog@4003e000 { compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; reg = <0x4003e000 0x1000>; clocks = <&clks VF610_CLK_WDT>; clock-names = "wdog"; }; qspi0: quadspi@40044000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,vf610-qspi"; reg = <0x40044000 0x1000>; interrupts = <0 24 0x04>; clocks = <&clks VF610_CLK_QSPI0_EN>, <&clks VF610_CLK_QSPI0>; clock-names = "qspi_en", "qspi"; status = "disabled"; }; iomuxc: iomuxc@40048000 { compatible = "fsl,vf610-iomuxc"; reg = <0x40048000 0x1000>; #gpio-range-cells = <3>; }; gpio1: gpio@40049000 { compatible = "fsl,vf610-gpio"; reg = <0x40049000 0x1000 0x400ff000 0x40>; interrupts = <0 107 0x04>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&iomuxc 0 0 32>; }; gpio2: gpio@4004a000 { compatible = "fsl,vf610-gpio"; reg = <0x4004a000 0x1000 0x400ff040 0x40>; interrupts = <0 108 0x04>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&iomuxc 0 32 32>; }; gpio3: gpio@4004b000 { compatible = "fsl,vf610-gpio"; reg = <0x4004b000 0x1000 0x400ff080 0x40>; interrupts = <0 109 0x04>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&iomuxc 0 64 32>; }; gpio4: gpio@4004c000 { compatible = "fsl,vf610-gpio"; reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; interrupts = <0 110 0x04>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&iomuxc 0 96 32>; }; gpio5: gpio@4004d000 { compatible = "fsl,vf610-gpio"; reg = <0x4004d000 0x1000 0x400ff100 0x40>; interrupts = <0 111 0x04>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&iomuxc 0 128 7>; }; anatop@40050000 { compatible = "fsl,vf610-anatop"; reg = <0x40050000 0x1000>; }; i2c0: i2c@40066000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,vf610-i2c"; reg = <0x40066000 0x1000>; interrupts =<0 71 0x04>; clocks = <&clks VF610_CLK_I2C0>; clock-names = "ipg"; status = "disabled"; }; clks: ccm@4006b000 { compatible = "fsl,vf610-ccm"; reg = <0x4006b000 0x1000>; #clock-cells = <1>; }; }; aips1: aips-bus@40080000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x40080000 0x80000>; ranges; uart4: serial@400a9000 { compatible = "fsl,vf610-lpuart"; reg = <0x400a9000 0x1000>; interrupts = <0 65 0x04>; clocks = <&clks VF610_CLK_UART4>; clock-names = "ipg"; status = "disabled"; }; uart5: serial@400aa000 { compatible = "fsl,vf610-lpuart"; reg = <0x400aa000 0x1000>; interrupts = <0 66 0x04>; clocks = <&clks VF610_CLK_UART5>; clock-names = "ipg"; status = "disabled"; }; fec0: ethernet@400d0000 { compatible = "fsl,mvf600-fec"; reg = <0x400d0000 0x1000>; interrupts = <0 78 0x04>; clocks = <&clks VF610_CLK_ENET0>, <&clks VF610_CLK_ENET0>, <&clks VF610_CLK_ENET>; clock-names = "ipg", "ahb", "ptp"; status = "disabled"; }; fec1: ethernet@400d1000 { compatible = "fsl,mvf600-fec"; reg = <0x400d1000 0x1000>; interrupts = <0 79 0x04>; clocks = <&clks VF610_CLK_ENET1>, <&clks VF610_CLK_ENET1>, <&clks VF610_CLK_ENET>; clock-names = "ipg", "ahb", "ptp"; status = "disabled"; }; }; }; };