/* * arch/arm/mach-spear6xx/spear6xx.c * * SPEAr6XX machines common source file * * Copyright (C) 2009 ST Microelectronics * Rajeev Kumar<rajeev-dlh.kumar@st.com> * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ #include <linux/types.h> #include <linux/amba/pl061.h> #include <linux/ptrace.h> #include <linux/io.h> #include <asm/hardware/vic.h> #include <asm/irq.h> #include <asm/mach/arch.h> #include <mach/generic.h> #include <mach/hardware.h> #include <mach/irqs.h> /* Add spear6xx machines common devices here */ /* uart device registration */ struct amba_device uart_device[] = { { .dev = { .init_name = "uart0", }, .res = { .start = SPEAR6XX_ICM1_UART0_BASE, .end = SPEAR6XX_ICM1_UART0_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, .irq = {IRQ_UART_0, NO_IRQ}, }, { .dev = { .init_name = "uart1", }, .res = { .start = SPEAR6XX_ICM1_UART1_BASE, .end = SPEAR6XX_ICM1_UART1_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, .irq = {IRQ_UART_1, NO_IRQ}, } }; /* gpio device registration */ static struct pl061_platform_data gpio_plat_data[] = { { .gpio_base = 0, .irq_base = SPEAR_GPIO0_INT_BASE, }, { .gpio_base = 8, .irq_base = SPEAR_GPIO1_INT_BASE, }, { .gpio_base = 16, .irq_base = SPEAR_GPIO2_INT_BASE, }, }; struct amba_device gpio_device[] = { { .dev = { .init_name = "gpio0", .platform_data = &gpio_plat_data[0], }, .res = { .start = SPEAR6XX_CPU_GPIO_BASE, .end = SPEAR6XX_CPU_GPIO_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, .irq = {IRQ_LOCAL_GPIO, NO_IRQ}, }, { .dev = { .init_name = "gpio1", .platform_data = &gpio_plat_data[1], }, .res = { .start = SPEAR6XX_ICM3_GPIO_BASE, .end = SPEAR6XX_ICM3_GPIO_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, .irq = {IRQ_BASIC_GPIO, NO_IRQ}, }, { .dev = { .init_name = "gpio2", .platform_data = &gpio_plat_data[2], }, .res = { .start = SPEAR6XX_ICM2_GPIO_BASE, .end = SPEAR6XX_ICM2_GPIO_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, .irq = {IRQ_APPL_GPIO, NO_IRQ}, } }; /* This will add devices, and do machine specific tasks */ void __init spear6xx_init(void) { /* nothing to do for now */ } /* This will initialize vic */ void __init spear6xx_init_irq(void) { vic_init((void __iomem *)VA_SPEAR6XX_CPU_VIC_PRI_BASE, 0, ~0, 0); vic_init((void __iomem *)VA_SPEAR6XX_CPU_VIC_SEC_BASE, 32, ~0, 0); } /* Following will create static virtual/physical mappings */ static struct map_desc spear6xx_io_desc[] __initdata = { { .virtual = VA_SPEAR6XX_ICM1_UART0_BASE, .pfn = __phys_to_pfn(SPEAR6XX_ICM1_UART0_BASE), .length = SZ_4K, .type = MT_DEVICE }, { .virtual = VA_SPEAR6XX_CPU_VIC_PRI_BASE, .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_PRI_BASE), .length = SZ_4K, .type = MT_DEVICE }, { .virtual = VA_SPEAR6XX_CPU_VIC_SEC_BASE, .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_SEC_BASE), .length = SZ_4K, .type = MT_DEVICE }, { .virtual = VA_SPEAR6XX_ICM3_SYS_CTRL_BASE, .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SYS_CTRL_BASE), .length = SZ_4K, .type = MT_DEVICE }, { .virtual = VA_SPEAR6XX_ICM3_MISC_REG_BASE, .pfn = __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE), .length = SZ_4K, .type = MT_DEVICE }, }; /* This will create static memory mapping for selected devices */ void __init spear6xx_map_io(void) { iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc)); /* This will initialize clock framework */ spear6xx_clk_init(); } static void __init spear6xx_timer_init(void) { char pclk_name[] = "pll3_48m_clk"; struct clk *gpt_clk, *pclk; /* get the system timer clock */ gpt_clk = clk_get_sys("gpt0", NULL); if (IS_ERR(gpt_clk)) { pr_err("%s:couldn't get clk for gpt\n", __func__); BUG(); } /* get the suitable parent clock for timer*/ pclk = clk_get(NULL, pclk_name); if (IS_ERR(pclk)) { pr_err("%s:couldn't get %s as parent for gpt\n", __func__, pclk_name); BUG(); } clk_set_parent(gpt_clk, pclk); clk_put(gpt_clk); clk_put(pclk); spear_setup_timer(); } struct sys_timer spear6xx_timer = { .init = spear6xx_timer_init, };