/* * Device Tree Source for the r8a7794 SoC * * Copyright (C) 2014 Renesas Electronics Corporation * Copyright (C) 2014 Ulrich Hecht * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any * kind, whether express or implied. */ #include #include #include / { compatible = "renesas,r8a7794"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; aliases { i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; spi0 = &qspi; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0>; clock-frequency = <1000000000>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <1>; clock-frequency = <1000000000>; }; }; gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x1000>, <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; }; gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; reg = <0 0xe6050000 0 0x50>; interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 0 32>; #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7794_CLK_GPIO0>; power-domains = <&cpg_clocks>; }; gpio1: gpio@e6051000 { compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; reg = <0 0xe6051000 0 0x50>; interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 32 26>; #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7794_CLK_GPIO1>; power-domains = <&cpg_clocks>; }; gpio2: gpio@e6052000 { compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; reg = <0 0xe6052000 0 0x50>; interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 64 32>; #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7794_CLK_GPIO2>; power-domains = <&cpg_clocks>; }; gpio3: gpio@e6053000 { compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; reg = <0 0xe6053000 0 0x50>; interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 96 32>; #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7794_CLK_GPIO3>; power-domains = <&cpg_clocks>; }; gpio4: gpio@e6054000 { compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; reg = <0 0xe6054000 0 0x50>; interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 128 32>; #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7794_CLK_GPIO4>; power-domains = <&cpg_clocks>; }; gpio5: gpio@e6055000 { compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; reg = <0 0xe6055000 0 0x50>; interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 160 28>; #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7794_CLK_GPIO5>; power-domains = <&cpg_clocks>; }; gpio6: gpio@e6055400 { compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; reg = <0 0xe6055400 0 0x50>; interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 192 26>; #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7794_CLK_GPIO6>; power-domains = <&cpg_clocks>; }; cmt0: timer@ffca0000 { compatible = "renesas,cmt-48-gen2"; reg = <0 0xffca0000 0 0x1004>; interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, <0 143 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7794_CLK_CMT0>; clock-names = "fck"; power-domains = <&cpg_clocks>; renesas,channels-mask = <0x60>; status = "disabled"; }; cmt1: timer@e6130000 { compatible = "renesas,cmt-48-gen2"; reg = <0 0xe6130000 0 0x1004>; interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, <0 121 IRQ_TYPE_LEVEL_HIGH>, <0 122 IRQ_TYPE_LEVEL_HIGH>, <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 124 IRQ_TYPE_LEVEL_HIGH>, <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 126 IRQ_TYPE_LEVEL_HIGH>, <0 127 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7794_CLK_CMT1>; clock-names = "fck"; power-domains = <&cpg_clocks>; renesas,channels-mask = <0xff>; status = "disabled"; }; timer { compatible = "arm,armv7-timer"; interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; irqc0: interrupt-controller@e61c0000 { compatible = "renesas,irqc-r8a7794", "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; reg = <0 0xe61c0000 0 0x200>; interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, <0 1 IRQ_TYPE_LEVEL_HIGH>, <0 2 IRQ_TYPE_LEVEL_HIGH>, <0 3 IRQ_TYPE_LEVEL_HIGH>, <0 12 IRQ_TYPE_LEVEL_HIGH>, <0 13 IRQ_TYPE_LEVEL_HIGH>, <0 14 IRQ_TYPE_LEVEL_HIGH>, <0 15 IRQ_TYPE_LEVEL_HIGH>, <0 16 IRQ_TYPE_LEVEL_HIGH>, <0 17 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp4_clks R8A7794_CLK_IRQC>; power-domains = <&cpg_clocks>; }; pfc: pin-controller@e6060000 { compatible = "renesas,pfc-r8a7794"; reg = <0 0xe6060000 0 0x11c>; #gpio-range-cells = <3>; }; dmac0: dma-controller@e6700000 { compatible = "renesas,rcar-dmac"; reg = <0 0xe6700000 0 0x20000>; interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH 0 200 IRQ_TYPE_LEVEL_HIGH 0 201 IRQ_TYPE_LEVEL_HIGH 0 202 IRQ_TYPE_LEVEL_HIGH 0 203 IRQ_TYPE_LEVEL_HIGH 0 204 IRQ_TYPE_LEVEL_HIGH 0 205 IRQ_TYPE_LEVEL_HIGH 0 206 IRQ_TYPE_LEVEL_HIGH 0 207 IRQ_TYPE_LEVEL_HIGH 0 208 IRQ_TYPE_LEVEL_HIGH 0 209 IRQ_TYPE_LEVEL_HIGH 0 210 IRQ_TYPE_LEVEL_HIGH 0 211 IRQ_TYPE_LEVEL_HIGH 0 212 IRQ_TYPE_LEVEL_HIGH 0 213 IRQ_TYPE_LEVEL_HIGH 0 214 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>; clock-names = "fck"; power-domains = <&cpg_clocks>; #dma-cells = <1>; dma-channels = <15>; }; dmac1: dma-controller@e6720000 { compatible = "renesas,rcar-dmac"; reg = <0 0xe6720000 0 0x20000>; interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH 0 216 IRQ_TYPE_LEVEL_HIGH 0 217 IRQ_TYPE_LEVEL_HIGH 0 218 IRQ_TYPE_LEVEL_HIGH 0 219 IRQ_TYPE_LEVEL_HIGH 0 308 IRQ_TYPE_LEVEL_HIGH 0 309 IRQ_TYPE_LEVEL_HIGH 0 310 IRQ_TYPE_LEVEL_HIGH 0 311 IRQ_TYPE_LEVEL_HIGH 0 312 IRQ_TYPE_LEVEL_HIGH 0 313 IRQ_TYPE_LEVEL_HIGH 0 314 IRQ_TYPE_LEVEL_HIGH 0 315 IRQ_TYPE_LEVEL_HIGH 0 316 IRQ_TYPE_LEVEL_HIGH 0 317 IRQ_TYPE_LEVEL_HIGH 0 318 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>; clock-names = "fck"; power-domains = <&cpg_clocks>; #dma-cells = <1>; dma-channels = <15>; }; scifa0: serial@e6c40000 { compatible = "renesas,scifa-r8a7794", "renesas,scifa"; reg = <0 0xe6c40000 0 64>; interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>; clock-names = "sci_ick"; dmas = <&dmac0 0x21>, <&dmac0 0x22>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; status = "disabled"; }; scifa1: serial@e6c50000 { compatible = "renesas,scifa-r8a7794", "renesas,scifa"; reg = <0 0xe6c50000 0 64>; interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>; clock-names = "sci_ick"; dmas = <&dmac0 0x25>, <&dmac0 0x26>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; status = "disabled"; }; scifa2: serial@e6c60000 { compatible = "renesas,scifa-r8a7794", "renesas,scifa"; reg = <0 0xe6c60000 0 64>; interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>; clock-names = "sci_ick"; dmas = <&dmac0 0x27>, <&dmac0 0x28>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; status = "disabled"; }; scifa3: serial@e6c70000 { compatible = "renesas,scifa-r8a7794", "renesas,scifa"; reg = <0 0xe6c70000 0 64>; interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>; clock-names = "sci_ick"; dmas = <&dmac0 0x1b>, <&dmac0 0x1c>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; status = "disabled"; }; scifa4: serial@e6c78000 { compatible = "renesas,scifa-r8a7794", "renesas,scifa"; reg = <0 0xe6c78000 0 64>; interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>; clock-names = "sci_ick"; dmas = <&dmac0 0x1f>, <&dmac0 0x20>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; status = "disabled"; }; scifa5: serial@e6c80000 { compatible = "renesas,scifa-r8a7794", "renesas,scifa"; reg = <0 0xe6c80000 0 64>; interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>; clock-names = "sci_ick"; dmas = <&dmac0 0x23>, <&dmac0 0x24>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; status = "disabled"; }; scifb0: serial@e6c20000 { compatible = "renesas,scifb-r8a7794", "renesas,scifb"; reg = <0 0xe6c20000 0 64>; interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>; clock-names = "sci_ick"; dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; status = "disabled"; }; scifb1: serial@e6c30000 { compatible = "renesas,scifb-r8a7794", "renesas,scifb"; reg = <0 0xe6c30000 0 64>; interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>; clock-names = "sci_ick"; dmas = <&dmac0 0x19>, <&dmac0 0x1a>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; status = "disabled"; }; scifb2: serial@e6ce0000 { compatible = "renesas,scifb-r8a7794", "renesas,scifb"; reg = <0 0xe6ce0000 0 64>; interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>; clock-names = "sci_ick"; dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; status = "disabled"; }; scif0: serial@e6e60000 { compatible = "renesas,scif-r8a7794", "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_SCIF0>; clock-names = "sci_ick"; dmas = <&dmac0 0x29>, <&dmac0 0x2a>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; status = "disabled"; }; scif1: serial@e6e68000 { compatible = "renesas,scif-r8a7794", "renesas,scif"; reg = <0 0xe6e68000 0 64>; interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_SCIF1>; clock-names = "sci_ick"; dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; status = "disabled"; }; scif2: serial@e6e58000 { compatible = "renesas,scif-r8a7794", "renesas,scif"; reg = <0 0xe6e58000 0 64>; interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_SCIF2>; clock-names = "sci_ick"; dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; status = "disabled"; }; scif3: serial@e6ea8000 { compatible = "renesas,scif-r8a7794", "renesas,scif"; reg = <0 0xe6ea8000 0 64>; interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_SCIF3>; clock-names = "sci_ick"; dmas = <&dmac0 0x2f>, <&dmac0 0x30>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; status = "disabled"; }; scif4: serial@e6ee0000 { compatible = "renesas,scif-r8a7794", "renesas,scif"; reg = <0 0xe6ee0000 0 64>; interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_SCIF4>; clock-names = "sci_ick"; dmas = <&dmac0 0xfb>, <&dmac0 0xfc>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; status = "disabled"; }; scif5: serial@e6ee8000 { compatible = "renesas,scif-r8a7794", "renesas,scif"; reg = <0 0xe6ee8000 0 64>; interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_SCIF5>; clock-names = "sci_ick"; dmas = <&dmac0 0xfd>, <&dmac0 0xfe>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; status = "disabled"; }; hscif0: serial@e62c0000 { compatible = "renesas,hscif-r8a7794", "renesas,hscif"; reg = <0 0xe62c0000 0 96>; interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>; clock-names = "sci_ick"; dmas = <&dmac0 0x39>, <&dmac0 0x3a>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; status = "disabled"; }; hscif1: serial@e62c8000 { compatible = "renesas,hscif-r8a7794", "renesas,hscif"; reg = <0 0xe62c8000 0 96>; interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>; clock-names = "sci_ick"; dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; status = "disabled"; }; hscif2: serial@e62d0000 { compatible = "renesas,hscif-r8a7794", "renesas,hscif"; reg = <0 0xe62d0000 0 96>; interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>; clock-names = "sci_ick"; dmas = <&dmac0 0x3b>, <&dmac0 0x3c>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; status = "disabled"; }; ether: ethernet@ee700000 { compatible = "renesas,ether-r8a7794"; reg = <0 0xee700000 0 0x400>; interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp8_clks R8A7794_CLK_ETHER>; power-domains = <&cpg_clocks>; phy-mode = "rmii"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; /* The memory map in the User's Manual maps the cores to bus numbers */ i2c0: i2c@e6508000 { compatible = "renesas,i2c-r8a7794"; reg = <0 0xe6508000 0 0x40>; interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7794_CLK_I2C0>; power-domains = <&cpg_clocks>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c1: i2c@e6518000 { compatible = "renesas,i2c-r8a7794"; reg = <0 0xe6518000 0 0x40>; interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7794_CLK_I2C1>; power-domains = <&cpg_clocks>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c2: i2c@e6530000 { compatible = "renesas,i2c-r8a7794"; reg = <0 0xe6530000 0 0x40>; interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7794_CLK_I2C2>; power-domains = <&cpg_clocks>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c3: i2c@e6540000 { compatible = "renesas,i2c-r8a7794"; reg = <0 0xe6540000 0 0x40>; interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7794_CLK_I2C3>; power-domains = <&cpg_clocks>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c4: i2c@e6520000 { compatible = "renesas,i2c-r8a7794"; reg = <0 0xe6520000 0 0x40>; interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7794_CLK_I2C4>; power-domains = <&cpg_clocks>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c5: i2c@e6528000 { compatible = "renesas,i2c-r8a7794"; reg = <0 0xe6528000 0 0x40>; interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7794_CLK_I2C5>; power-domains = <&cpg_clocks>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; mmcif0: mmc@ee200000 { compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>; dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; reg-io-width = <4>; status = "disabled"; }; sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7794"; reg = <0 0xee100000 0 0x200>; interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7794_CLK_SDHI0>; power-domains = <&cpg_clocks>; status = "disabled"; }; sdhi1: sd@ee140000 { compatible = "renesas,sdhi-r8a7794"; reg = <0 0xee140000 0 0x100>; interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7794_CLK_SDHI1>; power-domains = <&cpg_clocks>; status = "disabled"; }; sdhi2: sd@ee160000 { compatible = "renesas,sdhi-r8a7794"; reg = <0 0xee160000 0 0x100>; interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7794_CLK_SDHI2>; power-domains = <&cpg_clocks>; status = "disabled"; }; qspi: spi@e6b10000 { compatible = "renesas,qspi-r8a7794", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>; interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>; dmas = <&dmac0 0x17>, <&dmac0 0x18>; dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; clocks { #address-cells = <2>; #size-cells = <2>; ranges; /* External root clock */ extal_clk: extal_clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overriden by the board. */ clock-frequency = <0>; clock-output-names = "extal"; }; /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7794-cpg-clocks", "renesas,rcar-gen2-cpg-clocks"; reg = <0 0xe6150000 0 0x1000>; clocks = <&extal_clk>; #clock-cells = <1>; clock-output-names = "main", "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "z"; #power-domain-cells = <0>; }; /* Variable factor clocks */ sd2_clk: sd2_clk@e6150078 { compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150078 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; clock-output-names = "sd2"; }; sd3_clk: sd3_clk@e615026c { compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615026c 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; clock-output-names = "sd3"; }; mmc0_clk: mmc0_clk@e6150240 { compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150240 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; clock-output-names = "mmc0"; }; /* Fixed factor clocks */ pll1_div2_clk: pll1_div2_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; clock-output-names = "pll1_div2"; }; zg_clk: zg_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <6>; clock-mult = <1>; clock-output-names = "zg"; }; zx_clk: zx_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <3>; clock-mult = <1>; clock-output-names = "zx"; }; zs_clk: zs_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <6>; clock-mult = <1>; clock-output-names = "zs"; }; hp_clk: hp_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <12>; clock-mult = <1>; clock-output-names = "hp"; }; i_clk: i_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; clock-output-names = "i"; }; b_clk: b_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <12>; clock-mult = <1>; clock-output-names = "b"; }; p_clk: p_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <24>; clock-mult = <1>; clock-output-names = "p"; }; cl_clk: cl_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <48>; clock-mult = <1>; clock-output-names = "cl"; }; m2_clk: m2_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; clock-output-names = "m2"; }; imp_clk: imp_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <4>; clock-mult = <1>; clock-output-names = "imp"; }; rclk_clk: rclk_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <(48 * 1024)>; clock-mult = <1>; clock-output-names = "rclk"; }; oscclk_clk: oscclk_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <(12 * 1024)>; clock-mult = <1>; clock-output-names = "oscclk"; }; zb3_clk: zb3_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL3>; #clock-cells = <0>; clock-div = <4>; clock-mult = <1>; clock-output-names = "zb3"; }; zb3d2_clk: zb3d2_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL3>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; clock-output-names = "zb3d2"; }; ddr_clk: ddr_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL3>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; clock-output-names = "ddr"; }; mp_clk: mp_clk { compatible = "fixed-factor-clock"; clocks = <&pll1_div2_clk>; #clock-cells = <0>; clock-div = <15>; clock-mult = <1>; clock-output-names = "mp"; }; cp_clk: cp_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <48>; clock-mult = <1>; clock-output-names = "cp"; }; acp_clk: acp_clk { compatible = "fixed-factor-clock"; clocks = <&extal_clk>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; clock-output-names = "acp"; }; /* Gate clocks */ mstp0_clks: mstp0_clks@e6150130 { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; clocks = <&mp_clk>; #clock-cells = <1>; clock-indices = ; clock-output-names = "msiof0"; }; mstp1_clks: mstp1_clks@e6150134 { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>; #clock-cells = <1>; clock-indices = < R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S >; clock-output-names = "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps"; }; mstp2_clks: mstp2_clks@e6150138 { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>; #clock-cells = <1>; clock-indices = < R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0 >; clock-output-names = "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", "scifb1", "msiof1", "scifb2", "sys-dmac1", "sys-dmac0"; }; mstp3_clks: mstp3_clks@e615013c { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>, <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>; #clock-cells = <1>; clock-indices = < R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0 R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1 >; clock-output-names = "sdhi2", "sdhi1", "sdhi0", "mmcif0", "cmt1", "usbdmac0", "usbdmac1"; }; mstp4_clks: mstp4_clks@e6150140 { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; clocks = <&cp_clk>; #clock-cells = <1>; clock-indices = ; clock-output-names = "irqc"; }; mstp7_clks: mstp7_clks@e615014c { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>; #clock-cells = <1>; clock-indices = < R8A7794_CLK_EHCI R8A7794_CLK_HSUSB R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1 R8A7794_CLK_SCIF0 >; clock-output-names = "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0", "scif3", "scif2", "scif1", "scif0"; }; mstp8_clks: mstp8_clks@e6150990 { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; clocks = <&zg_clk>, <&zg_clk>, <&p_clk>; #clock-cells = <1>; clock-indices = < R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER >; clock-output-names = "vin1", "vin0", "ether"; }; mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; #clock-cells = <1>; clock-indices = ; clock-output-names = "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", "qspi_mod", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; }; mstp11_clks: mstp11_clks@e615099c { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; #clock-cells = <1>; clock-indices = < R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5 >; clock-output-names = "scifa3", "scifa4", "scifa5"; }; }; ipmmu_sy0: mmu@e6280000 { compatible = "renesas,ipmmu-vmsa"; reg = <0 0xe6280000 0 0x1000>; interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>, <0 224 IRQ_TYPE_LEVEL_HIGH>; #iommu-cells = <1>; status = "disabled"; }; ipmmu_sy1: mmu@e6290000 { compatible = "renesas,ipmmu-vmsa"; reg = <0 0xe6290000 0 0x1000>; interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>; #iommu-cells = <1>; status = "disabled"; }; ipmmu_ds: mmu@e6740000 { compatible = "renesas,ipmmu-vmsa"; reg = <0 0xe6740000 0 0x1000>; interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, <0 199 IRQ_TYPE_LEVEL_HIGH>; #iommu-cells = <1>; }; ipmmu_mp: mmu@ec680000 { compatible = "renesas,ipmmu-vmsa"; reg = <0 0xec680000 0 0x1000>; interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>; #iommu-cells = <1>; status = "disabled"; }; ipmmu_mx: mmu@fe951000 { compatible = "renesas,ipmmu-vmsa"; reg = <0 0xfe951000 0 0x1000>; interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>; #iommu-cells = <1>; }; ipmmu_gp: mmu@e62a0000 { compatible = "renesas,ipmmu-vmsa"; reg = <0 0xe62a0000 0 0x1000>; interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>, <0 261 IRQ_TYPE_LEVEL_HIGH>; #iommu-cells = <1>; status = "disabled"; }; };