James Hogan 013044cc65 KVM: MIPS/T&E: Expose CP0_EntryLo0/1 registers ... Expose the CP0_EntryLo0 and CP0_EntryLo1 registers through the KVM register access API. This is fairly straightforward for trap & emulate since we don't support the RI and XI bits. For the sake of future proofing (particularly for VZ) it is explicitly specified that the API always exposes the 64-bit version of these registers (i.e. with the RI and XI bits in bit positions 63 and 62 respectively), and they are implemented in trap_emul.c rather than mips.c to allow them to be implemented differently for VZ. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org		2017-02-03 15:21:32 +00:00
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asm	KVM: MIPS/T&E: Expose CP0_EntryLo0/1 registers	2017-02-03 15:21:32 +00:00
uapi/asm	KVM: MIPS: Claim KVM_CAP_READONLY_MEM support	2017-02-03 15:21:29 +00:00