mirror of https://gitee.com/openkylin/linux.git
663 lines
17 KiB
C
663 lines
17 KiB
C
/*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* CPU frequency scaling for S5PC110/S5PV210
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/cpufreq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/reboot.h>
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#include <linux/regulator/consumer.h>
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static void __iomem *clk_base;
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static void __iomem *dmc_base[2];
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#define S5P_CLKREG(x) (clk_base + (x))
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#define S5P_APLL_LOCK S5P_CLKREG(0x00)
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#define S5P_APLL_CON S5P_CLKREG(0x100)
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#define S5P_CLK_SRC0 S5P_CLKREG(0x200)
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#define S5P_CLK_SRC2 S5P_CLKREG(0x208)
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#define S5P_CLK_DIV0 S5P_CLKREG(0x300)
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#define S5P_CLK_DIV2 S5P_CLKREG(0x308)
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#define S5P_CLK_DIV6 S5P_CLKREG(0x318)
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#define S5P_CLKDIV_STAT0 S5P_CLKREG(0x1000)
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#define S5P_CLKDIV_STAT1 S5P_CLKREG(0x1004)
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#define S5P_CLKMUX_STAT0 S5P_CLKREG(0x1100)
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#define S5P_CLKMUX_STAT1 S5P_CLKREG(0x1104)
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#define S5P_ARM_MCS_CON S5P_CLKREG(0x6100)
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/* CLKSRC0 */
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#define S5P_CLKSRC0_MUX200_SHIFT (16)
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#define S5P_CLKSRC0_MUX200_MASK (0x1 << S5P_CLKSRC0_MUX200_SHIFT)
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#define S5P_CLKSRC0_MUX166_MASK (0x1<<20)
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#define S5P_CLKSRC0_MUX133_MASK (0x1<<24)
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/* CLKSRC2 */
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#define S5P_CLKSRC2_G3D_SHIFT (0)
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#define S5P_CLKSRC2_G3D_MASK (0x3 << S5P_CLKSRC2_G3D_SHIFT)
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#define S5P_CLKSRC2_MFC_SHIFT (4)
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#define S5P_CLKSRC2_MFC_MASK (0x3 << S5P_CLKSRC2_MFC_SHIFT)
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/* CLKDIV0 */
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#define S5P_CLKDIV0_APLL_SHIFT (0)
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#define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT)
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#define S5P_CLKDIV0_A2M_SHIFT (4)
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#define S5P_CLKDIV0_A2M_MASK (0x7 << S5P_CLKDIV0_A2M_SHIFT)
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#define S5P_CLKDIV0_HCLK200_SHIFT (8)
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#define S5P_CLKDIV0_HCLK200_MASK (0x7 << S5P_CLKDIV0_HCLK200_SHIFT)
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#define S5P_CLKDIV0_PCLK100_SHIFT (12)
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#define S5P_CLKDIV0_PCLK100_MASK (0x7 << S5P_CLKDIV0_PCLK100_SHIFT)
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#define S5P_CLKDIV0_HCLK166_SHIFT (16)
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#define S5P_CLKDIV0_HCLK166_MASK (0xF << S5P_CLKDIV0_HCLK166_SHIFT)
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#define S5P_CLKDIV0_PCLK83_SHIFT (20)
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#define S5P_CLKDIV0_PCLK83_MASK (0x7 << S5P_CLKDIV0_PCLK83_SHIFT)
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#define S5P_CLKDIV0_HCLK133_SHIFT (24)
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#define S5P_CLKDIV0_HCLK133_MASK (0xF << S5P_CLKDIV0_HCLK133_SHIFT)
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#define S5P_CLKDIV0_PCLK66_SHIFT (28)
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#define S5P_CLKDIV0_PCLK66_MASK (0x7 << S5P_CLKDIV0_PCLK66_SHIFT)
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/* CLKDIV2 */
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#define S5P_CLKDIV2_G3D_SHIFT (0)
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#define S5P_CLKDIV2_G3D_MASK (0xF << S5P_CLKDIV2_G3D_SHIFT)
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#define S5P_CLKDIV2_MFC_SHIFT (4)
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#define S5P_CLKDIV2_MFC_MASK (0xF << S5P_CLKDIV2_MFC_SHIFT)
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/* CLKDIV6 */
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#define S5P_CLKDIV6_ONEDRAM_SHIFT (28)
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#define S5P_CLKDIV6_ONEDRAM_MASK (0xF << S5P_CLKDIV6_ONEDRAM_SHIFT)
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static struct clk *dmc0_clk;
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static struct clk *dmc1_clk;
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static DEFINE_MUTEX(set_freq_lock);
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/* APLL M,P,S values for 1G/800Mhz */
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#define APLL_VAL_1000 ((1 << 31) | (125 << 16) | (3 << 8) | 1)
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#define APLL_VAL_800 ((1 << 31) | (100 << 16) | (3 << 8) | 1)
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/* Use 800MHz when entering sleep mode */
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#define SLEEP_FREQ (800 * 1000)
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/* Tracks if cpu freqency can be updated anymore */
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static bool no_cpufreq_access;
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/*
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* DRAM configurations to calculate refresh counter for changing
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* frequency of memory.
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*/
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struct dram_conf {
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unsigned long freq; /* HZ */
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unsigned long refresh; /* DRAM refresh counter * 1000 */
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};
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/* DRAM configuration (DMC0 and DMC1) */
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static struct dram_conf s5pv210_dram_conf[2];
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enum perf_level {
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L0, L1, L2, L3, L4,
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};
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enum s5pv210_mem_type {
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LPDDR = 0x1,
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LPDDR2 = 0x2,
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DDR2 = 0x4,
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};
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enum s5pv210_dmc_port {
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DMC0 = 0,
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DMC1,
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};
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static struct cpufreq_frequency_table s5pv210_freq_table[] = {
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{0, L0, 1000*1000},
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{0, L1, 800*1000},
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{0, L2, 400*1000},
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{0, L3, 200*1000},
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{0, L4, 100*1000},
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{0, 0, CPUFREQ_TABLE_END},
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};
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static struct regulator *arm_regulator;
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static struct regulator *int_regulator;
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struct s5pv210_dvs_conf {
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int arm_volt; /* uV */
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int int_volt; /* uV */
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};
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static const int arm_volt_max = 1350000;
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static const int int_volt_max = 1250000;
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static struct s5pv210_dvs_conf dvs_conf[] = {
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[L0] = {
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.arm_volt = 1250000,
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.int_volt = 1100000,
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},
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[L1] = {
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.arm_volt = 1200000,
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.int_volt = 1100000,
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},
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[L2] = {
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.arm_volt = 1050000,
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.int_volt = 1100000,
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},
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[L3] = {
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.arm_volt = 950000,
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.int_volt = 1100000,
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},
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[L4] = {
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.arm_volt = 950000,
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.int_volt = 1000000,
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},
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};
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static u32 clkdiv_val[5][11] = {
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/*
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* Clock divider value for following
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* { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
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* HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
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* ONEDRAM, MFC, G3D }
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*/
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/* L0 : [1000/200/100][166/83][133/66][200/200] */
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{0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
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/* L1 : [800/200/100][166/83][133/66][200/200] */
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{0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
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/* L2 : [400/200/100][166/83][133/66][200/200] */
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{1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
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/* L3 : [200/200/100][166/83][133/66][200/200] */
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{3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
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/* L4 : [100/100/100][83/83][66/66][100/100] */
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{7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
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};
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/*
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* This function set DRAM refresh counter
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* accoriding to operating frequency of DRAM
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* ch: DMC port number 0 or 1
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* freq: Operating frequency of DRAM(KHz)
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*/
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static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq)
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{
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unsigned long tmp, tmp1;
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void __iomem *reg = NULL;
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if (ch == DMC0) {
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reg = (dmc_base[0] + 0x30);
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} else if (ch == DMC1) {
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reg = (dmc_base[1] + 0x30);
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} else {
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printk(KERN_ERR "Cannot find DMC port\n");
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return;
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}
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/* Find current DRAM frequency */
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tmp = s5pv210_dram_conf[ch].freq;
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do_div(tmp, freq);
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tmp1 = s5pv210_dram_conf[ch].refresh;
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do_div(tmp1, tmp);
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__raw_writel(tmp1, reg);
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}
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static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
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{
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unsigned long reg;
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unsigned int priv_index;
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unsigned int pll_changing = 0;
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unsigned int bus_speed_changing = 0;
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unsigned int old_freq, new_freq;
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int arm_volt, int_volt;
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int ret = 0;
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mutex_lock(&set_freq_lock);
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if (no_cpufreq_access) {
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pr_err("Denied access to %s as it is disabled temporarily\n",
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__func__);
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ret = -EINVAL;
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goto exit;
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}
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old_freq = policy->cur;
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new_freq = s5pv210_freq_table[index].frequency;
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/* Finding current running level index */
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if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
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old_freq, CPUFREQ_RELATION_H,
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&priv_index)) {
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ret = -EINVAL;
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goto exit;
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}
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arm_volt = dvs_conf[index].arm_volt;
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int_volt = dvs_conf[index].int_volt;
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if (new_freq > old_freq) {
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ret = regulator_set_voltage(arm_regulator,
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arm_volt, arm_volt_max);
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if (ret)
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goto exit;
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ret = regulator_set_voltage(int_regulator,
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int_volt, int_volt_max);
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if (ret)
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goto exit;
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}
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/* Check if there need to change PLL */
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if ((index == L0) || (priv_index == L0))
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pll_changing = 1;
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/* Check if there need to change System bus clock */
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if ((index == L4) || (priv_index == L4))
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bus_speed_changing = 1;
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if (bus_speed_changing) {
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/*
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* Reconfigure DRAM refresh counter value for minimum
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* temporary clock while changing divider.
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* expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
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*/
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if (pll_changing)
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s5pv210_set_refresh(DMC1, 83000);
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else
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s5pv210_set_refresh(DMC1, 100000);
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s5pv210_set_refresh(DMC0, 83000);
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}
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/*
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* APLL should be changed in this level
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* APLL -> MPLL(for stable transition) -> APLL
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* Some clock source's clock API are not prepared.
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* Do not use clock API in below code.
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*/
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if (pll_changing) {
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/*
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* 1. Temporary Change divider for MFC and G3D
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* SCLKA2M(200/1=200)->(200/4=50)Mhz
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*/
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reg = __raw_readl(S5P_CLK_DIV2);
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reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
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reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) |
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(3 << S5P_CLKDIV2_MFC_SHIFT);
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__raw_writel(reg, S5P_CLK_DIV2);
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/* For MFC, G3D dividing */
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do {
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reg = __raw_readl(S5P_CLKDIV_STAT0);
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} while (reg & ((1 << 16) | (1 << 17)));
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/*
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* 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
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* (200/4=50)->(667/4=166)Mhz
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*/
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reg = __raw_readl(S5P_CLK_SRC2);
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reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
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reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) |
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(1 << S5P_CLKSRC2_MFC_SHIFT);
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__raw_writel(reg, S5P_CLK_SRC2);
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do {
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reg = __raw_readl(S5P_CLKMUX_STAT1);
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} while (reg & ((1 << 7) | (1 << 3)));
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/*
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* 3. DMC1 refresh count for 133Mhz if (index == L4) is
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* true refresh counter is already programed in upper
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* code. 0x287@83Mhz
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*/
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if (!bus_speed_changing)
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s5pv210_set_refresh(DMC1, 133000);
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/* 4. SCLKAPLL -> SCLKMPLL */
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reg = __raw_readl(S5P_CLK_SRC0);
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reg &= ~(S5P_CLKSRC0_MUX200_MASK);
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reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);
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__raw_writel(reg, S5P_CLK_SRC0);
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do {
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reg = __raw_readl(S5P_CLKMUX_STAT0);
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} while (reg & (0x1 << 18));
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}
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/* Change divider */
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reg = __raw_readl(S5P_CLK_DIV0);
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reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK |
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S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK |
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S5P_CLKDIV0_HCLK166_MASK | S5P_CLKDIV0_PCLK83_MASK |
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S5P_CLKDIV0_HCLK133_MASK | S5P_CLKDIV0_PCLK66_MASK);
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reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) |
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(clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) |
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(clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) |
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(clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) |
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(clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) |
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(clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) |
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(clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) |
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(clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT));
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__raw_writel(reg, S5P_CLK_DIV0);
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do {
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reg = __raw_readl(S5P_CLKDIV_STAT0);
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} while (reg & 0xff);
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/* ARM MCS value changed */
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reg = __raw_readl(S5P_ARM_MCS_CON);
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reg &= ~0x3;
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if (index >= L3)
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reg |= 0x3;
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else
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reg |= 0x1;
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__raw_writel(reg, S5P_ARM_MCS_CON);
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if (pll_changing) {
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/* 5. Set Lock time = 30us*24Mhz = 0x2cf */
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__raw_writel(0x2cf, S5P_APLL_LOCK);
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/*
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* 6. Turn on APLL
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* 6-1. Set PMS values
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* 6-2. Wait untile the PLL is locked
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*/
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if (index == L0)
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__raw_writel(APLL_VAL_1000, S5P_APLL_CON);
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else
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__raw_writel(APLL_VAL_800, S5P_APLL_CON);
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do {
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reg = __raw_readl(S5P_APLL_CON);
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} while (!(reg & (0x1 << 29)));
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/*
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* 7. Change souce clock from SCLKMPLL(667Mhz)
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* to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
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* (667/4=166)->(200/4=50)Mhz
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*/
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reg = __raw_readl(S5P_CLK_SRC2);
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reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
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reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) |
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(0 << S5P_CLKSRC2_MFC_SHIFT);
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__raw_writel(reg, S5P_CLK_SRC2);
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do {
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reg = __raw_readl(S5P_CLKMUX_STAT1);
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} while (reg & ((1 << 7) | (1 << 3)));
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/*
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* 8. Change divider for MFC and G3D
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* (200/4=50)->(200/1=200)Mhz
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*/
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reg = __raw_readl(S5P_CLK_DIV2);
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reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
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reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) |
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(clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT);
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__raw_writel(reg, S5P_CLK_DIV2);
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/* For MFC, G3D dividing */
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do {
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reg = __raw_readl(S5P_CLKDIV_STAT0);
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} while (reg & ((1 << 16) | (1 << 17)));
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/* 9. Change MPLL to APLL in MSYS_MUX */
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reg = __raw_readl(S5P_CLK_SRC0);
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reg &= ~(S5P_CLKSRC0_MUX200_MASK);
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reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);
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__raw_writel(reg, S5P_CLK_SRC0);
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do {
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reg = __raw_readl(S5P_CLKMUX_STAT0);
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} while (reg & (0x1 << 18));
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/*
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* 10. DMC1 refresh counter
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* L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
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* Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
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*/
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if (!bus_speed_changing)
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s5pv210_set_refresh(DMC1, 200000);
|
|
}
|
|
|
|
/*
|
|
* L4 level need to change memory bus speed, hence onedram clock divier
|
|
* and memory refresh parameter should be changed
|
|
*/
|
|
if (bus_speed_changing) {
|
|
reg = __raw_readl(S5P_CLK_DIV6);
|
|
reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
|
|
reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
|
|
__raw_writel(reg, S5P_CLK_DIV6);
|
|
|
|
do {
|
|
reg = __raw_readl(S5P_CLKDIV_STAT1);
|
|
} while (reg & (1 << 15));
|
|
|
|
/* Reconfigure DRAM refresh counter value */
|
|
if (index != L4) {
|
|
/*
|
|
* DMC0 : 166Mhz
|
|
* DMC1 : 200Mhz
|
|
*/
|
|
s5pv210_set_refresh(DMC0, 166000);
|
|
s5pv210_set_refresh(DMC1, 200000);
|
|
} else {
|
|
/*
|
|
* DMC0 : 83Mhz
|
|
* DMC1 : 100Mhz
|
|
*/
|
|
s5pv210_set_refresh(DMC0, 83000);
|
|
s5pv210_set_refresh(DMC1, 100000);
|
|
}
|
|
}
|
|
|
|
if (new_freq < old_freq) {
|
|
regulator_set_voltage(int_regulator,
|
|
int_volt, int_volt_max);
|
|
|
|
regulator_set_voltage(arm_regulator,
|
|
arm_volt, arm_volt_max);
|
|
}
|
|
|
|
printk(KERN_DEBUG "Perf changed[L%d]\n", index);
|
|
|
|
exit:
|
|
mutex_unlock(&set_freq_lock);
|
|
return ret;
|
|
}
|
|
|
|
static int check_mem_type(void __iomem *dmc_reg)
|
|
{
|
|
unsigned long val;
|
|
|
|
val = __raw_readl(dmc_reg + 0x4);
|
|
val = (val & (0xf << 8));
|
|
|
|
return val >> 8;
|
|
}
|
|
|
|
static int s5pv210_cpu_init(struct cpufreq_policy *policy)
|
|
{
|
|
unsigned long mem_type;
|
|
int ret;
|
|
|
|
policy->clk = clk_get(NULL, "armclk");
|
|
if (IS_ERR(policy->clk))
|
|
return PTR_ERR(policy->clk);
|
|
|
|
dmc0_clk = clk_get(NULL, "sclk_dmc0");
|
|
if (IS_ERR(dmc0_clk)) {
|
|
ret = PTR_ERR(dmc0_clk);
|
|
goto out_dmc0;
|
|
}
|
|
|
|
dmc1_clk = clk_get(NULL, "hclk_msys");
|
|
if (IS_ERR(dmc1_clk)) {
|
|
ret = PTR_ERR(dmc1_clk);
|
|
goto out_dmc1;
|
|
}
|
|
|
|
if (policy->cpu != 0) {
|
|
ret = -EINVAL;
|
|
goto out_dmc1;
|
|
}
|
|
|
|
/*
|
|
* check_mem_type : This driver only support LPDDR & LPDDR2.
|
|
* other memory type is not supported.
|
|
*/
|
|
mem_type = check_mem_type(dmc_base[0]);
|
|
|
|
if ((mem_type != LPDDR) && (mem_type != LPDDR2)) {
|
|
printk(KERN_ERR "CPUFreq doesn't support this memory type\n");
|
|
ret = -EINVAL;
|
|
goto out_dmc1;
|
|
}
|
|
|
|
/* Find current refresh counter and frequency each DMC */
|
|
s5pv210_dram_conf[0].refresh = (__raw_readl(dmc_base[0] + 0x30) * 1000);
|
|
s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);
|
|
|
|
s5pv210_dram_conf[1].refresh = (__raw_readl(dmc_base[1] + 0x30) * 1000);
|
|
s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk);
|
|
|
|
policy->suspend_freq = SLEEP_FREQ;
|
|
return cpufreq_generic_init(policy, s5pv210_freq_table, 40000);
|
|
|
|
out_dmc1:
|
|
clk_put(dmc0_clk);
|
|
out_dmc0:
|
|
clk_put(policy->clk);
|
|
return ret;
|
|
}
|
|
|
|
static int s5pv210_cpufreq_reboot_notifier_event(struct notifier_block *this,
|
|
unsigned long event, void *ptr)
|
|
{
|
|
int ret;
|
|
|
|
ret = cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ, 0);
|
|
if (ret < 0)
|
|
return NOTIFY_BAD;
|
|
|
|
no_cpufreq_access = true;
|
|
return NOTIFY_DONE;
|
|
}
|
|
|
|
static struct cpufreq_driver s5pv210_driver = {
|
|
.flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
|
|
.verify = cpufreq_generic_frequency_table_verify,
|
|
.target_index = s5pv210_target,
|
|
.get = cpufreq_generic_get,
|
|
.init = s5pv210_cpu_init,
|
|
.name = "s5pv210",
|
|
#ifdef CONFIG_PM
|
|
.suspend = cpufreq_generic_suspend,
|
|
.resume = cpufreq_generic_suspend, /* We need to set SLEEP FREQ again */
|
|
#endif
|
|
};
|
|
|
|
static struct notifier_block s5pv210_cpufreq_reboot_notifier = {
|
|
.notifier_call = s5pv210_cpufreq_reboot_notifier_event,
|
|
};
|
|
|
|
static int s5pv210_cpufreq_probe(struct platform_device *pdev)
|
|
{
|
|
struct device_node *np;
|
|
int id;
|
|
|
|
/*
|
|
* HACK: This is a temporary workaround to get access to clock
|
|
* and DMC controller registers directly and remove static mappings
|
|
* and dependencies on platform headers. It is necessary to enable
|
|
* S5PV210 multi-platform support and will be removed together with
|
|
* this whole driver as soon as S5PV210 gets migrated to use
|
|
* cpufreq-dt driver.
|
|
*/
|
|
np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock");
|
|
if (!np) {
|
|
pr_err("%s: failed to find clock controller DT node\n",
|
|
__func__);
|
|
return -ENODEV;
|
|
}
|
|
|
|
clk_base = of_iomap(np, 0);
|
|
if (!clk_base) {
|
|
pr_err("%s: failed to map clock registers\n", __func__);
|
|
return -EFAULT;
|
|
}
|
|
|
|
for_each_compatible_node(np, NULL, "samsung,s5pv210-dmc") {
|
|
id = of_alias_get_id(np, "dmc");
|
|
if (id < 0 || id >= ARRAY_SIZE(dmc_base)) {
|
|
pr_err("%s: failed to get alias of dmc node '%s'\n",
|
|
__func__, np->name);
|
|
return id;
|
|
}
|
|
|
|
dmc_base[id] = of_iomap(np, 0);
|
|
if (!dmc_base[id]) {
|
|
pr_err("%s: failed to map dmc%d registers\n",
|
|
__func__, id);
|
|
return -EFAULT;
|
|
}
|
|
}
|
|
|
|
for (id = 0; id < ARRAY_SIZE(dmc_base); ++id) {
|
|
if (!dmc_base[id]) {
|
|
pr_err("%s: failed to find dmc%d node\n", __func__, id);
|
|
return -ENODEV;
|
|
}
|
|
}
|
|
|
|
arm_regulator = regulator_get(NULL, "vddarm");
|
|
if (IS_ERR(arm_regulator)) {
|
|
pr_err("failed to get regulator vddarm");
|
|
return PTR_ERR(arm_regulator);
|
|
}
|
|
|
|
int_regulator = regulator_get(NULL, "vddint");
|
|
if (IS_ERR(int_regulator)) {
|
|
pr_err("failed to get regulator vddint");
|
|
regulator_put(arm_regulator);
|
|
return PTR_ERR(int_regulator);
|
|
}
|
|
|
|
register_reboot_notifier(&s5pv210_cpufreq_reboot_notifier);
|
|
|
|
return cpufreq_register_driver(&s5pv210_driver);
|
|
}
|
|
|
|
static struct platform_driver s5pv210_cpufreq_platdrv = {
|
|
.driver = {
|
|
.name = "s5pv210-cpufreq",
|
|
},
|
|
.probe = s5pv210_cpufreq_probe,
|
|
};
|
|
module_platform_driver(s5pv210_cpufreq_platdrv);
|