mirror of https://gitee.com/openkylin/linux.git
176 lines
4.7 KiB
C
176 lines
4.7 KiB
C
/*
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* Intel CE4100 platform specific setup code
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*
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* (C) Copyright 2010 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/reboot.h>
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#include <linux/serial_reg.h>
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#include <linux/serial_8250.h>
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#include <linux/reboot.h>
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#include <asm/ce4100.h>
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#include <asm/prom.h>
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#include <asm/setup.h>
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#include <asm/i8259.h>
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#include <asm/io.h>
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#include <asm/io_apic.h>
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#include <asm/emergency-restart.h>
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static int ce4100_i8042_detect(void)
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{
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return 0;
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}
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/*
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* The CE4100 platform has an internal 8051 Microcontroller which is
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* responsible for signaling to the external Power Management Unit the
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* intention to reset, reboot or power off the system. This 8051 device has
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* its command register mapped at I/O port 0xcf9 and the value 0x4 is used
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* to power off the system.
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*/
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static void ce4100_power_off(void)
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{
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outb(0x4, 0xcf9);
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}
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#ifdef CONFIG_SERIAL_8250
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static unsigned int mem_serial_in(struct uart_port *p, int offset)
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{
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offset = offset << p->regshift;
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return readl(p->membase + offset);
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}
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/*
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* The UART Tx interrupts are not set under some conditions and therefore serial
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* transmission hangs. This is a silicon issue and has not been root caused. The
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* workaround for this silicon issue checks UART_LSR_THRE bit and UART_LSR_TEMT
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* bit of LSR register in interrupt handler to see whether at least one of these
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* two bits is set, if so then process the transmit request. If this workaround
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* is not applied, then the serial transmission may hang. This workaround is for
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* errata number 9 in Errata - B step.
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*/
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static unsigned int ce4100_mem_serial_in(struct uart_port *p, int offset)
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{
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unsigned int ret, ier, lsr;
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if (offset == UART_IIR) {
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offset = offset << p->regshift;
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ret = readl(p->membase + offset);
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if (ret & UART_IIR_NO_INT) {
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/* see if the TX interrupt should have really set */
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ier = mem_serial_in(p, UART_IER);
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/* see if the UART's XMIT interrupt is enabled */
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if (ier & UART_IER_THRI) {
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lsr = mem_serial_in(p, UART_LSR);
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/* now check to see if the UART should be
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generating an interrupt (but isn't) */
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if (lsr & (UART_LSR_THRE | UART_LSR_TEMT))
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ret &= ~UART_IIR_NO_INT;
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}
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}
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} else
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ret = mem_serial_in(p, offset);
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return ret;
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}
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static void ce4100_mem_serial_out(struct uart_port *p, int offset, int value)
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{
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offset = offset << p->regshift;
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writel(value, p->membase + offset);
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}
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static void ce4100_serial_fixup(int port, struct uart_port *up,
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unsigned short *capabilites)
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{
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#ifdef CONFIG_EARLY_PRINTK
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/*
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* Over ride the legacy port configuration that comes from
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* asm/serial.h. Using the ioport driver then switching to the
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* PCI memmaped driver hangs the IOAPIC
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*/
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if (up->iotype != UPIO_MEM32) {
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up->uartclk = 14745600;
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up->mapbase = 0xdffe0200;
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set_fixmap_nocache(FIX_EARLYCON_MEM_BASE,
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up->mapbase & PAGE_MASK);
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up->membase =
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(void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE);
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up->membase += up->mapbase & ~PAGE_MASK;
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up->mapbase += port * 0x100;
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up->membase += port * 0x100;
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up->iotype = UPIO_MEM32;
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up->regshift = 2;
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up->irq = 4;
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}
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#endif
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up->iobase = 0;
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up->serial_in = ce4100_mem_serial_in;
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up->serial_out = ce4100_mem_serial_out;
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*capabilites |= (1 << 12);
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}
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static __init void sdv_serial_fixup(void)
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{
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serial8250_set_isa_configurator(ce4100_serial_fixup);
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}
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#else
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static inline void sdv_serial_fixup(void) {};
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#endif
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static void __init sdv_arch_setup(void)
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{
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sdv_serial_fixup();
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}
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#ifdef CONFIG_X86_IO_APIC
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static void sdv_pci_init(void)
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{
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x86_of_pci_init();
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/* We can't set this earlier, because we need to calibrate the timer */
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legacy_pic = &null_legacy_pic;
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}
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#endif
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/*
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* CE4100 specific x86_init function overrides and early setup
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* calls.
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*/
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void __init x86_ce4100_early_setup(void)
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{
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x86_init.oem.arch_setup = sdv_arch_setup;
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x86_platform.i8042_detect = ce4100_i8042_detect;
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x86_init.resources.probe_roms = x86_init_noop;
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x86_init.mpparse.get_smp_config = x86_init_uint_noop;
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x86_init.mpparse.find_smp_config = x86_init_noop;
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x86_init.pci.init = ce4100_pci_init;
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/*
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* By default, the reboot method is ACPI which is supported by the
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* CE4100 bootloader CEFDK using FADT.ResetReg Address and ResetValue
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* the bootloader will however issue a system power off instead of
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* reboot. By using BOOT_KBD we ensure proper system reboot as
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* expected.
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*/
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reboot_type = BOOT_KBD;
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#ifdef CONFIG_X86_IO_APIC
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x86_init.pci.init_irq = sdv_pci_init;
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x86_init.mpparse.setup_ioapic_ids = setup_ioapic_ids_from_mpc_nocheck;
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#endif
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pm_power_off = ce4100_power_off;
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}
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