mirror of https://gitee.com/openkylin/linux.git
490 lines
13 KiB
C
490 lines
13 KiB
C
/*
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* Copyright(c) 2015, 2016 Intel Corporation.
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* BSD LICENSE
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* - Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/vmalloc.h>
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#include "hfi.h"
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#include "twsi.h"
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/*
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* "Two Wire Serial Interface" support.
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*
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* Originally written for a not-quite-i2c serial eeprom, which is
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* still used on some supported boards. Later boards have added a
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* variety of other uses, most board-specific, so the bit-boffing
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* part has been split off to this file, while the other parts
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* have been moved to chip-specific files.
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*
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* We have also dropped all pretense of fully generic (e.g. pretend
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* we don't know whether '1' is the higher voltage) interface, as
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* the restrictions of the generic i2c interface (e.g. no access from
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* driver itself) make it unsuitable for this use.
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*/
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#define READ_CMD 1
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#define WRITE_CMD 0
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/**
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* i2c_wait_for_writes - wait for a write
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* @dd: the hfi1_ib device
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*
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* We use this instead of udelay directly, so we can make sure
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* that previous register writes have been flushed all the way
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* to the chip. Since we are delaying anyway, the cost doesn't
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* hurt, and makes the bit twiddling more regular
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*/
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static void i2c_wait_for_writes(struct hfi1_devdata *dd, u32 target)
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{
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/*
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* implicit read of EXTStatus is as good as explicit
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* read of scratch, if all we want to do is flush
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* writes.
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*/
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hfi1_gpio_mod(dd, target, 0, 0, 0);
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rmb(); /* inlined, so prevent compiler reordering */
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}
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/*
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* QSFP modules are allowed to hold SCL low for 500uSec. Allow twice that
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* for "almost compliant" modules
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*/
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#define SCL_WAIT_USEC 1000
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/* BUF_WAIT is time bus must be free between STOP or ACK and to next START.
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* Should be 20, but some chips need more.
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*/
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#define TWSI_BUF_WAIT_USEC 60
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static void scl_out(struct hfi1_devdata *dd, u32 target, u8 bit)
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{
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u32 mask;
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udelay(1);
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mask = QSFP_HFI0_I2CCLK;
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/* SCL is meant to be bare-drain, so never set "OUT", just DIR */
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hfi1_gpio_mod(dd, target, 0, bit ? 0 : mask, mask);
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/*
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* Allow for slow slaves by simple
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* delay for falling edge, sampling on rise.
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*/
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if (!bit) {
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udelay(2);
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} else {
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int rise_usec;
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for (rise_usec = SCL_WAIT_USEC; rise_usec > 0; rise_usec -= 2) {
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if (mask & hfi1_gpio_mod(dd, target, 0, 0, 0))
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break;
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udelay(2);
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}
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if (rise_usec <= 0)
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dd_dev_err(dd, "SCL interface stuck low > %d uSec\n",
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SCL_WAIT_USEC);
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}
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i2c_wait_for_writes(dd, target);
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}
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static u8 scl_in(struct hfi1_devdata *dd, u32 target, int wait)
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{
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u32 read_val, mask;
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mask = QSFP_HFI0_I2CCLK;
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/* SCL is meant to be bare-drain, so never set "OUT", just DIR */
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hfi1_gpio_mod(dd, target, 0, 0, mask);
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read_val = hfi1_gpio_mod(dd, target, 0, 0, 0);
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if (wait)
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i2c_wait_for_writes(dd, target);
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return (read_val & mask) >> GPIO_SCL_NUM;
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}
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static void sda_out(struct hfi1_devdata *dd, u32 target, u8 bit)
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{
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u32 mask;
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mask = QSFP_HFI0_I2CDAT;
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/* SDA is meant to be bare-drain, so never set "OUT", just DIR */
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hfi1_gpio_mod(dd, target, 0, bit ? 0 : mask, mask);
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i2c_wait_for_writes(dd, target);
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udelay(2);
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}
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static u8 sda_in(struct hfi1_devdata *dd, u32 target, int wait)
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{
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u32 read_val, mask;
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mask = QSFP_HFI0_I2CDAT;
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/* SDA is meant to be bare-drain, so never set "OUT", just DIR */
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hfi1_gpio_mod(dd, target, 0, 0, mask);
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read_val = hfi1_gpio_mod(dd, target, 0, 0, 0);
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if (wait)
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i2c_wait_for_writes(dd, target);
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return (read_val & mask) >> GPIO_SDA_NUM;
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}
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/**
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* i2c_ackrcv - see if ack following write is true
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* @dd: the hfi1_ib device
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*/
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static int i2c_ackrcv(struct hfi1_devdata *dd, u32 target)
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{
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u8 ack_received;
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/* AT ENTRY SCL = LOW */
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/* change direction, ignore data */
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ack_received = sda_in(dd, target, 1);
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scl_out(dd, target, 1);
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ack_received = sda_in(dd, target, 1) == 0;
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scl_out(dd, target, 0);
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return ack_received;
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}
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static void stop_cmd(struct hfi1_devdata *dd, u32 target);
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/**
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* rd_byte - read a byte, sending STOP on last, else ACK
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* @dd: the hfi1_ib device
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*
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* Returns byte shifted out of device
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*/
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static int rd_byte(struct hfi1_devdata *dd, u32 target, int last)
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{
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int bit_cntr, data;
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data = 0;
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for (bit_cntr = 7; bit_cntr >= 0; --bit_cntr) {
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data <<= 1;
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scl_out(dd, target, 1);
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data |= sda_in(dd, target, 0);
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scl_out(dd, target, 0);
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}
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if (last) {
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scl_out(dd, target, 1);
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stop_cmd(dd, target);
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} else {
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sda_out(dd, target, 0);
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scl_out(dd, target, 1);
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scl_out(dd, target, 0);
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sda_out(dd, target, 1);
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}
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return data;
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}
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/**
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* wr_byte - write a byte, one bit at a time
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* @dd: the hfi1_ib device
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* @data: the byte to write
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*
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* Returns 0 if we got the following ack, otherwise 1
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*/
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static int wr_byte(struct hfi1_devdata *dd, u32 target, u8 data)
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{
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int bit_cntr;
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u8 bit;
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for (bit_cntr = 7; bit_cntr >= 0; bit_cntr--) {
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bit = (data >> bit_cntr) & 1;
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sda_out(dd, target, bit);
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scl_out(dd, target, 1);
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scl_out(dd, target, 0);
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}
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return (!i2c_ackrcv(dd, target)) ? 1 : 0;
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}
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/*
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* issue TWSI start sequence:
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* (both clock/data high, clock high, data low while clock is high)
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*/
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static void start_seq(struct hfi1_devdata *dd, u32 target)
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{
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sda_out(dd, target, 1);
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scl_out(dd, target, 1);
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sda_out(dd, target, 0);
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udelay(1);
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scl_out(dd, target, 0);
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}
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/**
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* stop_seq - transmit the stop sequence
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* @dd: the hfi1_ib device
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*
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* (both clock/data low, clock high, data high while clock is high)
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*/
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static void stop_seq(struct hfi1_devdata *dd, u32 target)
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{
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scl_out(dd, target, 0);
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sda_out(dd, target, 0);
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scl_out(dd, target, 1);
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sda_out(dd, target, 1);
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}
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/**
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* stop_cmd - transmit the stop condition
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* @dd: the hfi1_ib device
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*
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* (both clock/data low, clock high, data high while clock is high)
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*/
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static void stop_cmd(struct hfi1_devdata *dd, u32 target)
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{
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stop_seq(dd, target);
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udelay(TWSI_BUF_WAIT_USEC);
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}
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/**
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* hfi1_twsi_reset - reset I2C communication
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* @dd: the hfi1_ib device
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* returns 0 if ok, -EIO on error
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*/
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int hfi1_twsi_reset(struct hfi1_devdata *dd, u32 target)
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{
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int clock_cycles_left = 9;
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u32 mask;
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/* Both SCL and SDA should be high. If not, there
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* is something wrong.
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*/
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mask = QSFP_HFI0_I2CCLK | QSFP_HFI0_I2CDAT;
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/*
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* Force pins to desired innocuous state.
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* This is the default power-on state with out=0 and dir=0,
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* So tri-stated and should be floating high (barring HW problems)
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*/
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hfi1_gpio_mod(dd, target, 0, 0, mask);
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/* Check if SCL is low, if it is low then we have a slave device
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* misbehaving and there is not much we can do.
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*/
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if (!scl_in(dd, target, 0))
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return -EIO;
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/* Check if SDA is low, if it is low then we have to clock SDA
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* up to 9 times for the device to release the bus
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*/
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while (clock_cycles_left--) {
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if (sda_in(dd, target, 0))
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return 0;
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scl_out(dd, target, 0);
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scl_out(dd, target, 1);
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}
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return -EIO;
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}
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#define HFI1_TWSI_START 0x100
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#define HFI1_TWSI_STOP 0x200
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/* Write byte to TWSI, optionally prefixed with START or suffixed with
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* STOP.
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* returns 0 if OK (ACK received), else != 0
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*/
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static int twsi_wr(struct hfi1_devdata *dd, u32 target, int data, int flags)
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{
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int ret = 1;
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if (flags & HFI1_TWSI_START)
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start_seq(dd, target);
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/* Leaves SCL low (from i2c_ackrcv()) */
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ret = wr_byte(dd, target, data);
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if (flags & HFI1_TWSI_STOP)
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stop_cmd(dd, target);
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return ret;
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}
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/* Added functionality for IBA7220-based cards */
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#define HFI1_TEMP_DEV 0x98
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/*
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* hfi1_twsi_blk_rd
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* General interface for data transfer from twsi devices.
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* One vestige of its former role is that it recognizes a device
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* HFI1_TWSI_NO_DEV and does the correct operation for the legacy part,
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* which responded to all TWSI device codes, interpreting them as
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* address within device. On all other devices found on board handled by
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* this driver, the device is followed by a N-byte "address" which selects
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* the "register" or "offset" within the device from which data should
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* be read.
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*/
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int hfi1_twsi_blk_rd(struct hfi1_devdata *dd, u32 target, int dev, int addr,
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void *buffer, int len)
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{
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u8 *bp = buffer;
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int ret = 1;
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int i;
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int offset_size;
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/* obtain the offset size, strip it from the device address */
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offset_size = (dev >> 8) & 0xff;
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dev &= 0xff;
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/* allow at most a 2 byte offset */
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if (offset_size > 2)
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goto bail;
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if (dev == HFI1_TWSI_NO_DEV) {
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/* legacy not-really-I2C */
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addr = (addr << 1) | READ_CMD;
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ret = twsi_wr(dd, target, addr, HFI1_TWSI_START);
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} else {
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/* Actual I2C */
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if (offset_size) {
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ret = twsi_wr(dd, target,
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dev | WRITE_CMD, HFI1_TWSI_START);
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if (ret) {
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stop_cmd(dd, target);
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goto bail;
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}
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for (i = 0; i < offset_size; i++) {
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ret = twsi_wr(dd, target,
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(addr >> (i * 8)) & 0xff, 0);
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udelay(TWSI_BUF_WAIT_USEC);
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if (ret) {
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dd_dev_err(dd, "Failed to write byte %d of offset 0x%04X\n",
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i, addr);
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goto bail;
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}
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}
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}
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ret = twsi_wr(dd, target, dev | READ_CMD, HFI1_TWSI_START);
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}
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if (ret) {
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stop_cmd(dd, target);
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goto bail;
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}
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/*
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* block devices keeps clocking data out as long as we ack,
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* automatically incrementing the address. Some have "pages"
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* whose boundaries will not be crossed, but the handling
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* of these is left to the caller, who is in a better
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* position to know.
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*/
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while (len-- > 0) {
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/*
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* Get and store data, sending ACK if length remaining,
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* else STOP
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*/
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*bp++ = rd_byte(dd, target, !len);
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}
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ret = 0;
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bail:
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return ret;
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}
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/*
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* hfi1_twsi_blk_wr
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* General interface for data transfer to twsi devices.
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* One vestige of its former role is that it recognizes a device
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* HFI1_TWSI_NO_DEV and does the correct operation for the legacy part,
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* which responded to all TWSI device codes, interpreting them as
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* address within device. On all other devices found on board handled by
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* this driver, the device is followed by a N-byte "address" which selects
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* the "register" or "offset" within the device to which data should
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* be written.
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*/
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int hfi1_twsi_blk_wr(struct hfi1_devdata *dd, u32 target, int dev, int addr,
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const void *buffer, int len)
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{
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const u8 *bp = buffer;
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int ret = 1;
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int i;
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int offset_size;
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/* obtain the offset size, strip it from the device address */
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offset_size = (dev >> 8) & 0xff;
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dev &= 0xff;
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/* allow at most a 2 byte offset */
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if (offset_size > 2)
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goto bail;
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if (dev == HFI1_TWSI_NO_DEV) {
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if (twsi_wr(dd, target, (addr << 1) | WRITE_CMD,
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HFI1_TWSI_START)) {
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goto failed_write;
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}
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} else {
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/* Real I2C */
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if (twsi_wr(dd, target, dev | WRITE_CMD, HFI1_TWSI_START))
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goto failed_write;
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}
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for (i = 0; i < offset_size; i++) {
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ret = twsi_wr(dd, target, (addr >> (i * 8)) & 0xff, 0);
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udelay(TWSI_BUF_WAIT_USEC);
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if (ret) {
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dd_dev_err(dd, "Failed to write byte %d of offset 0x%04X\n",
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i, addr);
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goto bail;
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}
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}
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for (i = 0; i < len; i++)
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if (twsi_wr(dd, target, *bp++, 0))
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goto failed_write;
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ret = 0;
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failed_write:
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stop_cmd(dd, target);
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bail:
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return ret;
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}
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