mirror of https://gitee.com/openkylin/linux.git
259 lines
7.7 KiB
C
259 lines
7.7 KiB
C
/*
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* ALSA SoC TLV320AIC31XX codec driver
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*
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* This package is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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*
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*/
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#ifndef _TLV320AIC31XX_H
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#define _TLV320AIC31XX_H
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#define AIC31XX_RATES SNDRV_PCM_RATE_8000_192000
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#define AIC31XX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
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| SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
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#define AIC31XX_STEREO_CLASS_D_BIT 0x1
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#define AIC31XX_MINIDSP_BIT 0x2
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enum aic31xx_type {
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AIC3100 = 0,
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AIC3110 = AIC31XX_STEREO_CLASS_D_BIT,
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AIC3120 = AIC31XX_MINIDSP_BIT,
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AIC3111 = (AIC31XX_STEREO_CLASS_D_BIT | AIC31XX_MINIDSP_BIT),
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};
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struct aic31xx_pdata {
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enum aic31xx_type codec_type;
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unsigned int gpio_reset;
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int micbias_vg;
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};
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/* Page Control Register */
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#define AIC31XX_PAGECTL 0x00
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/* Page 0 Registers */
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/* Software reset register */
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#define AIC31XX_RESET 0x01
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/* OT FLAG register */
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#define AIC31XX_OT_FLAG 0x03
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/* Clock clock Gen muxing, Multiplexers*/
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#define AIC31XX_CLKMUX 0x04
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/* PLL P and R-VAL register */
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#define AIC31XX_PLLPR 0x05
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/* PLL J-VAL register */
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#define AIC31XX_PLLJ 0x06
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/* PLL D-VAL MSB register */
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#define AIC31XX_PLLDMSB 0x07
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/* PLL D-VAL LSB register */
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#define AIC31XX_PLLDLSB 0x08
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/* DAC NDAC_VAL register*/
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#define AIC31XX_NDAC 0x0B
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/* DAC MDAC_VAL register */
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#define AIC31XX_MDAC 0x0C
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/* DAC OSR setting register 1, MSB value */
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#define AIC31XX_DOSRMSB 0x0D
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/* DAC OSR setting register 2, LSB value */
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#define AIC31XX_DOSRLSB 0x0E
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#define AIC31XX_MINI_DSP_INPOL 0x10
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/* Clock setting register 8, PLL */
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#define AIC31XX_NADC 0x12
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/* Clock setting register 9, PLL */
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#define AIC31XX_MADC 0x13
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/* ADC Oversampling (AOSR) Register */
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#define AIC31XX_AOSR 0x14
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/* Clock setting register 9, Multiplexers */
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#define AIC31XX_CLKOUTMUX 0x19
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/* Clock setting register 10, CLOCKOUT M divider value */
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#define AIC31XX_CLKOUTMVAL 0x1A
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/* Audio Interface Setting Register 1 */
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#define AIC31XX_IFACE1 0x1B
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/* Audio Data Slot Offset Programming */
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#define AIC31XX_DATA_OFFSET 0x1C
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/* Audio Interface Setting Register 2 */
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#define AIC31XX_IFACE2 0x1D
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/* Clock setting register 11, BCLK N Divider */
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#define AIC31XX_BCLKN 0x1E
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/* Audio Interface Setting Register 3, Secondary Audio Interface */
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#define AIC31XX_IFACESEC1 0x1F
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/* Audio Interface Setting Register 4 */
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#define AIC31XX_IFACESEC2 0x20
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/* Audio Interface Setting Register 5 */
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#define AIC31XX_IFACESEC3 0x21
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/* I2C Bus Condition */
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#define AIC31XX_I2C 0x22
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/* ADC FLAG */
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#define AIC31XX_ADCFLAG 0x24
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/* DAC Flag Registers */
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#define AIC31XX_DACFLAG1 0x25
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#define AIC31XX_DACFLAG2 0x26
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/* Sticky Interrupt flag (overflow) */
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#define AIC31XX_OFFLAG 0x27
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/* Sticy DAC Interrupt flags */
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#define AIC31XX_INTRDACFLAG 0x2C
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/* Sticy ADC Interrupt flags */
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#define AIC31XX_INTRADCFLAG 0x2D
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/* DAC Interrupt flags 2 */
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#define AIC31XX_INTRDACFLAG2 0x2E
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/* ADC Interrupt flags 2 */
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#define AIC31XX_INTRADCFLAG2 0x2F
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/* INT1 interrupt control */
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#define AIC31XX_INT1CTRL 0x30
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/* INT2 interrupt control */
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#define AIC31XX_INT2CTRL 0x31
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/* GPIO1 control */
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#define AIC31XX_GPIO1 0x33
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#define AIC31XX_DACPRB 0x3C
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/* ADC Instruction Set Register */
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#define AIC31XX_ADCPRB 0x3D
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/* DAC channel setup register */
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#define AIC31XX_DACSETUP 0x3F
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/* DAC Mute and volume control register */
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#define AIC31XX_DACMUTE 0x40
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/* Left DAC channel digital volume control */
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#define AIC31XX_LDACVOL 0x41
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/* Right DAC channel digital volume control */
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#define AIC31XX_RDACVOL 0x42
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/* Headset detection */
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#define AIC31XX_HSDETECT 0x43
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/* ADC Digital Mic */
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#define AIC31XX_ADCSETUP 0x51
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/* ADC Digital Volume Control Fine Adjust */
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#define AIC31XX_ADCFGA 0x52
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/* ADC Digital Volume Control Coarse Adjust */
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#define AIC31XX_ADCVOL 0x53
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/* Page 1 Registers */
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/* Headphone drivers */
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#define AIC31XX_HPDRIVER 0x9F
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/* Class-D Speakear Amplifier */
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#define AIC31XX_SPKAMP 0xA0
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/* HP Output Drivers POP Removal Settings */
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#define AIC31XX_HPPOP 0xA1
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/* Output Driver PGA Ramp-Down Period Control */
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#define AIC31XX_SPPGARAMP 0xA2
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/* DAC_L and DAC_R Output Mixer Routing */
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#define AIC31XX_DACMIXERROUTE 0xA3
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/* Left Analog Vol to HPL */
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#define AIC31XX_LANALOGHPL 0xA4
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/* Right Analog Vol to HPR */
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#define AIC31XX_RANALOGHPR 0xA5
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/* Left Analog Vol to SPL */
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#define AIC31XX_LANALOGSPL 0xA6
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/* Right Analog Vol to SPR */
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#define AIC31XX_RANALOGSPR 0xA7
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/* HPL Driver */
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#define AIC31XX_HPLGAIN 0xA8
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/* HPR Driver */
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#define AIC31XX_HPRGAIN 0xA9
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/* SPL Driver */
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#define AIC31XX_SPLGAIN 0xAA
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/* SPR Driver */
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#define AIC31XX_SPRGAIN 0xAB
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/* HP Driver Control */
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#define AIC31XX_HPCONTROL 0xAC
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/* MIC Bias Control */
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#define AIC31XX_MICBIAS 0xAE
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/* MIC PGA*/
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#define AIC31XX_MICPGA 0xAF
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/* Delta-Sigma Mono ADC Channel Fine-Gain Input Selection for P-Terminal */
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#define AIC31XX_MICPGAPI 0xB0
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/* ADC Input Selection for M-Terminal */
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#define AIC31XX_MICPGAMI 0xB1
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/* Input CM Settings */
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#define AIC31XX_MICPGACM 0xB2
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/* Bits, masks and shifts */
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/* AIC31XX_CLKMUX */
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#define AIC31XX_PLL_CLKIN_MASK 0x0c
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#define AIC31XX_PLL_CLKIN_SHIFT 2
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#define AIC31XX_PLL_CLKIN_MCLK 0
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#define AIC31XX_CODEC_CLKIN_MASK 0x03
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#define AIC31XX_CODEC_CLKIN_SHIFT 0
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#define AIC31XX_CODEC_CLKIN_PLL 3
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#define AIC31XX_CODEC_CLKIN_BCLK 1
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/* AIC31XX_PLLPR, AIC31XX_NDAC, AIC31XX_MDAC, AIC31XX_NADC, AIC31XX_MADC,
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AIC31XX_BCLKN */
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#define AIC31XX_PLL_MASK 0x7f
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#define AIC31XX_PM_MASK 0x80
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/* AIC31XX_IFACE1 */
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#define AIC31XX_WORD_LEN_16BITS 0x00
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#define AIC31XX_WORD_LEN_20BITS 0x01
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#define AIC31XX_WORD_LEN_24BITS 0x02
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#define AIC31XX_WORD_LEN_32BITS 0x03
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#define AIC31XX_IFACE1_DATALEN_MASK 0x30
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#define AIC31XX_IFACE1_DATALEN_SHIFT (4)
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#define AIC31XX_IFACE1_DATATYPE_MASK 0xC0
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#define AIC31XX_IFACE1_DATATYPE_SHIFT (6)
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#define AIC31XX_I2S_MODE 0x00
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#define AIC31XX_DSP_MODE 0x01
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#define AIC31XX_RIGHT_JUSTIFIED_MODE 0x02
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#define AIC31XX_LEFT_JUSTIFIED_MODE 0x03
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#define AIC31XX_IFACE1_MASTER_MASK 0x0C
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#define AIC31XX_BCLK_MASTER 0x08
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#define AIC31XX_WCLK_MASTER 0x04
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/* AIC31XX_DATA_OFFSET */
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#define AIC31XX_DATA_OFFSET_MASK 0xFF
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/* AIC31XX_IFACE2 */
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#define AIC31XX_BCLKINV_MASK 0x08
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#define AIC31XX_BDIVCLK_MASK 0x03
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#define AIC31XX_DAC2BCLK 0x00
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#define AIC31XX_DACMOD2BCLK 0x01
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#define AIC31XX_ADC2BCLK 0x02
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#define AIC31XX_ADCMOD2BCLK 0x03
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/* AIC31XX_ADCFLAG */
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#define AIC31XX_ADCPWRSTATUS_MASK 0x40
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/* AIC31XX_DACFLAG1 */
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#define AIC31XX_LDACPWRSTATUS_MASK 0x80
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#define AIC31XX_RDACPWRSTATUS_MASK 0x08
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#define AIC31XX_HPLDRVPWRSTATUS_MASK 0x20
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#define AIC31XX_HPRDRVPWRSTATUS_MASK 0x02
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#define AIC31XX_SPLDRVPWRSTATUS_MASK 0x10
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#define AIC31XX_SPRDRVPWRSTATUS_MASK 0x01
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/* AIC31XX_INTRDACFLAG */
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#define AIC31XX_HPSCDETECT_MASK 0x80
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#define AIC31XX_BUTTONPRESS_MASK 0x20
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#define AIC31XX_HSPLUG_MASK 0x10
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#define AIC31XX_LDRCTHRES_MASK 0x08
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#define AIC31XX_RDRCTHRES_MASK 0x04
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#define AIC31XX_DACSINT_MASK 0x02
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#define AIC31XX_DACAINT_MASK 0x01
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/* AIC31XX_INT1CTRL */
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#define AIC31XX_HSPLUGDET_MASK 0x80
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#define AIC31XX_BUTTONPRESSDET_MASK 0x40
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#define AIC31XX_DRCTHRES_MASK 0x20
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#define AIC31XX_AGCNOISE_MASK 0x10
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#define AIC31XX_OC_MASK 0x08
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#define AIC31XX_ENGINE_MASK 0x04
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/* AIC31XX_DACSETUP */
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#define AIC31XX_SOFTSTEP_MASK 0x03
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/* AIC31XX_DACMUTE */
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#define AIC31XX_DACMUTE_MASK 0x0C
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/* AIC31XX_MICBIAS */
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#define AIC31XX_MICBIAS_MASK 0x03
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#define AIC31XX_MICBIAS_SHIFT 0
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#endif /* _TLV320AIC31XX_H */
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