mirror of https://gitee.com/openkylin/linux.git
553 lines
15 KiB
C
553 lines
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_TLBFLUSH_H
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#define _ASM_X86_TLBFLUSH_H
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <asm/processor.h>
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#include <asm/cpufeature.h>
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#include <asm/special_insns.h>
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#include <asm/smp.h>
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#include <asm/invpcid.h>
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#include <asm/pti.h>
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#include <asm/processor-flags.h>
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/*
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* The x86 feature is called PCID (Process Context IDentifier). It is similar
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* to what is traditionally called ASID on the RISC processors.
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*
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* We don't use the traditional ASID implementation, where each process/mm gets
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* its own ASID and flush/restart when we run out of ASID space.
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*
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* Instead we have a small per-cpu array of ASIDs and cache the last few mm's
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* that came by on this CPU, allowing cheaper switch_mm between processes on
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* this CPU.
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*
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* We end up with different spaces for different things. To avoid confusion we
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* use different names for each of them:
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*
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* ASID - [0, TLB_NR_DYN_ASIDS-1]
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* the canonical identifier for an mm
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*
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* kPCID - [1, TLB_NR_DYN_ASIDS]
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* the value we write into the PCID part of CR3; corresponds to the
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* ASID+1, because PCID 0 is special.
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*
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* uPCID - [2048 + 1, 2048 + TLB_NR_DYN_ASIDS]
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* for KPTI each mm has two address spaces and thus needs two
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* PCID values, but we can still do with a single ASID denomination
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* for each mm. Corresponds to kPCID + 2048.
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*
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*/
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/* There are 12 bits of space for ASIDS in CR3 */
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#define CR3_HW_ASID_BITS 12
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/*
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* When enabled, PAGE_TABLE_ISOLATION consumes a single bit for
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* user/kernel switches
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*/
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#ifdef CONFIG_PAGE_TABLE_ISOLATION
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# define PTI_CONSUMED_PCID_BITS 1
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#else
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# define PTI_CONSUMED_PCID_BITS 0
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#endif
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#define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS)
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/*
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* ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid. -1 below to account
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* for them being zero-based. Another -1 is because PCID 0 is reserved for
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* use by non-PCID-aware users.
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*/
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#define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_PCID_BITS) - 2)
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/*
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* 6 because 6 should be plenty and struct tlb_state will fit in two cache
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* lines.
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*/
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#define TLB_NR_DYN_ASIDS 6
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/*
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* Given @asid, compute kPCID
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*/
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static inline u16 kern_pcid(u16 asid)
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{
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VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
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#ifdef CONFIG_PAGE_TABLE_ISOLATION
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/*
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* Make sure that the dynamic ASID space does not confict with the
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* bit we are using to switch between user and kernel ASIDs.
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*/
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BUILD_BUG_ON(TLB_NR_DYN_ASIDS >= (1 << X86_CR3_PTI_PCID_USER_BIT));
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/*
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* The ASID being passed in here should have respected the
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* MAX_ASID_AVAILABLE and thus never have the switch bit set.
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*/
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VM_WARN_ON_ONCE(asid & (1 << X86_CR3_PTI_PCID_USER_BIT));
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#endif
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/*
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* The dynamically-assigned ASIDs that get passed in are small
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* (<TLB_NR_DYN_ASIDS). They never have the high switch bit set,
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* so do not bother to clear it.
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*
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* If PCID is on, ASID-aware code paths put the ASID+1 into the
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* PCID bits. This serves two purposes. It prevents a nasty
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* situation in which PCID-unaware code saves CR3, loads some other
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* value (with PCID == 0), and then restores CR3, thus corrupting
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* the TLB for ASID 0 if the saved ASID was nonzero. It also means
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* that any bugs involving loading a PCID-enabled CR3 with
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* CR4.PCIDE off will trigger deterministically.
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*/
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return asid + 1;
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}
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/*
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* Given @asid, compute uPCID
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*/
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static inline u16 user_pcid(u16 asid)
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{
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u16 ret = kern_pcid(asid);
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#ifdef CONFIG_PAGE_TABLE_ISOLATION
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ret |= 1 << X86_CR3_PTI_PCID_USER_BIT;
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#endif
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return ret;
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}
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struct pgd_t;
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static inline unsigned long build_cr3(pgd_t *pgd, u16 asid)
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{
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if (static_cpu_has(X86_FEATURE_PCID)) {
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return __sme_pa(pgd) | kern_pcid(asid);
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} else {
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VM_WARN_ON_ONCE(asid != 0);
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return __sme_pa(pgd);
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}
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}
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static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
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{
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VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
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VM_WARN_ON_ONCE(!this_cpu_has(X86_FEATURE_PCID));
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return __sme_pa(pgd) | kern_pcid(asid) | CR3_NOFLUSH;
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}
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#define __flush_tlb() __native_flush_tlb()
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#define __flush_tlb_global() __native_flush_tlb_global()
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#define __flush_tlb_one_user(addr) __native_flush_tlb_one_user(addr)
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#endif
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static inline bool tlb_defer_switch_to_init_mm(void)
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{
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/*
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* If we have PCID, then switching to init_mm is reasonably
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* fast. If we don't have PCID, then switching to init_mm is
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* quite slow, so we try to defer it in the hopes that we can
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* avoid it entirely. The latter approach runs the risk of
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* receiving otherwise unnecessary IPIs.
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*
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* This choice is just a heuristic. The tlb code can handle this
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* function returning true or false regardless of whether we have
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* PCID.
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*/
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return !static_cpu_has(X86_FEATURE_PCID);
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}
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struct tlb_context {
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u64 ctx_id;
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u64 tlb_gen;
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};
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struct tlb_state {
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/*
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* cpu_tlbstate.loaded_mm should match CR3 whenever interrupts
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* are on. This means that it may not match current->active_mm,
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* which will contain the previous user mm when we're in lazy TLB
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* mode even if we've already switched back to swapper_pg_dir.
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*/
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struct mm_struct *loaded_mm;
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u16 loaded_mm_asid;
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u16 next_asid;
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/* last user mm's ctx id */
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u64 last_ctx_id;
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/*
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* We can be in one of several states:
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*
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* - Actively using an mm. Our CPU's bit will be set in
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* mm_cpumask(loaded_mm) and is_lazy == false;
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*
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* - Not using a real mm. loaded_mm == &init_mm. Our CPU's bit
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* will not be set in mm_cpumask(&init_mm) and is_lazy == false.
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*
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* - Lazily using a real mm. loaded_mm != &init_mm, our bit
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* is set in mm_cpumask(loaded_mm), but is_lazy == true.
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* We're heuristically guessing that the CR3 load we
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* skipped more than makes up for the overhead added by
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* lazy mode.
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*/
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bool is_lazy;
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/*
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* If set we changed the page tables in such a way that we
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* needed an invalidation of all contexts (aka. PCIDs / ASIDs).
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* This tells us to go invalidate all the non-loaded ctxs[]
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* on the next context switch.
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*
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* The current ctx was kept up-to-date as it ran and does not
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* need to be invalidated.
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*/
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bool invalidate_other;
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/*
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* Mask that contains TLB_NR_DYN_ASIDS+1 bits to indicate
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* the corresponding user PCID needs a flush next time we
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* switch to it; see SWITCH_TO_USER_CR3.
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*/
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unsigned short user_pcid_flush_mask;
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/*
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* Access to this CR4 shadow and to H/W CR4 is protected by
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* disabling interrupts when modifying either one.
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*/
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unsigned long cr4;
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/*
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* This is a list of all contexts that might exist in the TLB.
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* There is one per ASID that we use, and the ASID (what the
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* CPU calls PCID) is the index into ctxts.
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*
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* For each context, ctx_id indicates which mm the TLB's user
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* entries came from. As an invariant, the TLB will never
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* contain entries that are out-of-date as when that mm reached
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* the tlb_gen in the list.
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*
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* To be clear, this means that it's legal for the TLB code to
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* flush the TLB without updating tlb_gen. This can happen
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* (for now, at least) due to paravirt remote flushes.
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*
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* NB: context 0 is a bit special, since it's also used by
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* various bits of init code. This is fine -- code that
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* isn't aware of PCID will end up harmlessly flushing
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* context 0.
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*/
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struct tlb_context ctxs[TLB_NR_DYN_ASIDS];
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};
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DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate);
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/* Initialize cr4 shadow for this CPU. */
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static inline void cr4_init_shadow(void)
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{
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this_cpu_write(cpu_tlbstate.cr4, __read_cr4());
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}
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static inline void __cr4_set(unsigned long cr4)
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{
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lockdep_assert_irqs_disabled();
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this_cpu_write(cpu_tlbstate.cr4, cr4);
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__write_cr4(cr4);
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}
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/* Set in this cpu's CR4. */
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static inline void cr4_set_bits(unsigned long mask)
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{
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unsigned long cr4, flags;
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local_irq_save(flags);
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cr4 = this_cpu_read(cpu_tlbstate.cr4);
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if ((cr4 | mask) != cr4)
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__cr4_set(cr4 | mask);
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local_irq_restore(flags);
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}
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/* Clear in this cpu's CR4. */
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static inline void cr4_clear_bits(unsigned long mask)
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{
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unsigned long cr4, flags;
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local_irq_save(flags);
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cr4 = this_cpu_read(cpu_tlbstate.cr4);
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if ((cr4 & ~mask) != cr4)
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__cr4_set(cr4 & ~mask);
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local_irq_restore(flags);
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}
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static inline void cr4_toggle_bits_irqsoff(unsigned long mask)
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{
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unsigned long cr4;
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cr4 = this_cpu_read(cpu_tlbstate.cr4);
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__cr4_set(cr4 ^ mask);
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}
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/* Read the CR4 shadow. */
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static inline unsigned long cr4_read_shadow(void)
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{
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return this_cpu_read(cpu_tlbstate.cr4);
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}
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/*
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* Mark all other ASIDs as invalid, preserves the current.
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*/
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static inline void invalidate_other_asid(void)
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{
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this_cpu_write(cpu_tlbstate.invalidate_other, true);
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}
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/*
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* Save some of cr4 feature set we're using (e.g. Pentium 4MB
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* enable and PPro Global page enable), so that any CPU's that boot
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* up after us can get the correct flags. This should only be used
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* during boot on the boot cpu.
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*/
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extern unsigned long mmu_cr4_features;
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extern u32 *trampoline_cr4_features;
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static inline void cr4_set_bits_and_update_boot(unsigned long mask)
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{
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mmu_cr4_features |= mask;
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if (trampoline_cr4_features)
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*trampoline_cr4_features = mmu_cr4_features;
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cr4_set_bits(mask);
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}
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extern void initialize_tlbstate_and_flush(void);
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/*
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* Given an ASID, flush the corresponding user ASID. We can delay this
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* until the next time we switch to it.
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*
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* See SWITCH_TO_USER_CR3.
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*/
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static inline void invalidate_user_asid(u16 asid)
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{
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/* There is no user ASID if address space separation is off */
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if (!IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION))
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return;
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/*
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* We only have a single ASID if PCID is off and the CR3
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* write will have flushed it.
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*/
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if (!cpu_feature_enabled(X86_FEATURE_PCID))
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return;
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if (!static_cpu_has(X86_FEATURE_PTI))
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return;
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__set_bit(kern_pcid(asid),
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(unsigned long *)this_cpu_ptr(&cpu_tlbstate.user_pcid_flush_mask));
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}
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/*
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* flush the entire current user mapping
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*/
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static inline void __native_flush_tlb(void)
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{
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/*
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* Preemption or interrupts must be disabled to protect the access
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* to the per CPU variable and to prevent being preempted between
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* read_cr3() and write_cr3().
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*/
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WARN_ON_ONCE(preemptible());
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invalidate_user_asid(this_cpu_read(cpu_tlbstate.loaded_mm_asid));
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/* If current->mm == NULL then the read_cr3() "borrows" an mm */
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native_write_cr3(__native_read_cr3());
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}
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/*
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* flush everything
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*/
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static inline void __native_flush_tlb_global(void)
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{
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unsigned long cr4, flags;
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if (static_cpu_has(X86_FEATURE_INVPCID)) {
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/*
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* Using INVPCID is considerably faster than a pair of writes
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* to CR4 sandwiched inside an IRQ flag save/restore.
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*
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* Note, this works with CR4.PCIDE=0 or 1.
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*/
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invpcid_flush_all();
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return;
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}
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/*
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* Read-modify-write to CR4 - protect it from preemption and
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* from interrupts. (Use the raw variant because this code can
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* be called from deep inside debugging code.)
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*/
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raw_local_irq_save(flags);
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cr4 = this_cpu_read(cpu_tlbstate.cr4);
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/* toggle PGE */
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native_write_cr4(cr4 ^ X86_CR4_PGE);
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/* write old PGE again and flush TLBs */
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native_write_cr4(cr4);
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raw_local_irq_restore(flags);
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}
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/*
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* flush one page in the user mapping
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*/
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static inline void __native_flush_tlb_one_user(unsigned long addr)
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{
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u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
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asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
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if (!static_cpu_has(X86_FEATURE_PTI))
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return;
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/*
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* Some platforms #GP if we call invpcid(type=1/2) before CR4.PCIDE=1.
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* Just use invalidate_user_asid() in case we are called early.
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*/
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if (!this_cpu_has(X86_FEATURE_INVPCID_SINGLE))
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invalidate_user_asid(loaded_mm_asid);
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else
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invpcid_flush_one(user_pcid(loaded_mm_asid), addr);
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}
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/*
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* flush everything
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*/
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static inline void __flush_tlb_all(void)
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{
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if (boot_cpu_has(X86_FEATURE_PGE)) {
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__flush_tlb_global();
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} else {
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/*
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* !PGE -> !PCID (setup_pcid()), thus every flush is total.
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*/
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__flush_tlb();
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}
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}
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/*
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* flush one page in the kernel mapping
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*/
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static inline void __flush_tlb_one_kernel(unsigned long addr)
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{
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count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
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/*
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* If PTI is off, then __flush_tlb_one_user() is just INVLPG or its
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* paravirt equivalent. Even with PCID, this is sufficient: we only
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* use PCID if we also use global PTEs for the kernel mapping, and
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* INVLPG flushes global translations across all address spaces.
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*
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* If PTI is on, then the kernel is mapped with non-global PTEs, and
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* __flush_tlb_one_user() will flush the given address for the current
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* kernel address space and for its usermode counterpart, but it does
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* not flush it for other address spaces.
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*/
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__flush_tlb_one_user(addr);
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if (!static_cpu_has(X86_FEATURE_PTI))
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return;
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/*
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* See above. We need to propagate the flush to all other address
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* spaces. In principle, we only need to propagate it to kernelmode
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* address spaces, but the extra bookkeeping we would need is not
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* worth it.
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*/
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invalidate_other_asid();
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}
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#define TLB_FLUSH_ALL -1UL
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/*
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* TLB flushing:
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*
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* - flush_tlb_all() flushes all processes TLBs
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* - flush_tlb_mm(mm) flushes the specified mm context TLB's
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* - flush_tlb_page(vma, vmaddr) flushes one page
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* - flush_tlb_range(vma, start, end) flushes a range of pages
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* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
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* - flush_tlb_others(cpumask, info) flushes TLBs on other cpus
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*
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* ..but the i386 has somewhat limited tlb flushing capabilities,
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* and page-granular flushes are available only on i486 and up.
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*/
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struct flush_tlb_info {
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/*
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* We support several kinds of flushes.
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*
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* - Fully flush a single mm. .mm will be set, .end will be
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* TLB_FLUSH_ALL, and .new_tlb_gen will be the tlb_gen to
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* which the IPI sender is trying to catch us up.
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*
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* - Partially flush a single mm. .mm will be set, .start and
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* .end will indicate the range, and .new_tlb_gen will be set
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* such that the changes between generation .new_tlb_gen-1 and
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* .new_tlb_gen are entirely contained in the indicated range.
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*
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* - Fully flush all mms whose tlb_gens have been updated. .mm
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* will be NULL, .end will be TLB_FLUSH_ALL, and .new_tlb_gen
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|
* will be zero.
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|
*/
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|
struct mm_struct *mm;
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|
unsigned long start;
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|
unsigned long end;
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|
u64 new_tlb_gen;
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|
};
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|
|
|
#define local_flush_tlb() __flush_tlb()
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|
|
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#define flush_tlb_mm(mm) flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL)
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|
|
|
#define flush_tlb_range(vma, start, end) \
|
|
flush_tlb_mm_range(vma->vm_mm, start, end, vma->vm_flags)
|
|
|
|
extern void flush_tlb_all(void);
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|
extern void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
|
|
unsigned long end, unsigned long vmflag);
|
|
extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
|
|
|
|
static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long a)
|
|
{
|
|
flush_tlb_mm_range(vma->vm_mm, a, a + PAGE_SIZE, VM_NONE);
|
|
}
|
|
|
|
void native_flush_tlb_others(const struct cpumask *cpumask,
|
|
const struct flush_tlb_info *info);
|
|
|
|
static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
|
|
{
|
|
/*
|
|
* Bump the generation count. This also serves as a full barrier
|
|
* that synchronizes with switch_mm(): callers are required to order
|
|
* their read of mm_cpumask after their writes to the paging
|
|
* structures.
|
|
*/
|
|
return atomic64_inc_return(&mm->context.tlb_gen);
|
|
}
|
|
|
|
static inline void arch_tlbbatch_add_mm(struct arch_tlbflush_unmap_batch *batch,
|
|
struct mm_struct *mm)
|
|
{
|
|
inc_mm_tlb_gen(mm);
|
|
cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm));
|
|
}
|
|
|
|
extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch);
|
|
|
|
#ifndef CONFIG_PARAVIRT
|
|
#define flush_tlb_others(mask, info) \
|
|
native_flush_tlb_others(mask, info)
|
|
#endif
|
|
|
|
#endif /* _ASM_X86_TLBFLUSH_H */
|