mirror of https://gitee.com/openkylin/linux.git
1716 lines
44 KiB
Plaintext
1716 lines
44 KiB
Plaintext
/*
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* Copyright 2013 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/thermal/thermal.h>
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#include <dt-bindings/clock/sun4i-a10-pll2.h>
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#include <dt-bindings/dma/sun4i-a10.h>
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#include <dt-bindings/pinctrl/sun4i-a10.h>
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/ {
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interrupt-parent = <&gic>;
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aliases {
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ethernet0 = &gmac;
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};
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chosen {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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framebuffer@0 {
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0-hdmi";
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clocks = <&ahb_gates 36>, <&ahb_gates 43>,
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<&ahb_gates 44>, <&de_be0_clk>,
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<&tcon0_ch1_clk>, <&dram_gates 26>;
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status = "disabled";
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};
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framebuffer@1 {
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0";
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clocks = <&ahb_gates 36>, <&ahb_gates 44>,
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<&de_be0_clk>, <&tcon0_ch0_clk>,
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<&dram_gates 26>;
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status = "disabled";
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};
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framebuffer@2 {
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0-tve0";
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clocks = <&ahb_gates 34>, <&ahb_gates 36>,
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<&ahb_gates 44>,
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<&de_be0_clk>, <&tcon0_ch1_clk>,
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<&dram_gates 5>, <&dram_gates 26>;
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status = "disabled";
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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clocks = <&cpu>;
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clock-latency = <244144>; /* 8 32k periods */
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operating-points = <
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/* kHz uV */
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960000 1400000
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912000 1400000
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864000 1300000
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720000 1200000
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528000 1100000
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312000 1000000
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144000 1000000
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>;
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#cooling-cells = <2>;
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cooling-min-level = <0>;
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cooling-max-level = <6>;
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};
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cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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};
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};
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thermal-zones {
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cpu_thermal {
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/* milliseconds */
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&rtp>;
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cooling-maps {
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map0 {
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trip = <&cpu_alert0>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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trips {
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cpu_alert0: cpu_alert0 {
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/* milliCelsius */
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temperature = <75000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit: cpu_crit {
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/* milliCelsius */
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temperature = <100000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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};
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memory {
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reg = <0x40000000 0x80000000>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu {
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compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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osc24M: clk@01c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-osc-clk";
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reg = <0x01c20050 0x4>;
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc3M: osc3M_clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <8>;
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clock-mult = <1>;
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clocks = <&osc24M>;
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clock-output-names = "osc3M";
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};
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osc32k: clk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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pll1: clk@01c20000 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-pll1-clk";
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reg = <0x01c20000 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll1";
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};
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pll2: clk@01c20008 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-pll2-clk";
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reg = <0x01c20008 0x8>;
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clocks = <&osc24M>;
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clock-output-names = "pll2-1x", "pll2-2x",
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"pll2-4x", "pll2-8x";
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};
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pll3: clk@01c20010 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-pll3-clk";
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reg = <0x01c20010 0x4>;
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clocks = <&osc3M>;
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clock-output-names = "pll3";
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};
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pll3x2: pll3x2_clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&pll3>;
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clock-div = <1>;
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clock-mult = <2>;
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clock-output-names = "pll3-2x";
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};
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pll4: clk@01c20018 {
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#clock-cells = <0>;
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compatible = "allwinner,sun7i-a20-pll4-clk";
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reg = <0x01c20018 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll4";
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};
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pll5: clk@01c20020 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-pll5-clk";
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reg = <0x01c20020 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll5_ddr", "pll5_other";
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};
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pll6: clk@01c20028 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-pll6-clk";
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reg = <0x01c20028 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll6_sata", "pll6_other", "pll6",
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"pll6_div_4";
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};
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pll7: clk@01c20030 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-pll3-clk";
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reg = <0x01c20030 0x4>;
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clocks = <&osc3M>;
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clock-output-names = "pll7";
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};
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pll7x2: pll7x2_clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&pll7>;
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clock-div = <1>;
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clock-mult = <2>;
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clock-output-names = "pll7-2x";
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};
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pll8: clk@01c20040 {
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#clock-cells = <0>;
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compatible = "allwinner,sun7i-a20-pll4-clk";
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reg = <0x01c20040 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll8";
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};
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-cpu-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
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clock-output-names = "cpu";
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};
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axi: axi@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-axi-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&cpu>;
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clock-output-names = "axi";
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};
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ahb: ahb@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun5i-a13-ahb-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&axi>, <&pll6 3>, <&pll6 1>;
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clock-output-names = "ahb";
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/*
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* Use PLL6 as parent, instead of CPU/AXI
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* which has rate changes due to cpufreq
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*/
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assigned-clocks = <&ahb>;
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assigned-clock-parents = <&pll6 3>;
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};
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ahb_gates: clk@01c20060 {
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#clock-cells = <1>;
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compatible = "allwinner,sun7i-a20-ahb-gates-clk";
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reg = <0x01c20060 0x8>;
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clocks = <&ahb>;
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clock-indices = <0>, <1>,
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<2>, <3>, <4>,
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<5>, <6>, <7>, <8>,
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<9>, <10>, <11>, <12>,
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<13>, <14>, <16>,
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<17>, <18>, <20>, <21>,
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<22>, <23>, <25>,
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<28>, <32>, <33>, <34>,
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<35>, <36>, <37>, <40>,
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<41>, <42>, <43>,
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<44>, <45>, <46>,
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<47>, <49>, <50>,
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<52>;
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clock-output-names = "ahb_usb0", "ahb_ehci0",
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"ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
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"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
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"ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
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"ahb_nand", "ahb_sdram", "ahb_ace",
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"ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
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"ahb_spi2", "ahb_spi3", "ahb_sata",
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"ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
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"ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
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"ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
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"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
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"ahb_de_fe1", "ahb_gmac", "ahb_mp",
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"ahb_mali";
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};
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apb0: apb0@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-apb0-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&ahb>;
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clock-output-names = "apb0";
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};
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apb0_gates: clk@01c20068 {
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#clock-cells = <1>;
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compatible = "allwinner,sun7i-a20-apb0-gates-clk";
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reg = <0x01c20068 0x4>;
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clocks = <&apb0>;
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clock-indices = <0>, <1>,
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<2>, <3>, <4>,
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<5>, <6>, <7>,
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<8>, <10>;
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clock-output-names = "apb0_codec", "apb0_spdif",
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"apb0_ac97", "apb0_i2s0", "apb0_i2s1",
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"apb0_pio", "apb0_ir0", "apb0_ir1",
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"apb0_i2s2", "apb0_keypad";
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};
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apb1: clk@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-apb1-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
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clock-output-names = "apb1";
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};
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apb1_gates: clk@01c2006c {
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#clock-cells = <1>;
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compatible = "allwinner,sun7i-a20-apb1-gates-clk";
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reg = <0x01c2006c 0x4>;
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clocks = <&apb1>;
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clock-indices = <0>, <1>,
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<2>, <3>, <4>,
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<5>, <6>, <7>,
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<15>, <16>, <17>,
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<18>, <19>, <20>,
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<21>, <22>, <23>;
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clock-output-names = "apb1_i2c0", "apb1_i2c1",
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"apb1_i2c2", "apb1_i2c3", "apb1_can",
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"apb1_scr", "apb1_ps20", "apb1_ps21",
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"apb1_i2c4", "apb1_uart0", "apb1_uart1",
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"apb1_uart2", "apb1_uart3", "apb1_uart4",
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"apb1_uart5", "apb1_uart6", "apb1_uart7";
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};
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nand_clk: clk@01c20080 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c20080 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "nand";
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};
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ms_clk: clk@01c20084 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c20084 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ms";
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};
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mmc0_clk: clk@01c20088 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20088 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc0",
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"mmc0_output",
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"mmc0_sample";
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};
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mmc1_clk: clk@01c2008c {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c2008c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc1",
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"mmc1_output",
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"mmc1_sample";
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};
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mmc2_clk: clk@01c20090 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20090 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc2",
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"mmc2_output",
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"mmc2_sample";
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};
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mmc3_clk: clk@01c20094 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20094 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc3",
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"mmc3_output",
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"mmc3_sample";
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};
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ts_clk: clk@01c20098 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c20098 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ts";
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};
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ss_clk: clk@01c2009c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
|
|
reg = <0x01c2009c 0x4>;
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
clock-output-names = "ss";
|
|
};
|
|
|
|
spi0_clk: clk@01c200a0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
|
reg = <0x01c200a0 0x4>;
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
clock-output-names = "spi0";
|
|
};
|
|
|
|
spi1_clk: clk@01c200a4 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
|
reg = <0x01c200a4 0x4>;
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
clock-output-names = "spi1";
|
|
};
|
|
|
|
spi2_clk: clk@01c200a8 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
|
reg = <0x01c200a8 0x4>;
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
clock-output-names = "spi2";
|
|
};
|
|
|
|
pata_clk: clk@01c200ac {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
|
reg = <0x01c200ac 0x4>;
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
clock-output-names = "pata";
|
|
};
|
|
|
|
ir0_clk: clk@01c200b0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
|
reg = <0x01c200b0 0x4>;
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
clock-output-names = "ir0";
|
|
};
|
|
|
|
ir1_clk: clk@01c200b4 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
|
reg = <0x01c200b4 0x4>;
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
clock-output-names = "ir1";
|
|
};
|
|
|
|
i2s0_clk: clk@01c200b8 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-mod1-clk";
|
|
reg = <0x01c200b8 0x4>;
|
|
clocks = <&pll2 SUN4I_A10_PLL2_8X>,
|
|
<&pll2 SUN4I_A10_PLL2_4X>,
|
|
<&pll2 SUN4I_A10_PLL2_2X>,
|
|
<&pll2 SUN4I_A10_PLL2_1X>;
|
|
clock-output-names = "i2s0";
|
|
};
|
|
|
|
ac97_clk: clk@01c200bc {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-mod1-clk";
|
|
reg = <0x01c200bc 0x4>;
|
|
clocks = <&pll2 SUN4I_A10_PLL2_8X>,
|
|
<&pll2 SUN4I_A10_PLL2_4X>,
|
|
<&pll2 SUN4I_A10_PLL2_2X>,
|
|
<&pll2 SUN4I_A10_PLL2_1X>;
|
|
clock-output-names = "ac97";
|
|
};
|
|
|
|
spdif_clk: clk@01c200c0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-mod1-clk";
|
|
reg = <0x01c200c0 0x4>;
|
|
clocks = <&pll2 SUN4I_A10_PLL2_8X>,
|
|
<&pll2 SUN4I_A10_PLL2_4X>,
|
|
<&pll2 SUN4I_A10_PLL2_2X>,
|
|
<&pll2 SUN4I_A10_PLL2_1X>;
|
|
clock-output-names = "spdif";
|
|
};
|
|
|
|
keypad_clk: clk@01c200c4 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
|
reg = <0x01c200c4 0x4>;
|
|
clocks = <&osc24M>;
|
|
clock-output-names = "keypad";
|
|
};
|
|
|
|
usb_clk: clk@01c200cc {
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
compatible = "allwinner,sun4i-a10-usb-clk";
|
|
reg = <0x01c200cc 0x4>;
|
|
clocks = <&pll6 1>;
|
|
clock-output-names = "usb_ohci0", "usb_ohci1",
|
|
"usb_phy";
|
|
};
|
|
|
|
spi3_clk: clk@01c200d4 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
|
reg = <0x01c200d4 0x4>;
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
clock-output-names = "spi3";
|
|
};
|
|
|
|
i2s1_clk: clk@01c200d8 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-mod1-clk";
|
|
reg = <0x01c200d8 0x4>;
|
|
clocks = <&pll2 SUN4I_A10_PLL2_8X>,
|
|
<&pll2 SUN4I_A10_PLL2_4X>,
|
|
<&pll2 SUN4I_A10_PLL2_2X>,
|
|
<&pll2 SUN4I_A10_PLL2_1X>;
|
|
clock-output-names = "i2s1";
|
|
};
|
|
|
|
i2s2_clk: clk@01c200dc {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-mod1-clk";
|
|
reg = <0x01c200dc 0x4>;
|
|
clocks = <&pll2 SUN4I_A10_PLL2_8X>,
|
|
<&pll2 SUN4I_A10_PLL2_4X>,
|
|
<&pll2 SUN4I_A10_PLL2_2X>,
|
|
<&pll2 SUN4I_A10_PLL2_1X>;
|
|
clock-output-names = "i2s2";
|
|
};
|
|
|
|
dram_gates: clk@01c20100 {
|
|
#clock-cells = <1>;
|
|
compatible = "allwinner,sun4i-a10-dram-gates-clk";
|
|
reg = <0x01c20100 0x4>;
|
|
clocks = <&pll5 0>;
|
|
clock-indices = <0>,
|
|
<1>, <2>,
|
|
<3>,
|
|
<4>,
|
|
<5>, <6>,
|
|
<15>,
|
|
<24>, <25>,
|
|
<26>, <27>,
|
|
<28>, <29>;
|
|
clock-output-names = "dram_ve",
|
|
"dram_csi0", "dram_csi1",
|
|
"dram_ts",
|
|
"dram_tvd",
|
|
"dram_tve0", "dram_tve1",
|
|
"dram_output",
|
|
"dram_de_fe1", "dram_de_fe0",
|
|
"dram_de_be0", "dram_de_be1",
|
|
"dram_de_mp", "dram_ace";
|
|
};
|
|
|
|
de_be0_clk: clk@01c20104 {
|
|
#clock-cells = <0>;
|
|
#reset-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-display-clk";
|
|
reg = <0x01c20104 0x4>;
|
|
clocks = <&pll3>, <&pll7>, <&pll5 1>;
|
|
clock-output-names = "de-be0";
|
|
};
|
|
|
|
de_be1_clk: clk@01c20108 {
|
|
#clock-cells = <0>;
|
|
#reset-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-display-clk";
|
|
reg = <0x01c20108 0x4>;
|
|
clocks = <&pll3>, <&pll7>, <&pll5 1>;
|
|
clock-output-names = "de-be1";
|
|
};
|
|
|
|
de_fe0_clk: clk@01c2010c {
|
|
#clock-cells = <0>;
|
|
#reset-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-display-clk";
|
|
reg = <0x01c2010c 0x4>;
|
|
clocks = <&pll3>, <&pll7>, <&pll5 1>;
|
|
clock-output-names = "de-fe0";
|
|
};
|
|
|
|
de_fe1_clk: clk@01c20110 {
|
|
#clock-cells = <0>;
|
|
#reset-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-display-clk";
|
|
reg = <0x01c20110 0x4>;
|
|
clocks = <&pll3>, <&pll7>, <&pll5 1>;
|
|
clock-output-names = "de-fe1";
|
|
};
|
|
|
|
tcon0_ch0_clk: clk@01c20118 {
|
|
#clock-cells = <0>;
|
|
#reset-cells = <1>;
|
|
compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
|
|
reg = <0x01c20118 0x4>;
|
|
clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
|
|
clock-output-names = "tcon0-ch0-sclk";
|
|
|
|
};
|
|
|
|
tcon1_ch0_clk: clk@01c2011c {
|
|
#clock-cells = <0>;
|
|
#reset-cells = <1>;
|
|
compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
|
|
reg = <0x01c2011c 0x4>;
|
|
clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
|
|
clock-output-names = "tcon1-ch0-sclk";
|
|
|
|
};
|
|
|
|
tcon0_ch1_clk: clk@01c2012c {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
|
|
reg = <0x01c2012c 0x4>;
|
|
clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
|
|
clock-output-names = "tcon0-ch1-sclk";
|
|
|
|
};
|
|
|
|
tcon1_ch1_clk: clk@01c20130 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
|
|
reg = <0x01c20130 0x4>;
|
|
clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
|
|
clock-output-names = "tcon1-ch1-sclk";
|
|
|
|
};
|
|
|
|
ve_clk: clk@01c2013c {
|
|
#clock-cells = <0>;
|
|
#reset-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-ve-clk";
|
|
reg = <0x01c2013c 0x4>;
|
|
clocks = <&pll4>;
|
|
clock-output-names = "ve";
|
|
};
|
|
|
|
codec_clk: clk@01c20140 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-codec-clk";
|
|
reg = <0x01c20140 0x4>;
|
|
clocks = <&pll2 SUN4I_A10_PLL2_1X>;
|
|
clock-output-names = "codec";
|
|
};
|
|
|
|
mbus_clk: clk@01c2015c {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun5i-a13-mbus-clk";
|
|
reg = <0x01c2015c 0x4>;
|
|
clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
|
|
clock-output-names = "mbus";
|
|
};
|
|
|
|
/*
|
|
* The following two are dummy clocks, placeholders
|
|
* used in the gmac_tx clock. The gmac driver will
|
|
* choose one parent depending on the PHY interface
|
|
* mode, using clk_set_rate auto-reparenting.
|
|
*
|
|
* The actual TX clock rate is not controlled by the
|
|
* gmac_tx clock.
|
|
*/
|
|
mii_phy_tx_clk: clk@2 {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <25000000>;
|
|
clock-output-names = "mii_phy_tx";
|
|
};
|
|
|
|
gmac_int_tx_clk: clk@3 {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <125000000>;
|
|
clock-output-names = "gmac_int_tx";
|
|
};
|
|
|
|
gmac_tx_clk: clk@01c20164 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun7i-a20-gmac-clk";
|
|
reg = <0x01c20164 0x4>;
|
|
clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
|
|
clock-output-names = "gmac_tx";
|
|
};
|
|
|
|
/*
|
|
* Dummy clock used by output clocks
|
|
*/
|
|
osc24M_32k: clk@1 {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-factor-clock";
|
|
clock-div = <750>;
|
|
clock-mult = <1>;
|
|
clocks = <&osc24M>;
|
|
clock-output-names = "osc24M_32k";
|
|
};
|
|
|
|
clk_out_a: clk@01c201f0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun7i-a20-out-clk";
|
|
reg = <0x01c201f0 0x4>;
|
|
clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
|
|
clock-output-names = "clk_out_a";
|
|
};
|
|
|
|
clk_out_b: clk@01c201f4 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun7i-a20-out-clk";
|
|
reg = <0x01c201f4 0x4>;
|
|
clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
|
|
clock-output-names = "clk_out_b";
|
|
};
|
|
};
|
|
|
|
soc@01c00000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
sram-controller@01c00000 {
|
|
compatible = "allwinner,sun4i-a10-sram-controller";
|
|
reg = <0x01c00000 0x30>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
sram_a: sram@00000000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0x00000000 0xc000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x00000000 0xc000>;
|
|
|
|
emac_sram: sram-section@8000 {
|
|
compatible = "allwinner,sun4i-a10-sram-a3-a4";
|
|
reg = <0x8000 0x4000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
sram_d: sram@00010000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0x00010000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x00010000 0x1000>;
|
|
|
|
otg_sram: sram-section@0000 {
|
|
compatible = "allwinner,sun4i-a10-sram-d";
|
|
reg = <0x0000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
nmi_intc: interrupt-controller@01c00030 {
|
|
compatible = "allwinner,sun7i-a20-sc-nmi";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x01c00030 0x0c>;
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
dma: dma-controller@01c02000 {
|
|
compatible = "allwinner,sun4i-a10-dma";
|
|
reg = <0x01c02000 0x1000>;
|
|
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb_gates 6>;
|
|
#dma-cells = <2>;
|
|
};
|
|
|
|
nfc: nand@01c03000 {
|
|
compatible = "allwinner,sun4i-a10-nand";
|
|
reg = <0x01c03000 0x1000>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb_gates 13>, <&nand_clk>;
|
|
clock-names = "ahb", "mod";
|
|
dmas = <&dma SUN4I_DMA_DEDICATED 3>;
|
|
dma-names = "rxtx";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
spi0: spi@01c05000 {
|
|
compatible = "allwinner,sun4i-a10-spi";
|
|
reg = <0x01c05000 0x1000>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb_gates 20>, <&spi0_clk>;
|
|
clock-names = "ahb", "mod";
|
|
dmas = <&dma SUN4I_DMA_DEDICATED 27>,
|
|
<&dma SUN4I_DMA_DEDICATED 26>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
spi1: spi@01c06000 {
|
|
compatible = "allwinner,sun4i-a10-spi";
|
|
reg = <0x01c06000 0x1000>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb_gates 21>, <&spi1_clk>;
|
|
clock-names = "ahb", "mod";
|
|
dmas = <&dma SUN4I_DMA_DEDICATED 9>,
|
|
<&dma SUN4I_DMA_DEDICATED 8>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
emac: ethernet@01c0b000 {
|
|
compatible = "allwinner,sun4i-a10-emac";
|
|
reg = <0x01c0b000 0x1000>;
|
|
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb_gates 17>;
|
|
allwinner,sram = <&emac_sram 1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mdio: mdio@01c0b080 {
|
|
compatible = "allwinner,sun4i-a10-mdio";
|
|
reg = <0x01c0b080 0x14>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
mmc0: mmc@01c0f000 {
|
|
compatible = "allwinner,sun7i-a20-mmc";
|
|
reg = <0x01c0f000 0x1000>;
|
|
clocks = <&ahb_gates 8>,
|
|
<&mmc0_clk 0>,
|
|
<&mmc0_clk 1>,
|
|
<&mmc0_clk 2>;
|
|
clock-names = "ahb",
|
|
"mmc",
|
|
"output",
|
|
"sample";
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
mmc1: mmc@01c10000 {
|
|
compatible = "allwinner,sun7i-a20-mmc";
|
|
reg = <0x01c10000 0x1000>;
|
|
clocks = <&ahb_gates 9>,
|
|
<&mmc1_clk 0>,
|
|
<&mmc1_clk 1>,
|
|
<&mmc1_clk 2>;
|
|
clock-names = "ahb",
|
|
"mmc",
|
|
"output",
|
|
"sample";
|
|
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
mmc2: mmc@01c11000 {
|
|
compatible = "allwinner,sun7i-a20-mmc";
|
|
reg = <0x01c11000 0x1000>;
|
|
clocks = <&ahb_gates 10>,
|
|
<&mmc2_clk 0>,
|
|
<&mmc2_clk 1>,
|
|
<&mmc2_clk 2>;
|
|
clock-names = "ahb",
|
|
"mmc",
|
|
"output",
|
|
"sample";
|
|
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
mmc3: mmc@01c12000 {
|
|
compatible = "allwinner,sun7i-a20-mmc";
|
|
reg = <0x01c12000 0x1000>;
|
|
clocks = <&ahb_gates 11>,
|
|
<&mmc3_clk 0>,
|
|
<&mmc3_clk 1>,
|
|
<&mmc3_clk 2>;
|
|
clock-names = "ahb",
|
|
"mmc",
|
|
"output",
|
|
"sample";
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
usb_otg: usb@01c13000 {
|
|
compatible = "allwinner,sun4i-a10-musb";
|
|
reg = <0x01c13000 0x0400>;
|
|
clocks = <&ahb_gates 0>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "mc";
|
|
phys = <&usbphy 0>;
|
|
phy-names = "usb";
|
|
extcon = <&usbphy 0>;
|
|
allwinner,sram = <&otg_sram 1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbphy: phy@01c13400 {
|
|
#phy-cells = <1>;
|
|
compatible = "allwinner,sun7i-a20-usb-phy";
|
|
reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
|
|
reg-names = "phy_ctrl", "pmu1", "pmu2";
|
|
clocks = <&usb_clk 8>;
|
|
clock-names = "usb_phy";
|
|
resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
|
|
reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
|
|
status = "disabled";
|
|
};
|
|
|
|
ehci0: usb@01c14000 {
|
|
compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
|
|
reg = <0x01c14000 0x100>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb_gates 1>;
|
|
phys = <&usbphy 1>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
ohci0: usb@01c14400 {
|
|
compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
|
|
reg = <0x01c14400 0x100>;
|
|
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&usb_clk 6>, <&ahb_gates 2>;
|
|
phys = <&usbphy 1>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
crypto: crypto-engine@01c15000 {
|
|
compatible = "allwinner,sun4i-a10-crypto";
|
|
reg = <0x01c15000 0x1000>;
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb_gates 5>, <&ss_clk>;
|
|
clock-names = "ahb", "mod";
|
|
};
|
|
|
|
spi2: spi@01c17000 {
|
|
compatible = "allwinner,sun4i-a10-spi";
|
|
reg = <0x01c17000 0x1000>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb_gates 22>, <&spi2_clk>;
|
|
clock-names = "ahb", "mod";
|
|
dmas = <&dma SUN4I_DMA_DEDICATED 29>,
|
|
<&dma SUN4I_DMA_DEDICATED 28>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
ahci: sata@01c18000 {
|
|
compatible = "allwinner,sun4i-a10-ahci";
|
|
reg = <0x01c18000 0x1000>;
|
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pll6 0>, <&ahb_gates 25>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ehci1: usb@01c1c000 {
|
|
compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
|
|
reg = <0x01c1c000 0x100>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb_gates 3>;
|
|
phys = <&usbphy 2>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
ohci1: usb@01c1c400 {
|
|
compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
|
|
reg = <0x01c1c400 0x100>;
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&usb_clk 7>, <&ahb_gates 4>;
|
|
phys = <&usbphy 2>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi3: spi@01c1f000 {
|
|
compatible = "allwinner,sun4i-a10-spi";
|
|
reg = <0x01c1f000 0x1000>;
|
|
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb_gates 23>, <&spi3_clk>;
|
|
clock-names = "ahb", "mod";
|
|
dmas = <&dma SUN4I_DMA_DEDICATED 31>,
|
|
<&dma SUN4I_DMA_DEDICATED 30>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
pio: pinctrl@01c20800 {
|
|
compatible = "allwinner,sun7i-a20-pinctrl";
|
|
reg = <0x01c20800 0x400>;
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
|
|
clock-names = "apb", "hosc", "losc";
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
#gpio-cells = <3>;
|
|
|
|
clk_out_a_pins_a: clk_out_a@0 {
|
|
allwinner,pins = "PI12";
|
|
allwinner,function = "clk_out_a";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
clk_out_b_pins_a: clk_out_b@0 {
|
|
allwinner,pins = "PI13";
|
|
allwinner,function = "clk_out_b";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
emac_pins_a: emac0@0 {
|
|
allwinner,pins = "PA0", "PA1", "PA2",
|
|
"PA3", "PA4", "PA5", "PA6",
|
|
"PA7", "PA8", "PA9", "PA10",
|
|
"PA11", "PA12", "PA13", "PA14",
|
|
"PA15", "PA16";
|
|
allwinner,function = "emac";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
gmac_pins_mii_a: gmac_mii@0 {
|
|
allwinner,pins = "PA0", "PA1", "PA2",
|
|
"PA3", "PA4", "PA5", "PA6",
|
|
"PA7", "PA8", "PA9", "PA10",
|
|
"PA11", "PA12", "PA13", "PA14",
|
|
"PA15", "PA16";
|
|
allwinner,function = "gmac";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
gmac_pins_rgmii_a: gmac_rgmii@0 {
|
|
allwinner,pins = "PA0", "PA1", "PA2",
|
|
"PA3", "PA4", "PA5", "PA6",
|
|
"PA7", "PA8", "PA10",
|
|
"PA11", "PA12", "PA13",
|
|
"PA15", "PA16";
|
|
allwinner,function = "gmac";
|
|
/*
|
|
* data lines in RGMII mode use DDR mode
|
|
* and need a higher signal drive strength
|
|
*/
|
|
allwinner,drive = <SUN4I_PINCTRL_40_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
i2c0_pins_a: i2c0@0 {
|
|
allwinner,pins = "PB0", "PB1";
|
|
allwinner,function = "i2c0";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
i2c1_pins_a: i2c1@0 {
|
|
allwinner,pins = "PB18", "PB19";
|
|
allwinner,function = "i2c1";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
i2c2_pins_a: i2c2@0 {
|
|
allwinner,pins = "PB20", "PB21";
|
|
allwinner,function = "i2c2";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
i2c3_pins_a: i2c3@0 {
|
|
allwinner,pins = "PI0", "PI1";
|
|
allwinner,function = "i2c3";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
ir0_rx_pins_a: ir0@0 {
|
|
allwinner,pins = "PB4";
|
|
allwinner,function = "ir0";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
ir0_tx_pins_a: ir0@1 {
|
|
allwinner,pins = "PB3";
|
|
allwinner,function = "ir0";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
ir1_rx_pins_a: ir1@0 {
|
|
allwinner,pins = "PB23";
|
|
allwinner,function = "ir1";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
ir1_tx_pins_a: ir1@1 {
|
|
allwinner,pins = "PB22";
|
|
allwinner,function = "ir1";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
mmc0_pins_a: mmc0@0 {
|
|
allwinner,pins = "PF0", "PF1", "PF2",
|
|
"PF3", "PF4", "PF5";
|
|
allwinner,function = "mmc0";
|
|
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
|
|
allwinner,pins = "PH1";
|
|
allwinner,function = "gpio_in";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
|
|
};
|
|
|
|
mmc2_pins_a: mmc2@0 {
|
|
allwinner,pins = "PC6", "PC7", "PC8",
|
|
"PC9", "PC10", "PC11";
|
|
allwinner,function = "mmc2";
|
|
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
|
|
};
|
|
|
|
mmc3_pins_a: mmc3@0 {
|
|
allwinner,pins = "PI4", "PI5", "PI6",
|
|
"PI7", "PI8", "PI9";
|
|
allwinner,function = "mmc3";
|
|
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
ps20_pins_a: ps20@0 {
|
|
allwinner,pins = "PI20", "PI21";
|
|
allwinner,function = "ps2";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
ps21_pins_a: ps21@0 {
|
|
allwinner,pins = "PH12", "PH13";
|
|
allwinner,function = "ps2";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
pwm0_pins_a: pwm0@0 {
|
|
allwinner,pins = "PB2";
|
|
allwinner,function = "pwm";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
pwm1_pins_a: pwm1@0 {
|
|
allwinner,pins = "PI3";
|
|
allwinner,function = "pwm";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
spdif_tx_pins_a: spdif@0 {
|
|
allwinner,pins = "PB13";
|
|
allwinner,function = "spdif";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
|
|
};
|
|
|
|
spi0_pins_a: spi0@0 {
|
|
allwinner,pins = "PI11", "PI12", "PI13";
|
|
allwinner,function = "spi0";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
spi0_cs0_pins_a: spi0_cs0@0 {
|
|
allwinner,pins = "PI10";
|
|
allwinner,function = "spi0";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
spi0_cs1_pins_a: spi0_cs1@0 {
|
|
allwinner,pins = "PI14";
|
|
allwinner,function = "spi0";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
spi1_pins_a: spi1@0 {
|
|
allwinner,pins = "PI17", "PI18", "PI19";
|
|
allwinner,function = "spi1";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
spi1_cs0_pins_a: spi1_cs0@0 {
|
|
allwinner,pins = "PI16";
|
|
allwinner,function = "spi1";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
spi2_pins_a: spi2@0 {
|
|
allwinner,pins = "PC20", "PC21", "PC22";
|
|
allwinner,function = "spi2";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
spi2_pins_b: spi2@1 {
|
|
allwinner,pins = "PB15", "PB16", "PB17";
|
|
allwinner,function = "spi2";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
spi2_cs0_pins_a: spi2_cs0@0 {
|
|
allwinner,pins = "PC19";
|
|
allwinner,function = "spi2";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
spi2_cs0_pins_b: spi2_cs0@1 {
|
|
allwinner,pins = "PB14";
|
|
allwinner,function = "spi2";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
uart0_pins_a: uart0@0 {
|
|
allwinner,pins = "PB22", "PB23";
|
|
allwinner,function = "uart0";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
uart2_pins_a: uart2@0 {
|
|
allwinner,pins = "PI16", "PI17", "PI18", "PI19";
|
|
allwinner,function = "uart2";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
uart3_pins_a: uart3@0 {
|
|
allwinner,pins = "PG6", "PG7", "PG8", "PG9";
|
|
allwinner,function = "uart3";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
uart3_pins_b: uart3@1 {
|
|
allwinner,pins = "PH0", "PH1";
|
|
allwinner,function = "uart3";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
uart4_pins_a: uart4@0 {
|
|
allwinner,pins = "PG10", "PG11";
|
|
allwinner,function = "uart4";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
uart4_pins_b: uart4@1 {
|
|
allwinner,pins = "PH4", "PH5";
|
|
allwinner,function = "uart4";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
uart5_pins_a: uart5@0 {
|
|
allwinner,pins = "PI10", "PI11";
|
|
allwinner,function = "uart5";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
uart6_pins_a: uart6@0 {
|
|
allwinner,pins = "PI12", "PI13";
|
|
allwinner,function = "uart6";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
uart7_pins_a: uart7@0 {
|
|
allwinner,pins = "PI20", "PI21";
|
|
allwinner,function = "uart7";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
};
|
|
|
|
timer@01c20c00 {
|
|
compatible = "allwinner,sun4i-a10-timer";
|
|
reg = <0x01c20c00 0x90>;
|
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&osc24M>;
|
|
};
|
|
|
|
wdt: watchdog@01c20c90 {
|
|
compatible = "allwinner,sun4i-a10-wdt";
|
|
reg = <0x01c20c90 0x10>;
|
|
};
|
|
|
|
rtc: rtc@01c20d00 {
|
|
compatible = "allwinner,sun7i-a20-rtc";
|
|
reg = <0x01c20d00 0x20>;
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
pwm: pwm@01c20e00 {
|
|
compatible = "allwinner,sun7i-a20-pwm";
|
|
reg = <0x01c20e00 0xc>;
|
|
clocks = <&osc24M>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spdif: spdif@01c21000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-spdif";
|
|
reg = <0x01c21000 0x400>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb0_gates 1>, <&spdif_clk>;
|
|
clock-names = "apb", "spdif";
|
|
dmas = <&dma SUN4I_DMA_NORMAL 2>,
|
|
<&dma SUN4I_DMA_NORMAL 2>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
ir0: ir@01c21800 {
|
|
compatible = "allwinner,sun4i-a10-ir";
|
|
clocks = <&apb0_gates 6>, <&ir0_clk>;
|
|
clock-names = "apb", "ir";
|
|
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x01c21800 0x40>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ir1: ir@01c21c00 {
|
|
compatible = "allwinner,sun4i-a10-ir";
|
|
clocks = <&apb0_gates 7>, <&ir1_clk>;
|
|
clock-names = "apb", "ir";
|
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x01c21c00 0x40>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s1: i2s@01c22000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-i2s";
|
|
reg = <0x01c22000 0x400>;
|
|
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb0_gates 4>, <&i2s1_clk>;
|
|
clock-names = "apb", "mod";
|
|
dmas = <&dma SUN4I_DMA_NORMAL 4>,
|
|
<&dma SUN4I_DMA_NORMAL 4>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s0: i2s@01c22400 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-i2s";
|
|
reg = <0x01c22400 0x400>;
|
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb0_gates 3>, <&i2s0_clk>;
|
|
clock-names = "apb", "mod";
|
|
dmas = <&dma SUN4I_DMA_NORMAL 3>,
|
|
<&dma SUN4I_DMA_NORMAL 3>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
lradc: lradc@01c22800 {
|
|
compatible = "allwinner,sun4i-a10-lradc-keys";
|
|
reg = <0x01c22800 0x100>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
codec: codec@01c22c00 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "allwinner,sun7i-a20-codec";
|
|
reg = <0x01c22c00 0x40>;
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb0_gates 0>, <&codec_clk>;
|
|
clock-names = "apb", "codec";
|
|
dmas = <&dma SUN4I_DMA_NORMAL 19>,
|
|
<&dma SUN4I_DMA_NORMAL 19>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
sid: eeprom@01c23800 {
|
|
compatible = "allwinner,sun7i-a20-sid";
|
|
reg = <0x01c23800 0x200>;
|
|
};
|
|
|
|
i2s2: i2s@01c24400 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-i2s";
|
|
reg = <0x01c24400 0x400>;
|
|
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb0_gates 8>, <&i2s2_clk>;
|
|
clock-names = "apb", "mod";
|
|
dmas = <&dma SUN4I_DMA_NORMAL 6>,
|
|
<&dma SUN4I_DMA_NORMAL 6>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
rtp: rtp@01c25000 {
|
|
compatible = "allwinner,sun5i-a13-ts";
|
|
reg = <0x01c25000 0x100>;
|
|
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
#thermal-sensor-cells = <0>;
|
|
};
|
|
|
|
uart0: serial@01c28000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28000 0x400>;
|
|
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb1_gates 16>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@01c28400 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28400 0x400>;
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb1_gates 17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@01c28800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28800 0x400>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb1_gates 18>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@01c28c00 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28c00 0x400>;
|
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb1_gates 19>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@01c29000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29000 0x400>;
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb1_gates 20>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@01c29400 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29400 0x400>;
|
|
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb1_gates 21>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart6: serial@01c29800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29800 0x400>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb1_gates 22>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart7: serial@01c29c00 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29c00 0x400>;
|
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb1_gates 23>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@01c2ac00 {
|
|
compatible = "allwinner,sun7i-a20-i2c",
|
|
"allwinner,sun4i-a10-i2c";
|
|
reg = <0x01c2ac00 0x400>;
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb1_gates 0>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c1: i2c@01c2b000 {
|
|
compatible = "allwinner,sun7i-a20-i2c",
|
|
"allwinner,sun4i-a10-i2c";
|
|
reg = <0x01c2b000 0x400>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb1_gates 1>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c2: i2c@01c2b400 {
|
|
compatible = "allwinner,sun7i-a20-i2c",
|
|
"allwinner,sun4i-a10-i2c";
|
|
reg = <0x01c2b400 0x400>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb1_gates 2>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c3: i2c@01c2b800 {
|
|
compatible = "allwinner,sun7i-a20-i2c",
|
|
"allwinner,sun4i-a10-i2c";
|
|
reg = <0x01c2b800 0x400>;
|
|
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb1_gates 3>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c4: i2c@01c2c000 {
|
|
compatible = "allwinner,sun7i-a20-i2c",
|
|
"allwinner,sun4i-a10-i2c";
|
|
reg = <0x01c2c000 0x400>;
|
|
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb1_gates 15>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
gmac: ethernet@01c50000 {
|
|
compatible = "allwinner,sun7i-a20-gmac";
|
|
reg = <0x01c50000 0x10000>;
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
|
|
clock-names = "stmmaceth", "allwinner_gmac_tx";
|
|
snps,pbl = <2>;
|
|
snps,fixed-burst;
|
|
snps,force_sf_dma_mode;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
hstimer@01c60000 {
|
|
compatible = "allwinner,sun7i-a20-hstimer";
|
|
reg = <0x01c60000 0x1000>;
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb_gates 28>;
|
|
};
|
|
|
|
gic: interrupt-controller@01c81000 {
|
|
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
|
|
reg = <0x01c81000 0x1000>,
|
|
<0x01c82000 0x1000>,
|
|
<0x01c84000 0x2000>,
|
|
<0x01c86000 0x2000>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
};
|
|
|
|
ps20: ps2@01c2a000 {
|
|
compatible = "allwinner,sun4i-a10-ps2";
|
|
reg = <0x01c2a000 0x400>;
|
|
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb1_gates 6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ps21: ps2@01c2a400 {
|
|
compatible = "allwinner,sun4i-a10-ps2";
|
|
reg = <0x01c2a400 0x400>;
|
|
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb1_gates 7>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|