mirror of https://gitee.com/openkylin/linux.git
434 lines
13 KiB
C
434 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018, Intel Corporation. */
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#ifndef _ICE_H_
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#define _ICE_H_
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/compiler.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/cpumask.h>
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#include <linux/rtnetlink.h>
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#include <linux/if_vlan.h>
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#include <linux/dma-mapping.h>
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#include <linux/pci.h>
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#include <linux/workqueue.h>
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#include <linux/aer.h>
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#include <linux/interrupt.h>
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#include <linux/ethtool.h>
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#include <linux/timer.h>
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#include <linux/delay.h>
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#include <linux/bitmap.h>
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#include <linux/log2.h>
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#include <linux/ip.h>
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#include <linux/sctp.h>
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#include <linux/ipv6.h>
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#include <linux/if_bridge.h>
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#include <linux/avf/virtchnl.h>
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#include <net/ipv6.h>
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#include "ice_devids.h"
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#include "ice_type.h"
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#include "ice_txrx.h"
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#include "ice_dcb.h"
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#include "ice_switch.h"
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#include "ice_common.h"
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#include "ice_sched.h"
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#include "ice_virtchnl_pf.h"
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#include "ice_sriov.h"
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extern const char ice_drv_ver[];
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#define ICE_BAR0 0
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#define ICE_REQ_DESC_MULTIPLE 32
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#define ICE_MIN_NUM_DESC ICE_REQ_DESC_MULTIPLE
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#define ICE_MAX_NUM_DESC 8160
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/* set default number of Rx/Tx descriptors to the minimum between
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* ICE_MAX_NUM_DESC and the number of descriptors to fill up an entire page
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*/
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#define ICE_DFLT_NUM_RX_DESC min_t(u16, ICE_MAX_NUM_DESC, \
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ALIGN(PAGE_SIZE / \
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sizeof(union ice_32byte_rx_desc), \
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ICE_REQ_DESC_MULTIPLE))
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#define ICE_DFLT_NUM_TX_DESC min_t(u16, ICE_MAX_NUM_DESC, \
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ALIGN(PAGE_SIZE / \
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sizeof(struct ice_tx_desc), \
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ICE_REQ_DESC_MULTIPLE))
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#define ICE_DFLT_TRAFFIC_CLASS BIT(0)
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#define ICE_INT_NAME_STR_LEN (IFNAMSIZ + 16)
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#define ICE_ETHTOOL_FWVER_LEN 32
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#define ICE_AQ_LEN 64
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#define ICE_MBXQ_LEN 64
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#define ICE_MIN_MSIX 2
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#define ICE_NO_VSI 0xffff
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#define ICE_MAX_TXQS 2048
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#define ICE_MAX_RXQS 2048
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#define ICE_VSI_MAP_CONTIG 0
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#define ICE_VSI_MAP_SCATTER 1
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#define ICE_MAX_SCATTER_TXQS 16
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#define ICE_MAX_SCATTER_RXQS 16
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#define ICE_Q_WAIT_RETRY_LIMIT 10
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#define ICE_Q_WAIT_MAX_RETRY (5 * ICE_Q_WAIT_RETRY_LIMIT)
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#define ICE_MAX_LG_RSS_QS 256
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#define ICE_MAX_SMALL_RSS_QS 8
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#define ICE_RES_VALID_BIT 0x8000
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#define ICE_RES_MISC_VEC_ID (ICE_RES_VALID_BIT - 1)
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#define ICE_INVAL_Q_INDEX 0xffff
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#define ICE_INVAL_VFID 256
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#define ICE_MAX_VF_COUNT 256
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#define ICE_MAX_QS_PER_VF 256
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#define ICE_MIN_QS_PER_VF 1
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#define ICE_DFLT_QS_PER_VF 4
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#define ICE_MAX_BASE_QS_PER_VF 16
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#define ICE_MAX_INTR_PER_VF 65
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#define ICE_MIN_INTR_PER_VF (ICE_MIN_QS_PER_VF + 1)
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#define ICE_DFLT_INTR_PER_VF (ICE_DFLT_QS_PER_VF + 1)
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#define ICE_MAX_RESET_WAIT 20
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#define ICE_VSIQF_HKEY_ARRAY_SIZE ((VSIQF_HKEY_MAX_INDEX + 1) * 4)
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#define ICE_DFLT_NETIF_M (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
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#define ICE_MAX_MTU (ICE_AQ_SET_MAC_FRAME_SIZE_MAX - \
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(ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2)))
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#define ICE_UP_TABLE_TRANSLATE(val, i) \
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(((val) << ICE_AQ_VSI_UP_TABLE_UP##i##_S) & \
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ICE_AQ_VSI_UP_TABLE_UP##i##_M)
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#define ICE_TX_DESC(R, i) (&(((struct ice_tx_desc *)((R)->desc))[i]))
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#define ICE_RX_DESC(R, i) (&(((union ice_32b_rx_flex_desc *)((R)->desc))[i]))
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#define ICE_TX_CTX_DESC(R, i) (&(((struct ice_tx_ctx_desc *)((R)->desc))[i]))
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/* Macro for each VSI in a PF */
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#define ice_for_each_vsi(pf, i) \
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for ((i) = 0; (i) < (pf)->num_alloc_vsi; (i)++)
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/* Macros for each Tx/Rx ring in a VSI */
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#define ice_for_each_txq(vsi, i) \
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for ((i) = 0; (i) < (vsi)->num_txq; (i)++)
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#define ice_for_each_rxq(vsi, i) \
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for ((i) = 0; (i) < (vsi)->num_rxq; (i)++)
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/* Macros for each allocated Tx/Rx ring whether used or not in a VSI */
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#define ice_for_each_alloc_txq(vsi, i) \
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for ((i) = 0; (i) < (vsi)->alloc_txq; (i)++)
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#define ice_for_each_alloc_rxq(vsi, i) \
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for ((i) = 0; (i) < (vsi)->alloc_rxq; (i)++)
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#define ice_for_each_q_vector(vsi, i) \
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for ((i) = 0; (i) < (vsi)->num_q_vectors; (i)++)
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#define ICE_UCAST_PROMISC_BITS (ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX | \
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ICE_PROMISC_UCAST_RX | ICE_PROMISC_MCAST_RX)
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#define ICE_UCAST_VLAN_PROMISC_BITS (ICE_PROMISC_UCAST_TX | \
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ICE_PROMISC_MCAST_TX | \
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ICE_PROMISC_UCAST_RX | \
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ICE_PROMISC_MCAST_RX | \
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ICE_PROMISC_VLAN_TX | \
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ICE_PROMISC_VLAN_RX)
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#define ICE_MCAST_PROMISC_BITS (ICE_PROMISC_MCAST_TX | ICE_PROMISC_MCAST_RX)
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#define ICE_MCAST_VLAN_PROMISC_BITS (ICE_PROMISC_MCAST_TX | \
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ICE_PROMISC_MCAST_RX | \
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ICE_PROMISC_VLAN_TX | \
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ICE_PROMISC_VLAN_RX)
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struct ice_tc_info {
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u16 qoffset;
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u16 qcount_tx;
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u16 qcount_rx;
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u8 netdev_tc;
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};
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struct ice_tc_cfg {
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u8 numtc; /* Total number of enabled TCs */
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u8 ena_tc; /* Tx map */
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struct ice_tc_info tc_info[ICE_MAX_TRAFFIC_CLASS];
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};
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struct ice_res_tracker {
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u16 num_entries;
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u16 search_hint;
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u16 list[1];
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};
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struct ice_qs_cfg {
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struct mutex *qs_mutex; /* will be assigned to &pf->avail_q_mutex */
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unsigned long *pf_map;
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unsigned long pf_map_size;
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unsigned int q_count;
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unsigned int scatter_count;
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u16 *vsi_map;
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u16 vsi_map_offset;
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u8 mapping_mode;
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};
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struct ice_sw {
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struct ice_pf *pf;
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u16 sw_id; /* switch ID for this switch */
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u16 bridge_mode; /* VEB/VEPA/Port Virtualizer */
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};
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enum ice_state {
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__ICE_DOWN,
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__ICE_NEEDS_RESTART,
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__ICE_PREPARED_FOR_RESET, /* set by driver when prepared */
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__ICE_RESET_OICR_RECV, /* set by driver after rcv reset OICR */
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__ICE_PFR_REQ, /* set by driver and peers */
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__ICE_CORER_REQ, /* set by driver and peers */
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__ICE_GLOBR_REQ, /* set by driver and peers */
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__ICE_CORER_RECV, /* set by OICR handler */
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__ICE_GLOBR_RECV, /* set by OICR handler */
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__ICE_EMPR_RECV, /* set by OICR handler */
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__ICE_SUSPENDED, /* set on module remove path */
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__ICE_RESET_FAILED, /* set by reset/rebuild */
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/* When checking for the PF to be in a nominal operating state, the
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* bits that are grouped at the beginning of the list need to be
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* checked. Bits occurring before __ICE_STATE_NOMINAL_CHECK_BITS will
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* be checked. If you need to add a bit into consideration for nominal
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* operating state, it must be added before
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* __ICE_STATE_NOMINAL_CHECK_BITS. Do not move this entry's position
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* without appropriate consideration.
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*/
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__ICE_STATE_NOMINAL_CHECK_BITS,
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__ICE_ADMINQ_EVENT_PENDING,
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__ICE_MAILBOXQ_EVENT_PENDING,
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__ICE_MDD_EVENT_PENDING,
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__ICE_VFLR_EVENT_PENDING,
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__ICE_FLTR_OVERFLOW_PROMISC,
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__ICE_VF_DIS,
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__ICE_CFG_BUSY,
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__ICE_SERVICE_SCHED,
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__ICE_SERVICE_DIS,
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__ICE_STATE_NBITS /* must be last */
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};
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enum ice_vsi_flags {
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ICE_VSI_FLAG_UMAC_FLTR_CHANGED,
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ICE_VSI_FLAG_MMAC_FLTR_CHANGED,
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ICE_VSI_FLAG_VLAN_FLTR_CHANGED,
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ICE_VSI_FLAG_PROMISC_CHANGED,
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ICE_VSI_FLAG_NBITS /* must be last */
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};
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/* struct that defines a VSI, associated with a dev */
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struct ice_vsi {
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struct net_device *netdev;
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struct ice_sw *vsw; /* switch this VSI is on */
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struct ice_pf *back; /* back pointer to PF */
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struct ice_port_info *port_info; /* back pointer to port_info */
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struct ice_ring **rx_rings; /* Rx ring array */
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struct ice_ring **tx_rings; /* Tx ring array */
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struct ice_q_vector **q_vectors; /* q_vector array */
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irqreturn_t (*irq_handler)(int irq, void *data);
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u64 tx_linearize;
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DECLARE_BITMAP(state, __ICE_STATE_NBITS);
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DECLARE_BITMAP(flags, ICE_VSI_FLAG_NBITS);
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unsigned int current_netdev_flags;
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u32 tx_restart;
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u32 tx_busy;
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u32 rx_buf_failed;
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u32 rx_page_failed;
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int num_q_vectors;
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int sw_base_vector; /* Irq base for OS reserved vectors */
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int hw_base_vector; /* HW (absolute) index of a vector */
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enum ice_vsi_type type;
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u16 vsi_num; /* HW (absolute) index of this VSI */
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u16 idx; /* software index in pf->vsi[] */
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/* Interrupt thresholds */
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u16 work_lmt;
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s16 vf_id; /* VF ID for SR-IOV VSIs */
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/* RSS config */
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u16 rss_table_size; /* HW RSS table size */
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u16 rss_size; /* Allocated RSS queues */
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u8 *rss_hkey_user; /* User configured hash keys */
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u8 *rss_lut_user; /* User configured lookup table entries */
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u8 rss_lut_type; /* used to configure Get/Set RSS LUT AQ call */
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u16 max_frame;
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u16 rx_buf_len;
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struct ice_aqc_vsi_props info; /* VSI properties */
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/* VSI stats */
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struct rtnl_link_stats64 net_stats;
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struct ice_eth_stats eth_stats;
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struct ice_eth_stats eth_stats_prev;
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struct list_head tmp_sync_list; /* MAC filters to be synced */
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struct list_head tmp_unsync_list; /* MAC filters to be unsynced */
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u8 irqs_ready;
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u8 current_isup; /* Sync 'link up' logging */
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u8 stat_offsets_loaded;
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u8 vlan_ena;
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/* queue information */
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u8 tx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */
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u8 rx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */
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u16 txq_map[ICE_MAX_TXQS]; /* index in pf->avail_txqs */
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u16 rxq_map[ICE_MAX_RXQS]; /* index in pf->avail_rxqs */
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u16 alloc_txq; /* Allocated Tx queues */
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u16 num_txq; /* Used Tx queues */
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u16 alloc_rxq; /* Allocated Rx queues */
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u16 num_rxq; /* Used Rx queues */
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u16 num_rx_desc;
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u16 num_tx_desc;
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struct ice_tc_cfg tc_cfg;
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} ____cacheline_internodealigned_in_smp;
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/* struct that defines an interrupt vector */
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struct ice_q_vector {
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struct ice_vsi *vsi;
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u16 v_idx; /* index in the vsi->q_vector array. */
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u8 num_ring_rx; /* total number of Rx rings in vector */
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u8 num_ring_tx; /* total number of Tx rings in vector */
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u8 itr_countdown; /* when 0 should adjust adaptive ITR */
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/* in usecs, need to use ice_intrl_to_usecs_reg() before writing this
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* value to the device
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*/
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u8 intrl;
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struct napi_struct napi;
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struct ice_ring_container rx;
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struct ice_ring_container tx;
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cpumask_t affinity_mask;
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struct irq_affinity_notify affinity_notify;
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char name[ICE_INT_NAME_STR_LEN];
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} ____cacheline_internodealigned_in_smp;
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enum ice_pf_flags {
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ICE_FLAG_MSIX_ENA,
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ICE_FLAG_FLTR_SYNC,
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ICE_FLAG_RSS_ENA,
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ICE_FLAG_SRIOV_ENA,
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ICE_FLAG_SRIOV_CAPABLE,
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ICE_FLAG_DCB_CAPABLE,
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ICE_FLAG_DCB_ENA,
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ICE_FLAG_LINK_DOWN_ON_CLOSE_ENA,
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ICE_PF_FLAGS_NBITS /* must be last */
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};
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struct ice_pf {
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struct pci_dev *pdev;
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/* OS reserved IRQ details */
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struct msix_entry *msix_entries;
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struct ice_res_tracker *sw_irq_tracker;
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/* HW reserved Interrupts for this PF */
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struct ice_res_tracker *hw_irq_tracker;
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struct ice_vsi **vsi; /* VSIs created by the driver */
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struct ice_sw *first_sw; /* first switch created by firmware */
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/* Virtchnl/SR-IOV config info */
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struct ice_vf *vf;
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int num_alloc_vfs; /* actual number of VFs allocated */
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u16 num_vfs_supported; /* num VFs supported for this PF */
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u16 num_vf_qps; /* num queue pairs per VF */
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u16 num_vf_msix; /* num vectors per VF */
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DECLARE_BITMAP(state, __ICE_STATE_NBITS);
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DECLARE_BITMAP(avail_txqs, ICE_MAX_TXQS);
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DECLARE_BITMAP(avail_rxqs, ICE_MAX_RXQS);
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DECLARE_BITMAP(flags, ICE_PF_FLAGS_NBITS);
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unsigned long serv_tmr_period;
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unsigned long serv_tmr_prev;
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struct timer_list serv_tmr;
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struct work_struct serv_task;
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struct mutex avail_q_mutex; /* protects access to avail_[rx|tx]qs */
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struct mutex sw_mutex; /* lock for protecting VSI alloc flow */
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u32 msg_enable;
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u32 hw_csum_rx_error;
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u32 sw_oicr_idx; /* Other interrupt cause SW vector index */
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u32 num_avail_sw_msix; /* remaining MSIX SW vectors left unclaimed */
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u32 hw_oicr_idx; /* Other interrupt cause vector HW index */
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u32 num_avail_hw_msix; /* remaining HW MSIX vectors left unclaimed */
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u32 num_lan_msix; /* Total MSIX vectors for base driver */
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u16 num_lan_tx; /* num LAN Tx queues setup */
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u16 num_lan_rx; /* num LAN Rx queues setup */
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u16 q_left_tx; /* remaining num Tx queues left unclaimed */
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u16 q_left_rx; /* remaining num Rx queues left unclaimed */
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u16 next_vsi; /* Next free slot in pf->vsi[] - 0-based! */
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u16 num_alloc_vsi;
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u16 corer_count; /* Core reset count */
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u16 globr_count; /* Global reset count */
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u16 empr_count; /* EMP reset count */
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u16 pfr_count; /* PF reset count */
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struct ice_hw_port_stats stats;
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struct ice_hw_port_stats stats_prev;
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struct ice_hw hw;
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u8 stat_prev_loaded; /* has previous stats been loaded */
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#ifdef CONFIG_DCB
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u16 dcbx_cap;
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#endif /* CONFIG_DCB */
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u32 tx_timeout_count;
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unsigned long tx_timeout_last_recovery;
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u32 tx_timeout_recovery_level;
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char int_name[ICE_INT_NAME_STR_LEN];
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};
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struct ice_netdev_priv {
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struct ice_vsi *vsi;
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};
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/**
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* ice_irq_dynamic_ena - Enable default interrupt generation settings
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* @hw: pointer to HW struct
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* @vsi: pointer to VSI struct, can be NULL
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* @q_vector: pointer to q_vector, can be NULL
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*/
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static inline void
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ice_irq_dynamic_ena(struct ice_hw *hw, struct ice_vsi *vsi,
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struct ice_q_vector *q_vector)
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{
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u32 vector = (vsi && q_vector) ? vsi->hw_base_vector + q_vector->v_idx :
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((struct ice_pf *)hw->back)->hw_oicr_idx;
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int itr = ICE_ITR_NONE;
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u32 val;
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/* clear the PBA here, as this function is meant to clean out all
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* previous interrupts and enable the interrupt
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*/
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val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
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(itr << GLINT_DYN_CTL_ITR_INDX_S);
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if (vsi)
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if (test_bit(__ICE_DOWN, vsi->state))
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return;
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wr32(hw, GLINT_DYN_CTL(vector), val);
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}
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void ice_set_ethtool_ops(struct net_device *netdev);
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int ice_up(struct ice_vsi *vsi);
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int ice_down(struct ice_vsi *vsi);
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int ice_set_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
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int ice_get_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
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void ice_fill_rss_lut(u8 *lut, u16 rss_table_size, u16 rss_size);
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void ice_print_link_msg(struct ice_vsi *vsi, bool isup);
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void ice_napi_del(struct ice_vsi *vsi);
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#ifdef CONFIG_DCB
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int ice_pf_ena_all_vsi(struct ice_pf *pf, bool locked);
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void ice_pf_dis_all_vsi(struct ice_pf *pf, bool locked);
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#endif /* CONFIG_DCB */
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#endif /* _ICE_H_ */
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