mirror of https://gitee.com/openkylin/linux.git
49 lines
1.5 KiB
Plaintext
49 lines
1.5 KiB
Plaintext
* Samsung Exynos Power Domains
|
|
|
|
Exynos processors include support for multiple power domains which are used
|
|
to gate power to one or more peripherals on the processor.
|
|
|
|
Required Properties:
|
|
- compatible: should be one of the following.
|
|
* samsung,exynos4210-pd - for exynos4210 type power domain.
|
|
- reg: physical base address of the controller and length of memory mapped
|
|
region.
|
|
|
|
Optional Properties:
|
|
- clocks: List of clock handles. The parent clocks of the input clocks to the
|
|
devices in this power domain are set to oscclk before power gating
|
|
and restored back after powering on a domain. This is required for
|
|
all domains which are powered on and off and not required for unused
|
|
domains.
|
|
- clock-names: The following clocks can be specified:
|
|
- oscclk: Oscillator clock.
|
|
- pclkN, clkN: Pairs of parent of input clock and input clock to the
|
|
devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
|
|
are supported currently.
|
|
|
|
Node of a device using power domains must have a samsung,power-domain property
|
|
defined with a phandle to respective power domain.
|
|
|
|
Example:
|
|
|
|
lcd0: power-domain-lcd0 {
|
|
compatible = "samsung,exynos4210-pd";
|
|
reg = <0x10023C00 0x10>;
|
|
};
|
|
|
|
mfc_pd: power-domain@10044060 {
|
|
compatible = "samsung,exynos4210-pd";
|
|
reg = <0x10044060 0x20>;
|
|
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
|
|
<&clock CLK_MOUT_USER_ACLK333>;
|
|
clock-names = "oscclk", "pclk0", "clk0";
|
|
};
|
|
|
|
Example of the node using power domain:
|
|
|
|
node {
|
|
/* ... */
|
|
samsung,power-domain = <&lcd0>;
|
|
/* ... */
|
|
};
|