mirror of https://gitee.com/openkylin/linux.git
676 lines
20 KiB
C
676 lines
20 KiB
C
/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Vineetg: March 2009 (Supporting 2 levels of Interrupts)
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* Stack switching code can no longer reliably rely on the fact that
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* if we are NOT in user mode, stack is switched to kernel mode.
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* e.g. L2 IRQ interrupted a L1 ISR which had not yet completed
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* it's prologue including stack switching from user mode
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*
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* Vineetg: Aug 28th 2008: Bug #94984
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* -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
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* Normally CPU does this automatically, however when doing FAKE rtie,
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* we also need to explicitly do this. The problem in macros
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* FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit
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* was being "CLEARED" rather then "SET". Actually "SET" clears ZOL context
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*
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* Vineetg: May 5th 2008
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* -Modified CALLEE_REG save/restore macros to handle the fact that
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* r25 contains the kernel current task ptr
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* - Defined Stack Switching Macro to be reused in all intr/excp hdlrs
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* - Shaved off 11 instructions from RESTORE_ALL_INT1 by using the
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* address Write back load ld.ab instead of seperate ld/add instn
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*
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* Amit Bhor, Sameer Dhavale: Codito Technologies 2004
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*/
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#ifndef __ASM_ARC_ENTRY_H
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#define __ASM_ARC_ENTRY_H
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#ifdef __ASSEMBLY__
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#include <asm/unistd.h> /* For NR_syscalls defination */
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#include <asm/asm-offsets.h>
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#include <asm/arcregs.h>
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#include <asm/ptrace.h>
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#include <asm/processor.h> /* For VMALLOC_START */
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#include <asm/thread_info.h> /* For THREAD_SIZE */
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/* Note on the LD/ST addr modes with addr reg wback
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*
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* LD.a same as LD.aw
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*
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* LD.a reg1, [reg2, x] => Pre Incr
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* Eff Addr for load = [reg2 + x]
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*
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* LD.ab reg1, [reg2, x] => Post Incr
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* Eff Addr for load = [reg2]
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*/
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/*--------------------------------------------------------------
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* Save caller saved registers (scratch registers) ( r0 - r12 )
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* Registers are pushed / popped in the order defined in struct ptregs
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* in asm/ptrace.h
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*-------------------------------------------------------------*/
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.macro SAVE_CALLER_SAVED
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st.a r0, [sp, -4]
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st.a r1, [sp, -4]
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st.a r2, [sp, -4]
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st.a r3, [sp, -4]
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st.a r4, [sp, -4]
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st.a r5, [sp, -4]
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st.a r6, [sp, -4]
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st.a r7, [sp, -4]
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st.a r8, [sp, -4]
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st.a r9, [sp, -4]
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st.a r10, [sp, -4]
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st.a r11, [sp, -4]
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st.a r12, [sp, -4]
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.endm
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/*--------------------------------------------------------------
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* Restore caller saved registers (scratch registers)
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*-------------------------------------------------------------*/
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.macro RESTORE_CALLER_SAVED
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ld.ab r12, [sp, 4]
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ld.ab r11, [sp, 4]
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ld.ab r10, [sp, 4]
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ld.ab r9, [sp, 4]
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ld.ab r8, [sp, 4]
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ld.ab r7, [sp, 4]
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ld.ab r6, [sp, 4]
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ld.ab r5, [sp, 4]
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ld.ab r4, [sp, 4]
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ld.ab r3, [sp, 4]
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ld.ab r2, [sp, 4]
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ld.ab r1, [sp, 4]
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ld.ab r0, [sp, 4]
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.endm
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/*--------------------------------------------------------------
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* Save callee saved registers (non scratch registers) ( r13 - r25 )
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* on kernel stack.
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* User mode callee regs need to be saved in case of
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* -fork and friends for replicating from parent to child
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* -before going into do_signal( ) for ptrace/core-dump
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* Special case handling is required for r25 in case it is used by kernel
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* for caching task ptr. Low level exception/ISR save user mode r25
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* into task->thread.user_r25. So it needs to be retrieved from there and
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* saved into kernel stack with rest of callee reg-file
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*-------------------------------------------------------------*/
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.macro SAVE_CALLEE_SAVED_USER
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st.a r13, [sp, -4]
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st.a r14, [sp, -4]
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st.a r15, [sp, -4]
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st.a r16, [sp, -4]
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st.a r17, [sp, -4]
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st.a r18, [sp, -4]
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st.a r19, [sp, -4]
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st.a r20, [sp, -4]
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st.a r21, [sp, -4]
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st.a r22, [sp, -4]
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st.a r23, [sp, -4]
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st.a r24, [sp, -4]
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#ifdef CONFIG_ARC_CURR_IN_REG
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; Retrieve orig r25 and save it on stack
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ld r12, [r25, TASK_THREAD + THREAD_USER_R25]
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st.a r12, [sp, -4]
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#else
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st.a r25, [sp, -4]
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#endif
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/* move up by 1 word to "create" callee_regs->"stack_place_holder" */
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sub sp, sp, 4
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.endm
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/*--------------------------------------------------------------
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* Save callee saved registers (non scratch registers) ( r13 - r25 )
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* kernel mode callee regs needed to be saved in case of context switch
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* If r25 is used for caching task pointer then that need not be saved
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* as it can be re-created from current task global
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*-------------------------------------------------------------*/
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.macro SAVE_CALLEE_SAVED_KERNEL
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st.a r13, [sp, -4]
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st.a r14, [sp, -4]
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st.a r15, [sp, -4]
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st.a r16, [sp, -4]
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st.a r17, [sp, -4]
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st.a r18, [sp, -4]
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st.a r19, [sp, -4]
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st.a r20, [sp, -4]
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st.a r21, [sp, -4]
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st.a r22, [sp, -4]
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st.a r23, [sp, -4]
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st.a r24, [sp, -4]
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#ifdef CONFIG_ARC_CURR_IN_REG
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sub sp, sp, 8
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#else
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st.a r25, [sp, -4]
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sub sp, sp, 4
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#endif
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.endm
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/*--------------------------------------------------------------
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* RESTORE_CALLEE_SAVED_KERNEL:
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* Loads callee (non scratch) Reg File by popping from Kernel mode stack.
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* This is reverse of SAVE_CALLEE_SAVED,
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*
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* NOTE:
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* Ideally this shd only be called in switch_to for loading
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* switched-IN task's CALLEE Reg File.
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* For all other cases RESTORE_CALLEE_SAVED_FAST must be used
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* which simply pops the stack w/o touching regs.
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*-------------------------------------------------------------*/
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.macro RESTORE_CALLEE_SAVED_KERNEL
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#ifdef CONFIG_ARC_CURR_IN_REG
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add sp, sp, 8 /* skip callee_reg gutter and user r25 placeholder */
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#else
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add sp, sp, 4 /* skip "callee_regs->stack_place_holder" */
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ld.ab r25, [sp, 4]
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#endif
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ld.ab r24, [sp, 4]
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ld.ab r23, [sp, 4]
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ld.ab r22, [sp, 4]
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ld.ab r21, [sp, 4]
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ld.ab r20, [sp, 4]
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ld.ab r19, [sp, 4]
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ld.ab r18, [sp, 4]
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ld.ab r17, [sp, 4]
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ld.ab r16, [sp, 4]
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ld.ab r15, [sp, 4]
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ld.ab r14, [sp, 4]
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ld.ab r13, [sp, 4]
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.endm
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/*--------------------------------------------------------------
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* RESTORE_CALLEE_SAVED_USER:
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* This is called after do_signal where tracer might have changed callee regs
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* thus we need to restore the reg file.
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* Special case handling is required for r25 in case it is used by kernel
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* for caching task ptr. Ptrace would have modified on-kernel-stack value of
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* r25, which needs to be shoved back into task->thread.user_r25 where from
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* Low level exception/ISR return code will retrieve to populate with rest of
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* callee reg-file.
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*-------------------------------------------------------------*/
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.macro RESTORE_CALLEE_SAVED_USER
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add sp, sp, 4 /* skip "callee_regs->stack_place_holder" */
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#ifdef CONFIG_ARC_CURR_IN_REG
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ld.ab r12, [sp, 4]
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st r12, [r25, TASK_THREAD + THREAD_USER_R25]
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#else
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ld.ab r25, [sp, 4]
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#endif
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ld.ab r24, [sp, 4]
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ld.ab r23, [sp, 4]
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ld.ab r22, [sp, 4]
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ld.ab r21, [sp, 4]
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ld.ab r20, [sp, 4]
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ld.ab r19, [sp, 4]
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ld.ab r18, [sp, 4]
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ld.ab r17, [sp, 4]
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ld.ab r16, [sp, 4]
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ld.ab r15, [sp, 4]
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ld.ab r14, [sp, 4]
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ld.ab r13, [sp, 4]
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.endm
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/*--------------------------------------------------------------
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* Super FAST Restore callee saved regs by simply re-adjusting SP
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*-------------------------------------------------------------*/
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.macro DISCARD_CALLEE_SAVED_USER
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add sp, sp, 14 * 4
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.endm
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/*--------------------------------------------------------------
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* Restore User mode r25 saved in task_struct->thread.user_r25
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*-------------------------------------------------------------*/
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.macro RESTORE_USER_R25
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ld r25, [r25, TASK_THREAD + THREAD_USER_R25]
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.endm
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/*-------------------------------------------------------------
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* given a tsk struct, get to the base of it's kernel mode stack
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* tsk->thread_info is really a PAGE, whose bottom hoists stack
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* which grows upwards towards thread_info
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*------------------------------------------------------------*/
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.macro GET_TSK_STACK_BASE tsk, out
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/* Get task->thread_info (this is essentially start of a PAGE) */
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ld \out, [\tsk, TASK_THREAD_INFO]
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/* Go to end of page where stack begins (grows upwards) */
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add2 \out, \out, (THREAD_SIZE - 4)/4 /* one word GUTTER */
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.endm
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/*--------------------------------------------------------------
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* Switch to Kernel Mode stack if SP points to User Mode stack
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*
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* Entry : r9 contains pre-IRQ/exception/trap status32
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* Exit : SP is set to kernel mode stack pointer
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* If CURR_IN_REG, r25 set to "current" task pointer
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* Clobbers: r9
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*-------------------------------------------------------------*/
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.macro SWITCH_TO_KERNEL_STK
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/* User Mode when this happened ? Yes: Proceed to switch stack */
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bbit1 r9, STATUS_U_BIT, 88f
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/* OK we were already in kernel mode when this event happened, thus can
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* assume SP is kernel mode SP. _NO_ need to do any stack switching
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*/
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#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
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/* However....
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* If Level 2 Interrupts enabled, we may end up with a corner case:
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* 1. User Task executing
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* 2. L1 IRQ taken, ISR starts (CPU auto-switched to KERNEL mode)
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* 3. But before it could switch SP from USER to KERNEL stack
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* a L2 IRQ "Interrupts" L1
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* Thay way although L2 IRQ happened in Kernel mode, stack is still
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* not switched.
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* To handle this, we may need to switch stack even if in kernel mode
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* provided SP has values in range of USER mode stack ( < 0x7000_0000 )
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*/
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brlo sp, VMALLOC_START, 88f
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/* TODO: vineetg:
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* We need to be a bit more cautious here. What if a kernel bug in
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* L1 ISR, caused SP to go whaco (some small value which looks like
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* USER stk) and then we take L2 ISR.
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* Above brlo alone would treat it as a valid L1-L2 sceanrio
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* instead of shouting alound
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* The only feasible way is to make sure this L2 happened in
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* L1 prelogue ONLY i.e. ilink2 is less than a pre-set marker in
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* L1 ISR before it switches stack
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*/
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#endif
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/* Save Pre Intr/Exception KERNEL MODE SP on kernel stack
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* safe-keeping not really needed, but it keeps the epilogue code
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* (SP restore) simpler/uniform.
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*/
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b.d 77f
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st.a sp, [sp, -12] ; Make room for orig_r0 and orig_r8
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88: /*------Intr/Ecxp happened in user mode, "switch" stack ------ */
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GET_CURR_TASK_ON_CPU r9
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#ifdef CONFIG_ARC_CURR_IN_REG
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/* If current task pointer cached in r25, time to
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* -safekeep USER r25 in task->thread_struct->user_r25
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* -load r25 with current task ptr
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*/
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st.as r25, [r9, (TASK_THREAD + THREAD_USER_R25)/4]
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mov r25, r9
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#endif
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/* With current tsk in r9, get it's kernel mode stack base */
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GET_TSK_STACK_BASE r9, r9
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#ifdef PT_REGS_CANARY
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st 0xabcdabcd, [r9, 0]
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#endif
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/* Save Pre Intr/Exception User SP on kernel stack */
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st.a sp, [r9, -12] ; Make room for orig_r0 and orig_r8
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/* CAUTION:
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* SP should be set at the very end when we are done with everything
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* In case of 2 levels of interrupt we depend on value of SP to assume
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* that everything else is done (loading r25 etc)
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*/
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/* set SP to point to kernel mode stack */
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mov sp, r9
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77: /* ----- Stack Switched to kernel Mode, Now save REG FILE ----- */
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.endm
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/*------------------------------------------------------------
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* "FAKE" a rtie to return from CPU Exception context
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* This is to re-enable Exceptions within exception
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* Look at EV_ProtV to see how this is actually used
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*-------------------------------------------------------------*/
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.macro FAKE_RET_FROM_EXCPN reg
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ld \reg, [sp, PT_status32]
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bic \reg, \reg, (STATUS_U_MASK|STATUS_DE_MASK)
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bset \reg, \reg, STATUS_L_BIT
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sr \reg, [erstatus]
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mov \reg, 55f
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sr \reg, [eret]
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rtie
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55:
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.endm
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/*
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* @reg [OUT] &thread_info of "current"
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*/
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.macro GET_CURR_THR_INFO_FROM_SP reg
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and \reg, sp, ~(THREAD_SIZE - 1)
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.endm
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/*
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* @reg [OUT] thread_info->flags of "current"
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*/
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.macro GET_CURR_THR_INFO_FLAGS reg
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GET_CURR_THR_INFO_FROM_SP \reg
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ld \reg, [\reg, THREAD_INFO_FLAGS]
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.endm
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/*--------------------------------------------------------------
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* For early Exception Prologue, a core reg is temporarily needed to
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* code the rest of prolog (stack switching). This is done by stashing
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* it to memory (non-SMP case) or SCRATCH0 Aux Reg (SMP).
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*
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* Before saving the full regfile - this reg is restored back, only
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* to be saved again on kernel mode stack, as part of ptregs.
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*-------------------------------------------------------------*/
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.macro EXCPN_PROLOG_FREEUP_REG reg
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st \reg, [@ex_saved_reg1]
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.endm
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.macro EXCPN_PROLOG_RESTORE_REG reg
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ld \reg, [@ex_saved_reg1]
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.endm
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/*--------------------------------------------------------------
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* Save all registers used by Exceptions (TLB Miss, Prot-V, Mem err etc)
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* Requires SP to be already switched to kernel mode Stack
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* sp points to the next free element on the stack at exit of this macro.
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* Registers are pushed / popped in the order defined in struct ptregs
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* in asm/ptrace.h
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* Note that syscalls are implemented via TRAP which is also a exception
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* from CPU's point of view
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*-------------------------------------------------------------*/
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.macro SAVE_ALL_EXCEPTION marker
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st \marker, [sp, 8]
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st r0, [sp, 4] /* orig_r0, needed only for sys calls */
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/* Restore r9 used to code the early prologue */
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EXCPN_PROLOG_RESTORE_REG r9
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SAVE_CALLER_SAVED
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st.a r26, [sp, -4] /* gp */
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st.a fp, [sp, -4]
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st.a blink, [sp, -4]
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lr r9, [eret]
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st.a r9, [sp, -4]
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lr r9, [erstatus]
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st.a r9, [sp, -4]
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st.a lp_count, [sp, -4]
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lr r9, [lp_end]
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st.a r9, [sp, -4]
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lr r9, [lp_start]
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st.a r9, [sp, -4]
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lr r9, [erbta]
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st.a r9, [sp, -4]
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#ifdef PT_REGS_CANARY
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mov r9, 0xdeadbeef
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st r9, [sp, -4]
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#endif
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/* move up by 1 word to "create" pt_regs->"stack_place_holder" */
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sub sp, sp, 4
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.endm
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/*--------------------------------------------------------------
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* Save scratch regs for exceptions
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*-------------------------------------------------------------*/
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.macro SAVE_ALL_SYS
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SAVE_ALL_EXCEPTION orig_r8_IS_EXCPN
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.endm
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/*--------------------------------------------------------------
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* Save scratch regs for sys calls
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*-------------------------------------------------------------*/
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.macro SAVE_ALL_TRAP
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/*
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* Setup pt_regs->orig_r8.
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* Encode syscall number (r8) in upper short word of event type (r9)
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* N.B. #1: This is already endian safe (see ptrace.h)
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* #2: Only r9 can be used as scratch as it is already clobbered
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* and it's contents are no longer needed by the latter part
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* of exception prologue
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*/
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lsl r9, r8, 16
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or r9, r9, orig_r8_IS_SCALL
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SAVE_ALL_EXCEPTION r9
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.endm
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/*--------------------------------------------------------------
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* Restore all registers used by system call or Exceptions
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* SP should always be pointing to the next free stack element
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* when entering this macro.
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*
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* NOTE:
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*
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* It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
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* for memory load operations. If used in that way interrupts are deffered
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* by hardware and that is not good.
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*-------------------------------------------------------------*/
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.macro RESTORE_ALL_SYS
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add sp, sp, 4 /* hop over unused "pt_regs->stack_place_holder" */
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ld.ab r9, [sp, 4]
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sr r9, [erbta]
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ld.ab r9, [sp, 4]
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sr r9, [lp_start]
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ld.ab r9, [sp, 4]
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sr r9, [lp_end]
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ld.ab r9, [sp, 4]
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mov lp_count, r9
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ld.ab r9, [sp, 4]
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sr r9, [erstatus]
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ld.ab r9, [sp, 4]
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sr r9, [eret]
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ld.ab blink, [sp, 4]
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ld.ab fp, [sp, 4]
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ld.ab r26, [sp, 4] /* gp */
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RESTORE_CALLER_SAVED
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ld sp, [sp] /* restore original sp */
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/* orig_r0 and orig_r8 skipped automatically */
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.endm
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/*--------------------------------------------------------------
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* Save all registers used by interrupt handlers.
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*-------------------------------------------------------------*/
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.macro SAVE_ALL_INT1
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/* restore original r9 , saved in int1_saved_reg
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* It will be saved on stack in macro: SAVE_CALLER_SAVED
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*/
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ld r9, [@int1_saved_reg]
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/* now we are ready to save the remaining context :) */
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st orig_r8_IS_IRQ1, [sp, 8] /* Event Type */
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st 0, [sp, 4] /* orig_r0 , N/A for IRQ */
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SAVE_CALLER_SAVED
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st.a r26, [sp, -4] /* gp */
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st.a fp, [sp, -4]
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st.a blink, [sp, -4]
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st.a ilink1, [sp, -4]
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lr r9, [status32_l1]
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st.a r9, [sp, -4]
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st.a lp_count, [sp, -4]
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lr r9, [lp_end]
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st.a r9, [sp, -4]
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lr r9, [lp_start]
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st.a r9, [sp, -4]
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lr r9, [bta_l1]
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st.a r9, [sp, -4]
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#ifdef PT_REGS_CANARY
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mov r9, 0xdeadbee1
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st r9, [sp, -4]
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#endif
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/* move up by 1 word to "create" pt_regs->"stack_place_holder" */
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sub sp, sp, 4
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.endm
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.macro SAVE_ALL_INT2
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/* TODO-vineetg: SMP we can't use global nor can we use
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* SCRATCH0 as we do for int1 because while int1 is using
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* it, int2 can come
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*/
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/* retsore original r9 , saved in sys_saved_r9 */
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ld r9, [@int2_saved_reg]
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/* now we are ready to save the remaining context :) */
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st orig_r8_IS_IRQ2, [sp, 8] /* Event Type */
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st 0, [sp, 4] /* orig_r0 , N/A for IRQ */
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SAVE_CALLER_SAVED
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st.a r26, [sp, -4] /* gp */
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st.a fp, [sp, -4]
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st.a blink, [sp, -4]
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st.a ilink2, [sp, -4]
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lr r9, [status32_l2]
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st.a r9, [sp, -4]
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st.a lp_count, [sp, -4]
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lr r9, [lp_end]
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st.a r9, [sp, -4]
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lr r9, [lp_start]
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st.a r9, [sp, -4]
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lr r9, [bta_l2]
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st.a r9, [sp, -4]
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#ifdef PT_REGS_CANARY
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mov r9, 0xdeadbee2
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st r9, [sp, -4]
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#endif
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/* move up by 1 word to "create" pt_regs->"stack_place_holder" */
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sub sp, sp, 4
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.endm
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/*--------------------------------------------------------------
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* Restore all registers used by interrupt handlers.
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*
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* NOTE:
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*
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* It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
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* for memory load operations. If used in that way interrupts are deffered
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* by hardware and that is not good.
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*-------------------------------------------------------------*/
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.macro RESTORE_ALL_INT1
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add sp, sp, 4 /* hop over unused "pt_regs->stack_place_holder" */
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ld.ab r9, [sp, 4] /* Actual reg file */
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sr r9, [bta_l1]
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ld.ab r9, [sp, 4]
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sr r9, [lp_start]
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ld.ab r9, [sp, 4]
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sr r9, [lp_end]
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ld.ab r9, [sp, 4]
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mov lp_count, r9
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ld.ab r9, [sp, 4]
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sr r9, [status32_l1]
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ld.ab r9, [sp, 4]
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mov ilink1, r9
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ld.ab blink, [sp, 4]
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ld.ab fp, [sp, 4]
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ld.ab r26, [sp, 4] /* gp */
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RESTORE_CALLER_SAVED
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ld sp, [sp] /* restore original sp */
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/* orig_r0 and orig_r8 skipped automatically */
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.endm
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.macro RESTORE_ALL_INT2
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add sp, sp, 4 /* hop over unused "pt_regs->stack_place_holder" */
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ld.ab r9, [sp, 4]
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sr r9, [bta_l2]
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ld.ab r9, [sp, 4]
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sr r9, [lp_start]
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ld.ab r9, [sp, 4]
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sr r9, [lp_end]
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ld.ab r9, [sp, 4]
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mov lp_count, r9
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ld.ab r9, [sp, 4]
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sr r9, [status32_l2]
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ld.ab r9, [sp, 4]
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mov ilink2, r9
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ld.ab blink, [sp, 4]
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ld.ab fp, [sp, 4]
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ld.ab r26, [sp, 4] /* gp */
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RESTORE_CALLER_SAVED
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ld sp, [sp] /* restore original sp */
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/* orig_r0 and orig_r8 skipped automatically */
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.endm
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/* Get CPU-ID of this core */
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.macro GET_CPU_ID reg
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lr \reg, [identity]
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lsr \reg, \reg, 8
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bmsk \reg, \reg, 7
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.endm
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.macro GET_CURR_TASK_ON_CPU reg
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ld \reg, [@_current_task]
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.endm
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.macro SET_CURR_TASK_ON_CPU tsk, tmp
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st \tsk, [@_current_task]
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#ifdef CONFIG_ARC_CURR_IN_REG
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mov r25, \tsk
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#endif
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.endm
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/* ------------------------------------------------------------------
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* Get the ptr to some field of Current Task at @off in task struct
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* -Uses r25 for Current task ptr if that is enabled
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*/
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#ifdef CONFIG_ARC_CURR_IN_REG
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.macro GET_CURR_TASK_FIELD_PTR off, reg
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add \reg, r25, \off
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.endm
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#else
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.macro GET_CURR_TASK_FIELD_PTR off, reg
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GET_CURR_TASK_ON_CPU \reg
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add \reg, \reg, \off
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.endm
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#endif /* CONFIG_ARC_CURR_IN_REG */
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ARC_ENTRY_H */
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