mirror of https://gitee.com/openkylin/linux.git
423 lines
10 KiB
C
423 lines
10 KiB
C
/*
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* Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
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*
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* Copyright (c) 2003 Intracom S.A.
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* by Pantelis Antoniou <panto@intracom.gr>
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*
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* Heavily based on original FEC driver by Dan Malek <dan@embeddededge.com>
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* and modifications by Joakim Tjernlund <joakim.tjernlund@lumentis.se>
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*
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* Released under the GPL
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/string.h>
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#include <linux/ptrace.h>
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#include <linux/errno.h>
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#include <linux/ioport.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/spinlock.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/bitops.h>
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#include <asm/8xx_immap.h>
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#include <asm/pgtable.h>
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#include <asm/mpc8xx.h>
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#include <asm/irq.h>
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#include <asm/uaccess.h>
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#include <asm/commproc.h>
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/*************************************************/
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#include "fec_8xx.h"
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/*************************************************/
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/* Make MII read/write commands for the FEC.
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*/
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#define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
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#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
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#define mk_mii_end 0
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/*************************************************/
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/* XXX both FECs use the MII interface of FEC1 */
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static DEFINE_SPINLOCK(fec_mii_lock);
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#define FEC_MII_LOOPS 10000
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int fec_mii_read(struct net_device *dev, int phy_id, int location)
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{
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struct fec_enet_private *fep = netdev_priv(dev);
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fec_t *fecp;
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int i, ret = -1;
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unsigned long flags;
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/* XXX MII interface is only connected to FEC1 */
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fecp = &((immap_t *) IMAP_ADDR)->im_cpm.cp_fec;
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spin_lock_irqsave(&fec_mii_lock, flags);
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if ((FR(fecp, r_cntrl) & FEC_RCNTRL_MII_MODE) == 0) {
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FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
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FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
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FW(fecp, ievent, FEC_ENET_MII);
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}
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/* Add PHY address to register command. */
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FW(fecp, mii_speed, fep->fec_phy_speed);
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FW(fecp, mii_data, (phy_id << 23) | mk_mii_read(location));
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for (i = 0; i < FEC_MII_LOOPS; i++)
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if ((FR(fecp, ievent) & FEC_ENET_MII) != 0)
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break;
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if (i < FEC_MII_LOOPS) {
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FW(fecp, ievent, FEC_ENET_MII);
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ret = FR(fecp, mii_data) & 0xffff;
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}
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spin_unlock_irqrestore(&fec_mii_lock, flags);
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return ret;
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}
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void fec_mii_write(struct net_device *dev, int phy_id, int location, int value)
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{
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struct fec_enet_private *fep = netdev_priv(dev);
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fec_t *fecp;
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unsigned long flags;
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int i;
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/* XXX MII interface is only connected to FEC1 */
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fecp = &((immap_t *) IMAP_ADDR)->im_cpm.cp_fec;
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spin_lock_irqsave(&fec_mii_lock, flags);
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if ((FR(fecp, r_cntrl) & FEC_RCNTRL_MII_MODE) == 0) {
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FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
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FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
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FW(fecp, ievent, FEC_ENET_MII);
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}
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/* Add PHY address to register command. */
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FW(fecp, mii_speed, fep->fec_phy_speed); /* always adapt mii speed */
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FW(fecp, mii_data, (phy_id << 23) | mk_mii_write(location, value));
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for (i = 0; i < FEC_MII_LOOPS; i++)
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if ((FR(fecp, ievent) & FEC_ENET_MII) != 0)
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break;
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if (i < FEC_MII_LOOPS)
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FW(fecp, ievent, FEC_ENET_MII);
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spin_unlock_irqrestore(&fec_mii_lock, flags);
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}
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/*************************************************/
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#ifdef CONFIG_FEC_8XX_GENERIC_PHY
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/*
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* Generic PHY support.
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* Should work for all PHYs, but link change is detected by polling
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*/
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static void generic_timer_callback(unsigned long data)
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{
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struct net_device *dev = (struct net_device *)data;
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struct fec_enet_private *fep = netdev_priv(dev);
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fep->phy_timer_list.expires = jiffies + HZ / 2;
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add_timer(&fep->phy_timer_list);
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fec_mii_link_status_change_check(dev, 0);
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}
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static void generic_startup(struct net_device *dev)
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{
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struct fec_enet_private *fep = netdev_priv(dev);
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fep->phy_timer_list.expires = jiffies + HZ / 2; /* every 500ms */
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fep->phy_timer_list.data = (unsigned long)dev;
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fep->phy_timer_list.function = generic_timer_callback;
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add_timer(&fep->phy_timer_list);
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}
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static void generic_shutdown(struct net_device *dev)
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{
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struct fec_enet_private *fep = netdev_priv(dev);
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del_timer_sync(&fep->phy_timer_list);
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}
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#endif
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#ifdef CONFIG_FEC_8XX_DM9161_PHY
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/* ------------------------------------------------------------------------- */
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/* The Davicom DM9161 is used on the NETTA board */
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/* register definitions */
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#define MII_DM9161_ACR 16 /* Aux. Config Register */
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#define MII_DM9161_ACSR 17 /* Aux. Config/Status Register */
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#define MII_DM9161_10TCSR 18 /* 10BaseT Config/Status Reg. */
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#define MII_DM9161_INTR 21 /* Interrupt Register */
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#define MII_DM9161_RECR 22 /* Receive Error Counter Reg. */
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#define MII_DM9161_DISCR 23 /* Disconnect Counter Register */
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static void dm9161_startup(struct net_device *dev)
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{
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struct fec_enet_private *fep = netdev_priv(dev);
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fec_mii_write(dev, fep->mii_if.phy_id, MII_DM9161_INTR, 0x0000);
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}
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static void dm9161_ack_int(struct net_device *dev)
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{
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struct fec_enet_private *fep = netdev_priv(dev);
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fec_mii_read(dev, fep->mii_if.phy_id, MII_DM9161_INTR);
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}
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static void dm9161_shutdown(struct net_device *dev)
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{
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struct fec_enet_private *fep = netdev_priv(dev);
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fec_mii_write(dev, fep->mii_if.phy_id, MII_DM9161_INTR, 0x0f00);
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}
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#endif
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#ifdef CONFIG_FEC_8XX_LXT971_PHY
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/* Support for LXT971/972 PHY */
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#define MII_LXT971_PCR 16 /* Port Control Register */
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#define MII_LXT971_SR2 17 /* Status Register 2 */
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#define MII_LXT971_IER 18 /* Interrupt Enable Register */
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#define MII_LXT971_ISR 19 /* Interrupt Status Register */
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#define MII_LXT971_LCR 20 /* LED Control Register */
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#define MII_LXT971_TCR 30 /* Transmit Control Register */
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static void lxt971_startup(struct net_device *dev)
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{
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struct fec_enet_private *fep = netdev_priv(dev);
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fec_mii_write(dev, fep->mii_if.phy_id, MII_LXT971_IER, 0x00F2);
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}
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static void lxt971_ack_int(struct net_device *dev)
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{
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struct fec_enet_private *fep = netdev_priv(dev);
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fec_mii_read(dev, fep->mii_if.phy_id, MII_LXT971_ISR);
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}
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static void lxt971_shutdown(struct net_device *dev)
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{
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struct fec_enet_private *fep = netdev_priv(dev);
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fec_mii_write(dev, fep->mii_if.phy_id, MII_LXT971_IER, 0x0000);
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}
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#endif
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/**********************************************************************************/
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static const struct phy_info phy_info[] = {
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#ifdef CONFIG_FEC_8XX_DM9161_PHY
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{
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.id = 0x00181b88,
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.name = "DM9161",
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.startup = dm9161_startup,
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.ack_int = dm9161_ack_int,
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.shutdown = dm9161_shutdown,
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},
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#endif
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#ifdef CONFIG_FEC_8XX_LXT971_PHY
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{
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.id = 0x0001378e,
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.name = "LXT971/972",
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.startup = lxt971_startup,
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.ack_int = lxt971_ack_int,
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.shutdown = lxt971_shutdown,
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},
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#endif
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#ifdef CONFIG_FEC_8XX_GENERIC_PHY
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{
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.id = 0,
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.name = "GENERIC",
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.startup = generic_startup,
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.shutdown = generic_shutdown,
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},
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#endif
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};
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/**********************************************************************************/
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int fec_mii_phy_id_detect(struct net_device *dev)
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{
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struct fec_enet_private *fep = netdev_priv(dev);
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const struct fec_platform_info *fpi = fep->fpi;
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int i, r, start, end, phytype, physubtype;
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const struct phy_info *phy;
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int phy_hwid, phy_id;
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/* if no MDIO */
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if (fpi->use_mdio == 0)
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return -1;
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phy_hwid = -1;
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fep->phy = NULL;
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/* auto-detect? */
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if (fpi->phy_addr == -1) {
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start = 0;
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end = 32;
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} else { /* direct */
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start = fpi->phy_addr;
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end = start + 1;
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}
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for (phy_id = start; phy_id < end; phy_id++) {
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r = fec_mii_read(dev, phy_id, MII_PHYSID1);
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if (r == -1 || (phytype = (r & 0xffff)) == 0xffff)
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continue;
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r = fec_mii_read(dev, phy_id, MII_PHYSID2);
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if (r == -1 || (physubtype = (r & 0xffff)) == 0xffff)
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continue;
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phy_hwid = (phytype << 16) | physubtype;
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if (phy_hwid != -1)
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break;
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}
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if (phy_hwid == -1) {
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printk(KERN_ERR DRV_MODULE_NAME
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": %s No PHY detected!\n", dev->name);
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return -1;
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}
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for (i = 0, phy = phy_info; i < sizeof(phy_info) / sizeof(phy_info[0]);
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i++, phy++)
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if (phy->id == (phy_hwid >> 4) || phy->id == 0)
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break;
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if (i >= sizeof(phy_info) / sizeof(phy_info[0])) {
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printk(KERN_ERR DRV_MODULE_NAME
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": %s PHY id 0x%08x is not supported!\n",
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dev->name, phy_hwid);
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return -1;
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}
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fep->phy = phy;
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printk(KERN_INFO DRV_MODULE_NAME
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": %s Phy @ 0x%x, type %s (0x%08x)\n",
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dev->name, phy_id, fep->phy->name, phy_hwid);
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return phy_id;
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}
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void fec_mii_startup(struct net_device *dev)
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{
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struct fec_enet_private *fep = netdev_priv(dev);
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const struct fec_platform_info *fpi = fep->fpi;
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if (!fpi->use_mdio || fep->phy == NULL)
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return;
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if (fep->phy->startup == NULL)
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return;
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(*fep->phy->startup) (dev);
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}
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void fec_mii_shutdown(struct net_device *dev)
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{
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struct fec_enet_private *fep = netdev_priv(dev);
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const struct fec_platform_info *fpi = fep->fpi;
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if (!fpi->use_mdio || fep->phy == NULL)
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return;
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if (fep->phy->shutdown == NULL)
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return;
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(*fep->phy->shutdown) (dev);
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}
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void fec_mii_ack_int(struct net_device *dev)
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{
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struct fec_enet_private *fep = netdev_priv(dev);
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const struct fec_platform_info *fpi = fep->fpi;
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if (!fpi->use_mdio || fep->phy == NULL)
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return;
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if (fep->phy->ack_int == NULL)
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return;
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(*fep->phy->ack_int) (dev);
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}
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/* helper function */
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static int mii_negotiated(struct mii_if_info *mii)
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{
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int advert, lpa, val;
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if (!mii_link_ok(mii))
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return 0;
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val = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_BMSR);
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if ((val & BMSR_ANEGCOMPLETE) == 0)
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return 0;
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advert = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_ADVERTISE);
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lpa = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_LPA);
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return mii_nway_result(advert & lpa);
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}
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void fec_mii_link_status_change_check(struct net_device *dev, int init_media)
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{
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struct fec_enet_private *fep = netdev_priv(dev);
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unsigned int media;
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unsigned long flags;
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if (mii_check_media(&fep->mii_if, netif_msg_link(fep), init_media) == 0)
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return;
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media = mii_negotiated(&fep->mii_if);
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if (netif_carrier_ok(dev)) {
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spin_lock_irqsave(&fep->lock, flags);
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fec_restart(dev, !!(media & ADVERTISE_FULL),
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(media & (ADVERTISE_100FULL | ADVERTISE_100HALF)) ?
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100 : 10);
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spin_unlock_irqrestore(&fep->lock, flags);
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netif_start_queue(dev);
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} else {
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netif_stop_queue(dev);
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spin_lock_irqsave(&fep->lock, flags);
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fec_stop(dev);
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spin_unlock_irqrestore(&fep->lock, flags);
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}
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}
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