mirror of https://gitee.com/openkylin/linux.git
304 lines
7.3 KiB
C
304 lines
7.3 KiB
C
/*
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* MPC8560ADS board specific routines
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*
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* Maintainer: Kumar Gala <galak@kernel.crashing.org>
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*
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* Copyright 2004 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/major.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#include <linux/serial.h>
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#include <linux/tty.h> /* for linux/serial_core.h */
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#include <linux/serial_core.h>
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#include <linux/initrd.h>
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#include <linux/module.h>
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#include <linux/fsl_devices.h>
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#include <linux/fs_enet_pd.h>
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#include <asm/system.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/atomic.h>
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#include <asm/time.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/open_pic.h>
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#include <asm/bootinfo.h>
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#include <asm/pci-bridge.h>
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#include <asm/mpc85xx.h>
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#include <asm/irq.h>
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#include <asm/immap_85xx.h>
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#include <asm/kgdb.h>
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#include <asm/ppc_sys.h>
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#include <asm/cpm2.h>
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#include <mm/mmu_decl.h>
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#include <syslib/cpm2_pic.h>
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#include <syslib/ppc85xx_common.h>
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#include <syslib/ppc85xx_setup.h>
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/* ************************************************************************
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*
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* Setup the architecture
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*
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*/
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static void init_fcc_ioports(void)
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{
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struct immap *immap;
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struct io_port *io;
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u32 tempval;
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immap = cpm2_immr;
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io = &immap->im_ioport;
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/* FCC2/3 are on the ports B/C. */
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tempval = in_be32(&io->iop_pdirb);
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tempval &= ~PB2_DIRB0;
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tempval |= PB2_DIRB1;
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out_be32(&io->iop_pdirb, tempval);
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tempval = in_be32(&io->iop_psorb);
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tempval &= ~PB2_PSORB0;
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tempval |= PB2_PSORB1;
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out_be32(&io->iop_psorb, tempval);
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tempval = in_be32(&io->iop_pparb);
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tempval |= (PB2_DIRB0 | PB2_DIRB1);
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out_be32(&io->iop_pparb, tempval);
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tempval = in_be32(&io->iop_pdirb);
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tempval &= ~PB3_DIRB0;
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tempval |= PB3_DIRB1;
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out_be32(&io->iop_pdirb, tempval);
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tempval = in_be32(&io->iop_psorb);
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tempval &= ~PB3_PSORB0;
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tempval |= PB3_PSORB1;
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out_be32(&io->iop_psorb, tempval);
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tempval = in_be32(&io->iop_pparb);
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tempval |= (PB3_DIRB0 | PB3_DIRB1);
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out_be32(&io->iop_pparb, tempval);
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tempval = in_be32(&io->iop_pdirc);
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tempval |= PC3_DIRC1;
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out_be32(&io->iop_pdirc, tempval);
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tempval = in_be32(&io->iop_pparc);
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tempval |= PC3_DIRC1;
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out_be32(&io->iop_pparc, tempval);
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/* Port C has clocks...... */
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tempval = in_be32(&io->iop_psorc);
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tempval &= ~(CLK_TRX);
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out_be32(&io->iop_psorc, tempval);
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tempval = in_be32(&io->iop_pdirc);
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tempval &= ~(CLK_TRX);
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out_be32(&io->iop_pdirc, tempval);
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tempval = in_be32(&io->iop_pparc);
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tempval |= (CLK_TRX);
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out_be32(&io->iop_pparc, tempval);
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/* Configure Serial Interface clock routing.
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* First, clear all FCC bits to zero,
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* then set the ones we want.
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*/
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immap->im_cpmux.cmx_fcr &= ~(CPMUX_CLK_MASK);
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immap->im_cpmux.cmx_fcr |= CPMUX_CLK_ROUTE;
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}
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static void __init
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mpc8560ads_setup_arch(void)
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{
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bd_t *binfo = (bd_t *) __res;
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unsigned int freq;
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struct gianfar_platform_data *pdata;
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struct gianfar_mdio_data *mdata;
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struct fs_platform_info *fpi;
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cpm2_reset();
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/* get the core frequency */
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freq = binfo->bi_intfreq;
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if (ppc_md.progress)
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ppc_md.progress("mpc8560ads_setup_arch()", 0);
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/* Set loops_per_jiffy to a half-way reasonable value,
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for use until calibrate_delay gets called. */
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loops_per_jiffy = freq / HZ;
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#ifdef CONFIG_PCI
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/* setup PCI host bridges */
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mpc85xx_setup_hose();
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#endif
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/* setup the board related info for the MDIO bus */
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mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
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mdata->irq[0] = MPC85xx_IRQ_EXT5;
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mdata->irq[1] = MPC85xx_IRQ_EXT5;
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mdata->irq[2] = -1;
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mdata->irq[3] = MPC85xx_IRQ_EXT5;
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mdata->irq[31] = -1;
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/* setup the board related information for the enet controllers */
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pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
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if (pdata) {
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pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
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pdata->bus_id = 0;
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pdata->phy_id = 0;
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memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
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}
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pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
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if (pdata) {
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pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
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pdata->bus_id = 0;
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pdata->phy_id = 1;
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memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
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}
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init_fcc_ioports();
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ppc_sys_device_remove(MPC85xx_CPM_FCC1);
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fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC2);
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if (fpi) {
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memcpy(fpi->macaddr, binfo->bi_enet2addr, 6);
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fpi->bus_id = "0:02";
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fpi->phy_addr = 2;
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fpi->dpram_offset = (u32)cpm2_immr->im_dprambase;
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fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[1];
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}
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fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC3);
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if (fpi) {
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memcpy(fpi->macaddr, binfo->bi_enet2addr, 6);
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fpi->macaddr[5] += 1;
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fpi->bus_id = "0:03";
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fpi->phy_addr = 3;
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fpi->dpram_offset = (u32)cpm2_immr->im_dprambase;
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fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[2];
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}
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#ifdef CONFIG_BLK_DEV_INITRD
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if (initrd_start)
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ROOT_DEV = Root_RAM0;
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else
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#endif
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#ifdef CONFIG_ROOT_NFS
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ROOT_DEV = Root_NFS;
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#else
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ROOT_DEV = Root_HDA1;
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#endif
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}
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static irqreturn_t cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
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{
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while ((irq = cpm2_get_irq(regs)) >= 0)
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__do_IRQ(irq, regs);
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return IRQ_HANDLED;
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}
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static struct irqaction cpm2_irqaction = {
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.handler = cpm2_cascade,
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.flags = IRQF_DISABLED,
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.mask = CPU_MASK_NONE,
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.name = "cpm2_cascade",
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};
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static void __init
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mpc8560_ads_init_IRQ(void)
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{
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/* Setup OpenPIC */
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mpc85xx_ads_init_IRQ();
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/* Setup CPM2 PIC */
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cpm2_init_IRQ();
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setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
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return;
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}
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/* ************************************************************************ */
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void __init
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platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7)
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{
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/* parse_bootinfo must always be called first */
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parse_bootinfo(find_bootinfo());
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/*
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* If we were passed in a board information, copy it into the
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* residual data area.
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*/
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if (r3) {
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memcpy((void *) __res, (void *) (r3 + KERNELBASE),
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sizeof (bd_t));
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}
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#if defined(CONFIG_BLK_DEV_INITRD)
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/*
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* If the init RAM disk has been configured in, and there's a valid
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* starting address for it, set it up.
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*/
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if (r4) {
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initrd_start = r4 + KERNELBASE;
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initrd_end = r5 + KERNELBASE;
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}
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#endif /* CONFIG_BLK_DEV_INITRD */
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/* Copy the kernel command line arguments to a safe place. */
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if (r6) {
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*(char *) (r7 + KERNELBASE) = 0;
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strcpy(cmd_line, (char *) (r6 + KERNELBASE));
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}
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identify_ppc_sys_by_id(mfspr(SPRN_SVR));
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/* setup the PowerPC module struct */
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ppc_md.setup_arch = mpc8560ads_setup_arch;
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ppc_md.show_cpuinfo = mpc85xx_ads_show_cpuinfo;
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ppc_md.init_IRQ = mpc8560_ads_init_IRQ;
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ppc_md.get_irq = openpic_get_irq;
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ppc_md.restart = mpc85xx_restart;
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ppc_md.power_off = mpc85xx_power_off;
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ppc_md.halt = mpc85xx_halt;
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ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
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ppc_md.time_init = NULL;
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ppc_md.set_rtc_time = NULL;
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ppc_md.get_rtc_time = NULL;
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ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
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if (ppc_md.progress)
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ppc_md.progress("mpc8560ads_init(): exit", 0);
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return;
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}
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