mirror of https://gitee.com/openkylin/linux.git
490 lines
13 KiB
C
490 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018, Intel Corporation. */
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#ifndef _ICE_LAN_TX_RX_H_
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#define _ICE_LAN_TX_RX_H_
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union ice_32byte_rx_desc {
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struct {
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__le64 pkt_addr; /* Packet buffer address */
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__le64 hdr_addr; /* Header buffer address */
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/* bit 0 of hdr_addr is DD bit */
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__le64 rsvd1;
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__le64 rsvd2;
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} read;
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struct {
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struct {
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struct {
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__le16 mirroring_status;
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__le16 l2tag1;
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} lo_dword;
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union {
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__le32 rss; /* RSS Hash */
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__le32 fd_id; /* Flow Director filter id */
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} hi_dword;
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} qword0;
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struct {
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/* status/error/PTYPE/length */
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__le64 status_error_len;
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} qword1;
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struct {
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__le16 ext_status; /* extended status */
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__le16 rsvd;
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__le16 l2tag2_1;
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__le16 l2tag2_2;
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} qword2;
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struct {
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__le32 reserved;
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__le32 fd_id;
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} qword3;
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} wb; /* writeback */
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};
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struct ice_rx_ptype_decoded {
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u32 ptype:10;
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u32 known:1;
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u32 outer_ip:1;
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u32 outer_ip_ver:2;
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u32 outer_frag:1;
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u32 tunnel_type:3;
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u32 tunnel_end_prot:2;
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u32 tunnel_end_frag:1;
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u32 inner_prot:4;
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u32 payload_layer:3;
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};
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enum ice_rx_ptype_outer_ip {
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ICE_RX_PTYPE_OUTER_L2 = 0,
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ICE_RX_PTYPE_OUTER_IP = 1,
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};
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enum ice_rx_ptype_outer_ip_ver {
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ICE_RX_PTYPE_OUTER_NONE = 0,
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ICE_RX_PTYPE_OUTER_IPV4 = 1,
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ICE_RX_PTYPE_OUTER_IPV6 = 2,
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};
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enum ice_rx_ptype_outer_fragmented {
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ICE_RX_PTYPE_NOT_FRAG = 0,
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ICE_RX_PTYPE_FRAG = 1,
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};
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enum ice_rx_ptype_tunnel_type {
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ICE_RX_PTYPE_TUNNEL_NONE = 0,
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ICE_RX_PTYPE_TUNNEL_IP_IP = 1,
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ICE_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
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ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
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ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
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};
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enum ice_rx_ptype_tunnel_end_prot {
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ICE_RX_PTYPE_TUNNEL_END_NONE = 0,
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ICE_RX_PTYPE_TUNNEL_END_IPV4 = 1,
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ICE_RX_PTYPE_TUNNEL_END_IPV6 = 2,
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};
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enum ice_rx_ptype_inner_prot {
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ICE_RX_PTYPE_INNER_PROT_NONE = 0,
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ICE_RX_PTYPE_INNER_PROT_UDP = 1,
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ICE_RX_PTYPE_INNER_PROT_TCP = 2,
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ICE_RX_PTYPE_INNER_PROT_SCTP = 3,
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ICE_RX_PTYPE_INNER_PROT_ICMP = 4,
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ICE_RX_PTYPE_INNER_PROT_TIMESYNC = 5,
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};
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enum ice_rx_ptype_payload_layer {
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ICE_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
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ICE_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
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ICE_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
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ICE_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
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};
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/* RX Flex Descriptor
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* This descriptor is used instead of the legacy version descriptor when
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* ice_rlan_ctx.adv_desc is set
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*/
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union ice_32b_rx_flex_desc {
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struct {
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__le64 pkt_addr; /* Packet buffer address */
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__le64 hdr_addr; /* Header buffer address */
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/* bit 0 of hdr_addr is DD bit */
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__le64 rsvd1;
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__le64 rsvd2;
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} read;
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struct {
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/* Qword 0 */
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u8 rxdid; /* descriptor builder profile id */
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u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
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__le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
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__le16 pkt_len; /* [15:14] are reserved */
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__le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
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/* sph=[11:11] */
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/* ff1/ext=[15:12] */
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/* Qword 1 */
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__le16 status_error0;
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__le16 l2tag1;
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__le16 flex_meta0;
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__le16 flex_meta1;
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/* Qword 2 */
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__le16 status_error1;
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u8 flex_flags2;
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u8 time_stamp_low;
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__le16 l2tag2_1st;
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__le16 l2tag2_2nd;
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/* Qword 3 */
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__le16 flex_meta2;
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__le16 flex_meta3;
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union {
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struct {
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__le16 flex_meta4;
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__le16 flex_meta5;
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} flex;
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__le32 ts_high;
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} flex_ts;
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} wb; /* writeback */
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};
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/* Rx Flex Descriptor NIC Profile
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* This descriptor corresponds to RxDID 2 which contains
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* metadata fields for RSS, flow id and timestamp info
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*/
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struct ice_32b_rx_flex_desc_nic {
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/* Qword 0 */
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u8 rxdid;
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u8 mir_id_umb_cast;
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__le16 ptype_flexi_flags0;
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__le16 pkt_len;
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__le16 hdr_len_sph_flex_flags1;
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/* Qword 1 */
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__le16 status_error0;
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__le16 l2tag1;
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__le32 rss_hash;
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/* Qword 2 */
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__le16 status_error1;
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u8 flexi_flags2;
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u8 ts_low;
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__le16 l2tag2_1st;
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__le16 l2tag2_2nd;
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/* Qword 3 */
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__le32 flow_id;
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union {
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struct {
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__le16 vlan_id;
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__le16 flow_id_ipv6;
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} flex;
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__le32 ts_high;
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} flex_ts;
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};
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/* Receive Flex Descriptor profile IDs: There are a total
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* of 64 profiles where profile IDs 0/1 are for legacy; and
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* profiles 2-63 are flex profiles that can be programmed
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* with a specific metadata (profile 7 reserved for HW)
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*/
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enum ice_rxdid {
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ICE_RXDID_LEGACY_0 = 0,
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ICE_RXDID_LEGACY_1 = 1,
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ICE_RXDID_FLEX_NIC = 2,
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ICE_RXDID_FLEX_NIC_2 = 6,
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ICE_RXDID_HW = 7,
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ICE_RXDID_LAST = 63,
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};
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/* Receive Flex Descriptor Rx opcode values */
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#define ICE_RX_OPC_MDID 0x01
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/* Receive Descriptor MDID values */
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enum ice_flex_rx_mdid {
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ICE_RX_MDID_FLOW_ID_LOWER = 5,
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ICE_RX_MDID_FLOW_ID_HIGH,
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ICE_RX_MDID_SRC_VSI = 19,
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ICE_RX_MDID_HASH_LOW = 56,
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ICE_RX_MDID_HASH_HIGH,
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};
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/* Rx Flag64 packet flag bits */
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enum ice_rx_flg64_bits {
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ICE_RXFLG_PKT_DSI = 0,
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ICE_RXFLG_EVLAN_x8100 = 15,
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ICE_RXFLG_EVLAN_x9100,
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ICE_RXFLG_VLAN_x8100,
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ICE_RXFLG_TNL_MAC = 22,
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ICE_RXFLG_TNL_VLAN,
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ICE_RXFLG_PKT_FRG,
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ICE_RXFLG_FIN = 32,
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ICE_RXFLG_SYN,
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ICE_RXFLG_RST,
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ICE_RXFLG_TNL0 = 38,
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ICE_RXFLG_TNL1,
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ICE_RXFLG_TNL2,
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ICE_RXFLG_UDP_GRE,
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ICE_RXFLG_RSVD = 63
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};
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/* for ice_32byte_rx_flex_desc.ptype_flexi_flags0 member */
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#define ICE_RX_FLEX_DESC_PTYPE_M (0x3FF) /* 10-bits */
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/* for ice_32byte_rx_flex_desc.pkt_length member */
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#define ICE_RX_FLX_DESC_PKT_LEN_M (0x3FFF) /* 14-bits */
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enum ice_rx_flex_desc_status_error_0_bits {
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/* Note: These are predefined bit offsets */
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ICE_RX_FLEX_DESC_STATUS0_DD_S = 0,
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ICE_RX_FLEX_DESC_STATUS0_EOF_S,
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ICE_RX_FLEX_DESC_STATUS0_HBO_S,
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ICE_RX_FLEX_DESC_STATUS0_L3L4P_S,
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ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S,
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ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S,
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ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S,
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ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S,
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ICE_RX_FLEX_DESC_STATUS0_LPBK_S,
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ICE_RX_FLEX_DESC_STATUS0_IPV6EXADD_S,
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ICE_RX_FLEX_DESC_STATUS0_RXE_S,
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ICE_RX_FLEX_DESC_STATUS0_CRCP_S,
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ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S,
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ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S,
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ICE_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S,
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ICE_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S,
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ICE_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */
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};
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#define ICE_RXQ_CTX_SIZE_DWORDS 8
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#define ICE_RXQ_CTX_SZ (ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32))
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/* RLAN Rx queue context data
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*
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* The sizes of the variables may be larger than needed due to crossing byte
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* boundaries. If we do not have the width of the variable set to the correct
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* size then we could end up shifting bits off the top of the variable when the
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* variable is at the top of a byte and crosses over into the next byte.
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*/
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struct ice_rlan_ctx {
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u16 head;
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u16 cpuid; /* bigger than needed, see above for reason */
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#define ICE_RLAN_BASE_S 7
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u64 base;
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u16 qlen;
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#define ICE_RLAN_CTX_DBUF_S 7
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u16 dbuf; /* bigger than needed, see above for reason */
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#define ICE_RLAN_CTX_HBUF_S 6
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u16 hbuf; /* bigger than needed, see above for reason */
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u8 dtype;
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u8 dsize;
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u8 crcstrip;
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u8 l2tsel;
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u8 hsplit_0;
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u8 hsplit_1;
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u8 showiv;
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u32 rxmax; /* bigger than needed, see above for reason */
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u8 tphrdesc_ena;
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u8 tphwdesc_ena;
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u8 tphdata_ena;
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u8 tphhead_ena;
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u16 lrxqthresh; /* bigger than needed, see above for reason */
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};
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struct ice_ctx_ele {
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u16 offset;
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u16 size_of;
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u16 width;
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u16 lsb;
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};
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#define ICE_CTX_STORE(_struct, _ele, _width, _lsb) { \
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.offset = offsetof(struct _struct, _ele), \
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.size_of = FIELD_SIZEOF(struct _struct, _ele), \
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.width = _width, \
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.lsb = _lsb, \
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}
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/* for hsplit_0 field of Rx RLAN context */
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enum ice_rlan_ctx_rx_hsplit_0 {
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ICE_RLAN_RX_HSPLIT_0_NO_SPLIT = 0,
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ICE_RLAN_RX_HSPLIT_0_SPLIT_L2 = 1,
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ICE_RLAN_RX_HSPLIT_0_SPLIT_IP = 2,
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ICE_RLAN_RX_HSPLIT_0_SPLIT_TCP_UDP = 4,
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ICE_RLAN_RX_HSPLIT_0_SPLIT_SCTP = 8,
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};
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/* for hsplit_1 field of Rx RLAN context */
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enum ice_rlan_ctx_rx_hsplit_1 {
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ICE_RLAN_RX_HSPLIT_1_NO_SPLIT = 0,
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ICE_RLAN_RX_HSPLIT_1_SPLIT_L2 = 1,
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ICE_RLAN_RX_HSPLIT_1_SPLIT_ALWAYS = 2,
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};
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/* TX Descriptor */
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struct ice_tx_desc {
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__le64 buf_addr; /* Address of descriptor's data buf */
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__le64 cmd_type_offset_bsz;
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};
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enum ice_tx_desc_dtype_value {
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ICE_TX_DESC_DTYPE_DATA = 0x0,
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ICE_TX_DESC_DTYPE_CTX = 0x1,
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/* DESC_DONE - HW has completed write-back of descriptor */
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ICE_TX_DESC_DTYPE_DESC_DONE = 0xF,
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};
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#define ICE_TXD_QW1_CMD_S 4
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#define ICE_TXD_QW1_CMD_M (0xFFFUL << ICE_TXD_QW1_CMD_S)
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enum ice_tx_desc_cmd_bits {
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ICE_TX_DESC_CMD_EOP = 0x0001,
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ICE_TX_DESC_CMD_RS = 0x0002,
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ICE_TX_DESC_CMD_IL2TAG1 = 0x0008,
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ICE_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
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ICE_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
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ICE_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
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ICE_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
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ICE_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
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};
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#define ICE_TXD_QW1_OFFSET_S 16
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#define ICE_TXD_QW1_OFFSET_M (0x3FFFFULL << ICE_TXD_QW1_OFFSET_S)
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enum ice_tx_desc_len_fields {
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/* Note: These are predefined bit offsets */
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ICE_TX_DESC_LEN_MACLEN_S = 0, /* 7 BITS */
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ICE_TX_DESC_LEN_IPLEN_S = 7, /* 7 BITS */
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ICE_TX_DESC_LEN_L4_LEN_S = 14 /* 4 BITS */
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};
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#define ICE_TXD_QW1_MACLEN_M (0x7FUL << ICE_TX_DESC_LEN_MACLEN_S)
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#define ICE_TXD_QW1_IPLEN_M (0x7FUL << ICE_TX_DESC_LEN_IPLEN_S)
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#define ICE_TXD_QW1_L4LEN_M (0xFUL << ICE_TX_DESC_LEN_L4_LEN_S)
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/* Tx descriptor field limits in bytes */
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#define ICE_TXD_MACLEN_MAX ((ICE_TXD_QW1_MACLEN_M >> \
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ICE_TX_DESC_LEN_MACLEN_S) * ICE_BYTES_PER_WORD)
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#define ICE_TXD_IPLEN_MAX ((ICE_TXD_QW1_IPLEN_M >> \
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ICE_TX_DESC_LEN_IPLEN_S) * ICE_BYTES_PER_DWORD)
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#define ICE_TXD_L4LEN_MAX ((ICE_TXD_QW1_L4LEN_M >> \
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ICE_TX_DESC_LEN_L4_LEN_S) * ICE_BYTES_PER_DWORD)
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#define ICE_TXD_QW1_TX_BUF_SZ_S 34
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#define ICE_TXD_QW1_L2TAG1_S 48
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/* Context descriptors */
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struct ice_tx_ctx_desc {
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__le32 tunneling_params;
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__le16 l2tag2;
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__le16 rsvd;
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__le64 qw1;
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};
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#define ICE_TXD_CTX_QW1_CMD_S 4
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#define ICE_TXD_CTX_QW1_CMD_M (0x7FUL << ICE_TXD_CTX_QW1_CMD_S)
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#define ICE_TXD_CTX_QW1_TSO_LEN_S 30
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#define ICE_TXD_CTX_QW1_TSO_LEN_M \
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(0x3FFFFULL << ICE_TXD_CTX_QW1_TSO_LEN_S)
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#define ICE_TXD_CTX_QW1_MSS_S 50
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enum ice_tx_ctx_desc_cmd_bits {
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ICE_TX_CTX_DESC_TSO = 0x01,
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ICE_TX_CTX_DESC_TSYN = 0x02,
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ICE_TX_CTX_DESC_IL2TAG2 = 0x04,
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ICE_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
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ICE_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
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ICE_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
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ICE_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
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ICE_TX_CTX_DESC_SWTCH_VSI = 0x30,
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ICE_TX_CTX_DESC_RESERVED = 0x40
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};
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#define ICE_LAN_TXQ_MAX_QGRPS 127
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#define ICE_LAN_TXQ_MAX_QDIS 1023
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/* Tx queue context data
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*
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* The sizes of the variables may be larger than needed due to crossing byte
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* boundaries. If we do not have the width of the variable set to the correct
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* size then we could end up shifting bits off the top of the variable when the
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* variable is at the top of a byte and crosses over into the next byte.
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*/
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struct ice_tlan_ctx {
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#define ICE_TLAN_CTX_BASE_S 7
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u64 base; /* base is defined in 128-byte units */
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u8 port_num;
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u16 cgd_num; /* bigger than needed, see above for reason */
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u8 pf_num;
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u16 vmvf_num;
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u8 vmvf_type;
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#define ICE_TLAN_CTX_VMVF_TYPE_VF 0
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#define ICE_TLAN_CTX_VMVF_TYPE_VMQ 1
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#define ICE_TLAN_CTX_VMVF_TYPE_PF 2
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u16 src_vsi;
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u8 tsyn_ena;
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u8 alt_vlan;
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u16 cpuid; /* bigger than needed, see above for reason */
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u8 wb_mode;
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u8 tphrd_desc;
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u8 tphrd;
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u8 tphwr_desc;
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u16 cmpq_id;
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u16 qnum_in_func;
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u8 itr_notification_mode;
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u8 adjust_prof_id;
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u32 qlen; /* bigger than needed, see above for reason */
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u8 quanta_prof_idx;
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u8 tso_ena;
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u16 tso_qnum;
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u8 legacy_int;
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u8 drop_ena;
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u8 cache_prof_idx;
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u8 pkt_shaper_prof_idx;
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u8 int_q_state; /* width not needed - internal do not write */
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};
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/* macro to make the table lines short */
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#define ICE_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
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{ PTYPE, \
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1, \
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ICE_RX_PTYPE_OUTER_##OUTER_IP, \
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ICE_RX_PTYPE_OUTER_##OUTER_IP_VER, \
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ICE_RX_PTYPE_##OUTER_FRAG, \
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ICE_RX_PTYPE_TUNNEL_##T, \
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ICE_RX_PTYPE_TUNNEL_END_##TE, \
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ICE_RX_PTYPE_##TEF, \
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ICE_RX_PTYPE_INNER_PROT_##I, \
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ICE_RX_PTYPE_PAYLOAD_LAYER_##PL }
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#define ICE_PTT_UNUSED_ENTRY(PTYPE) { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
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/* shorter macros makes the table fit but are terse */
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#define ICE_RX_PTYPE_NOF ICE_RX_PTYPE_NOT_FRAG
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/* Lookup table mapping the HW PTYPE to the bit field for decoding */
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static const struct ice_rx_ptype_decoded ice_ptype_lkup[] = {
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/* L2 Packet types */
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ICE_PTT_UNUSED_ENTRY(0),
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ICE_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
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ICE_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
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};
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static inline struct ice_rx_ptype_decoded ice_decode_rx_desc_ptype(u16 ptype)
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{
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return ice_ptype_lkup[ptype];
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}
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#define ICE_LINK_SPEED_UNKNOWN 0
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#define ICE_LINK_SPEED_10MBPS 10
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#define ICE_LINK_SPEED_100MBPS 100
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#define ICE_LINK_SPEED_1000MBPS 1000
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#define ICE_LINK_SPEED_2500MBPS 2500
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#define ICE_LINK_SPEED_5000MBPS 5000
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#define ICE_LINK_SPEED_10000MBPS 10000
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#define ICE_LINK_SPEED_20000MBPS 20000
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#define ICE_LINK_SPEED_25000MBPS 25000
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#define ICE_LINK_SPEED_40000MBPS 40000
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#endif /* _ICE_LAN_TX_RX_H_ */
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