linux/drivers/clk/rockchip
Nathan Chancellor e9c006bc78 clk: rockchip: Fix initialization of mux_pll_src_4plls_p
A new warning in Clang points out that the initialization of
mux_pll_src_4plls_p appears incorrect:

../drivers/clk/rockchip/clk-rk3228.c:140:58: warning: suspicious
concatenation of string literals in an array initialization; did you
mean to separate the elements with a comma? [-Wstring-concatenation]
PNAME(mux_pll_src_4plls_p)      = { "cpll", "gpll", "hdmiphy" "usb480m" };
                                                              ^
                                                             ,
../drivers/clk/rockchip/clk-rk3228.c:140:48: note: place parentheses
around the string literal to silence warning
PNAME(mux_pll_src_4plls_p)      = { "cpll", "gpll", "hdmiphy" "usb480m" };
                                                    ^
1 warning generated.

Given the name of the variable and the same variable name in rv1108, it
seems that this should have been four distinct elements. Fix it up by
adding the comma as suggested.

Fixes: 307a2e9ac5 ("clk: rockchip: add clock controller for rk3228")
Link: https://github.com/ClangBuiltLinux/linux/issues/1123
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Link: https://lore.kernel.org/r/20200810044020.2063350-1-natechancellor@gmail.com
Reviewed-by: Heiko Stübner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-08-18 20:09:02 -07:00
..
Makefile clk: rockchip: Add clock controller for the rk3308 2019-09-05 12:43:39 +02:00
clk-cpu.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 2019-06-19 17:09:55 +02:00
clk-ddr.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 2019-05-30 11:26:37 -07:00
clk-half-divider.c clk: rockchip: make clk_half_divider_ops static 2019-10-31 12:06:01 +01:00
clk-inverter.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 2019-05-30 11:26:37 -07:00
clk-mmc-phase.c clk: rockchip: fix mmc get phase 2020-03-06 12:06:01 -08:00
clk-muxgrf.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282 2019-06-05 17:36:37 +02:00
clk-pll.c clk: rockchip: convert rk3036 pll type to use internal lock status 2020-06-15 11:47:16 +02:00
clk-px30.c clk: rockchip: protect the pclk_usb_grf as critical on px30 2019-11-05 20:53:42 +01:00
clk-rk3036.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 2019-05-30 11:26:37 -07:00
clk-rk3128.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 2019-05-30 11:26:37 -07:00
clk-rk3188.c clk: rockchip: add sclk_mac_lbtest to rk3188_critical_clocks 2020-07-22 20:05:19 +02:00
clk-rk3228.c clk: rockchip: Fix initialization of mux_pll_src_4plls_p 2020-08-18 20:09:02 -07:00
clk-rk3288.c clk: rockchip: use separate compatibles for rk3288w-cru 2020-07-05 12:18:29 +02:00
clk-rk3308.c clk: rockchip: Add clock controller for the rk3308 2019-09-05 12:43:39 +02:00
clk-rk3328.c clk: rockchip: Revert "fix wrong mmc sample phase shift for rk3328" 2020-07-08 16:22:10 +02:00
clk-rk3368.c This round of clk driver and framework updates is heavy on the driver update 2019-07-17 10:07:48 -07:00
clk-rk3399.c This round of clk driver and framework updates is heavy on the driver update 2019-07-17 10:07:48 -07:00
clk-rv1108.c clk: rockchip: Fix -Wunused-const-variable in rv1108 clk driver 2019-07-25 21:00:52 +02:00
clk.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 2019-05-30 11:26:37 -07:00
clk.h clk: rockchip: Add clock controller for the rk3308 2019-09-05 12:43:39 +02:00
softrst.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 2019-05-30 11:26:37 -07:00