mirror of https://gitee.com/openkylin/linux.git
515 lines
12 KiB
C
515 lines
12 KiB
C
/*
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* Intel specific MCE features.
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* Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca>
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* Copyright (C) 2008, 2009 Intel Corporation
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* Author: Andi Kleen
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*/
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#include <linux/gfp.h>
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#include <linux/interrupt.h>
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#include <linux/percpu.h>
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#include <linux/sched.h>
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#include <linux/cpumask.h>
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#include <asm/apic.h>
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#include <asm/cpufeature.h>
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#include <asm/intel-family.h>
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#include <asm/processor.h>
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#include <asm/msr.h>
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#include <asm/mce.h>
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#include "mce-internal.h"
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/*
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* Support for Intel Correct Machine Check Interrupts. This allows
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* the CPU to raise an interrupt when a corrected machine check happened.
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* Normally we pick those up using a regular polling timer.
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* Also supports reliable discovery of shared banks.
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*/
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/*
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* CMCI can be delivered to multiple cpus that share a machine check bank
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* so we need to designate a single cpu to process errors logged in each bank
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* in the interrupt handler (otherwise we would have many races and potential
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* double reporting of the same error).
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* Note that this can change when a cpu is offlined or brought online since
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* some MCA banks are shared across cpus. When a cpu is offlined, cmci_clear()
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* disables CMCI on all banks owned by the cpu and clears this bitfield. At
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* this point, cmci_rediscover() kicks in and a different cpu may end up
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* taking ownership of some of the shared MCA banks that were previously
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* owned by the offlined cpu.
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*/
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static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned);
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/*
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* CMCI storm detection backoff counter
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*
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* During storm, we reset this counter to INITIAL_CHECK_INTERVAL in case we've
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* encountered an error. If not, we decrement it by one. We signal the end of
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* the CMCI storm when it reaches 0.
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*/
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static DEFINE_PER_CPU(int, cmci_backoff_cnt);
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/*
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* cmci_discover_lock protects against parallel discovery attempts
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* which could race against each other.
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*/
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static DEFINE_RAW_SPINLOCK(cmci_discover_lock);
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#define CMCI_THRESHOLD 1
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#define CMCI_POLL_INTERVAL (30 * HZ)
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#define CMCI_STORM_INTERVAL (HZ)
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#define CMCI_STORM_THRESHOLD 15
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static DEFINE_PER_CPU(unsigned long, cmci_time_stamp);
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static DEFINE_PER_CPU(unsigned int, cmci_storm_cnt);
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static DEFINE_PER_CPU(unsigned int, cmci_storm_state);
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enum {
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CMCI_STORM_NONE,
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CMCI_STORM_ACTIVE,
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CMCI_STORM_SUBSIDED,
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};
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static atomic_t cmci_storm_on_cpus;
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static int cmci_supported(int *banks)
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{
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u64 cap;
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if (mca_cfg.cmci_disabled || mca_cfg.ignore_ce)
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return 0;
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/*
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* Vendor check is not strictly needed, but the initial
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* initialization is vendor keyed and this
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* makes sure none of the backdoors are entered otherwise.
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*/
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if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
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return 0;
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if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6)
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return 0;
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rdmsrl(MSR_IA32_MCG_CAP, cap);
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*banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff);
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return !!(cap & MCG_CMCI_P);
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}
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static bool lmce_supported(void)
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{
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u64 tmp;
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if (mca_cfg.lmce_disabled)
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return false;
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rdmsrl(MSR_IA32_MCG_CAP, tmp);
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/*
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* LMCE depends on recovery support in the processor. Hence both
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* MCG_SER_P and MCG_LMCE_P should be present in MCG_CAP.
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*/
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if ((tmp & (MCG_SER_P | MCG_LMCE_P)) !=
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(MCG_SER_P | MCG_LMCE_P))
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return false;
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/*
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* BIOS should indicate support for LMCE by setting bit 20 in
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* IA32_FEATURE_CONTROL without which touching MCG_EXT_CTL will
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* generate a #GP fault.
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*/
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rdmsrl(MSR_IA32_FEATURE_CONTROL, tmp);
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if ((tmp & (FEATURE_CONTROL_LOCKED | FEATURE_CONTROL_LMCE)) ==
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(FEATURE_CONTROL_LOCKED | FEATURE_CONTROL_LMCE))
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return true;
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return false;
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}
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bool mce_intel_cmci_poll(void)
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{
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if (__this_cpu_read(cmci_storm_state) == CMCI_STORM_NONE)
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return false;
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/*
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* Reset the counter if we've logged an error in the last poll
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* during the storm.
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*/
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if (machine_check_poll(0, this_cpu_ptr(&mce_banks_owned)))
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this_cpu_write(cmci_backoff_cnt, INITIAL_CHECK_INTERVAL);
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else
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this_cpu_dec(cmci_backoff_cnt);
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return true;
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}
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void mce_intel_hcpu_update(unsigned long cpu)
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{
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if (per_cpu(cmci_storm_state, cpu) == CMCI_STORM_ACTIVE)
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atomic_dec(&cmci_storm_on_cpus);
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per_cpu(cmci_storm_state, cpu) = CMCI_STORM_NONE;
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}
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static void cmci_toggle_interrupt_mode(bool on)
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{
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unsigned long flags, *owned;
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int bank;
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u64 val;
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raw_spin_lock_irqsave(&cmci_discover_lock, flags);
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owned = this_cpu_ptr(mce_banks_owned);
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for_each_set_bit(bank, owned, MAX_NR_BANKS) {
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rdmsrl(MSR_IA32_MCx_CTL2(bank), val);
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if (on)
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val |= MCI_CTL2_CMCI_EN;
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else
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val &= ~MCI_CTL2_CMCI_EN;
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wrmsrl(MSR_IA32_MCx_CTL2(bank), val);
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}
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raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
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}
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unsigned long cmci_intel_adjust_timer(unsigned long interval)
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{
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if ((this_cpu_read(cmci_backoff_cnt) > 0) &&
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(__this_cpu_read(cmci_storm_state) == CMCI_STORM_ACTIVE)) {
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mce_notify_irq();
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return CMCI_STORM_INTERVAL;
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}
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switch (__this_cpu_read(cmci_storm_state)) {
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case CMCI_STORM_ACTIVE:
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/*
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* We switch back to interrupt mode once the poll timer has
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* silenced itself. That means no events recorded and the timer
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* interval is back to our poll interval.
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*/
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__this_cpu_write(cmci_storm_state, CMCI_STORM_SUBSIDED);
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if (!atomic_sub_return(1, &cmci_storm_on_cpus))
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pr_notice("CMCI storm subsided: switching to interrupt mode\n");
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/* FALLTHROUGH */
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case CMCI_STORM_SUBSIDED:
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/*
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* We wait for all CPUs to go back to SUBSIDED state. When that
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* happens we switch back to interrupt mode.
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*/
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if (!atomic_read(&cmci_storm_on_cpus)) {
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__this_cpu_write(cmci_storm_state, CMCI_STORM_NONE);
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cmci_toggle_interrupt_mode(true);
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cmci_recheck();
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}
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return CMCI_POLL_INTERVAL;
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default:
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/* We have shiny weather. Let the poll do whatever it thinks. */
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return interval;
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}
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}
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static bool cmci_storm_detect(void)
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{
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unsigned int cnt = __this_cpu_read(cmci_storm_cnt);
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unsigned long ts = __this_cpu_read(cmci_time_stamp);
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unsigned long now = jiffies;
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int r;
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if (__this_cpu_read(cmci_storm_state) != CMCI_STORM_NONE)
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return true;
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if (time_before_eq(now, ts + CMCI_STORM_INTERVAL)) {
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cnt++;
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} else {
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cnt = 1;
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__this_cpu_write(cmci_time_stamp, now);
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}
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__this_cpu_write(cmci_storm_cnt, cnt);
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if (cnt <= CMCI_STORM_THRESHOLD)
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return false;
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cmci_toggle_interrupt_mode(false);
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__this_cpu_write(cmci_storm_state, CMCI_STORM_ACTIVE);
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r = atomic_add_return(1, &cmci_storm_on_cpus);
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mce_timer_kick(CMCI_STORM_INTERVAL);
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this_cpu_write(cmci_backoff_cnt, INITIAL_CHECK_INTERVAL);
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if (r == 1)
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pr_notice("CMCI storm detected: switching to poll mode\n");
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return true;
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}
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/*
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* The interrupt handler. This is called on every event.
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* Just call the poller directly to log any events.
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* This could in theory increase the threshold under high load,
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* but doesn't for now.
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*/
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static void intel_threshold_interrupt(void)
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{
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if (cmci_storm_detect())
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return;
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machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_banks_owned));
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}
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/*
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* Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks
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* on this CPU. Use the algorithm recommended in the SDM to discover shared
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* banks.
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*/
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static void cmci_discover(int banks)
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{
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unsigned long *owned = (void *)this_cpu_ptr(&mce_banks_owned);
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unsigned long flags;
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int i;
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int bios_wrong_thresh = 0;
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raw_spin_lock_irqsave(&cmci_discover_lock, flags);
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for (i = 0; i < banks; i++) {
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u64 val;
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int bios_zero_thresh = 0;
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if (test_bit(i, owned))
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continue;
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/* Skip banks in firmware first mode */
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if (test_bit(i, mce_banks_ce_disabled))
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continue;
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rdmsrl(MSR_IA32_MCx_CTL2(i), val);
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/* Already owned by someone else? */
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if (val & MCI_CTL2_CMCI_EN) {
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clear_bit(i, owned);
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__clear_bit(i, this_cpu_ptr(mce_poll_banks));
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continue;
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}
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if (!mca_cfg.bios_cmci_threshold) {
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val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK;
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val |= CMCI_THRESHOLD;
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} else if (!(val & MCI_CTL2_CMCI_THRESHOLD_MASK)) {
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/*
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* If bios_cmci_threshold boot option was specified
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* but the threshold is zero, we'll try to initialize
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* it to 1.
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*/
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bios_zero_thresh = 1;
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val |= CMCI_THRESHOLD;
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}
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val |= MCI_CTL2_CMCI_EN;
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wrmsrl(MSR_IA32_MCx_CTL2(i), val);
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rdmsrl(MSR_IA32_MCx_CTL2(i), val);
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/* Did the enable bit stick? -- the bank supports CMCI */
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if (val & MCI_CTL2_CMCI_EN) {
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set_bit(i, owned);
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__clear_bit(i, this_cpu_ptr(mce_poll_banks));
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/*
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* We are able to set thresholds for some banks that
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* had a threshold of 0. This means the BIOS has not
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* set the thresholds properly or does not work with
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* this boot option. Note down now and report later.
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*/
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if (mca_cfg.bios_cmci_threshold && bios_zero_thresh &&
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(val & MCI_CTL2_CMCI_THRESHOLD_MASK))
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bios_wrong_thresh = 1;
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} else {
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WARN_ON(!test_bit(i, this_cpu_ptr(mce_poll_banks)));
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}
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}
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raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
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if (mca_cfg.bios_cmci_threshold && bios_wrong_thresh) {
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pr_info_once(
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"bios_cmci_threshold: Some banks do not have valid thresholds set\n");
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pr_info_once(
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"bios_cmci_threshold: Make sure your BIOS supports this boot option\n");
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}
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}
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/*
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* Just in case we missed an event during initialization check
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* all the CMCI owned banks.
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*/
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void cmci_recheck(void)
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{
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unsigned long flags;
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int banks;
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if (!mce_available(raw_cpu_ptr(&cpu_info)) || !cmci_supported(&banks))
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return;
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local_irq_save(flags);
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machine_check_poll(0, this_cpu_ptr(&mce_banks_owned));
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local_irq_restore(flags);
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}
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/* Caller must hold the lock on cmci_discover_lock */
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static void __cmci_disable_bank(int bank)
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{
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u64 val;
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if (!test_bit(bank, this_cpu_ptr(mce_banks_owned)))
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return;
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rdmsrl(MSR_IA32_MCx_CTL2(bank), val);
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val &= ~MCI_CTL2_CMCI_EN;
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wrmsrl(MSR_IA32_MCx_CTL2(bank), val);
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__clear_bit(bank, this_cpu_ptr(mce_banks_owned));
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}
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/*
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* Disable CMCI on this CPU for all banks it owns when it goes down.
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* This allows other CPUs to claim the banks on rediscovery.
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*/
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void cmci_clear(void)
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{
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unsigned long flags;
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int i;
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int banks;
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if (!cmci_supported(&banks))
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return;
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raw_spin_lock_irqsave(&cmci_discover_lock, flags);
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for (i = 0; i < banks; i++)
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__cmci_disable_bank(i);
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raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
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}
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static void cmci_rediscover_work_func(void *arg)
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{
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int banks;
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/* Recheck banks in case CPUs don't all have the same */
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if (cmci_supported(&banks))
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cmci_discover(banks);
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}
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/* After a CPU went down cycle through all the others and rediscover */
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void cmci_rediscover(void)
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{
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int banks;
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if (!cmci_supported(&banks))
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return;
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on_each_cpu(cmci_rediscover_work_func, NULL, 1);
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}
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/*
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* Reenable CMCI on this CPU in case a CPU down failed.
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*/
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void cmci_reenable(void)
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{
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int banks;
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if (cmci_supported(&banks))
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cmci_discover(banks);
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}
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void cmci_disable_bank(int bank)
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{
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int banks;
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unsigned long flags;
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if (!cmci_supported(&banks))
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return;
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raw_spin_lock_irqsave(&cmci_discover_lock, flags);
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__cmci_disable_bank(bank);
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raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
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}
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static void intel_init_cmci(void)
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{
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int banks;
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if (!cmci_supported(&banks))
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return;
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mce_threshold_vector = intel_threshold_interrupt;
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cmci_discover(banks);
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/*
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* For CPU #0 this runs with still disabled APIC, but that's
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* ok because only the vector is set up. We still do another
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* check for the banks later for CPU #0 just to make sure
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* to not miss any events.
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*/
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apic_write(APIC_LVTCMCI, THRESHOLD_APIC_VECTOR|APIC_DM_FIXED);
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cmci_recheck();
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}
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static void intel_init_lmce(void)
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{
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u64 val;
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if (!lmce_supported())
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return;
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rdmsrl(MSR_IA32_MCG_EXT_CTL, val);
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if (!(val & MCG_EXT_CTL_LMCE_EN))
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wrmsrl(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN);
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}
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static void intel_clear_lmce(void)
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{
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u64 val;
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if (!lmce_supported())
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return;
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rdmsrl(MSR_IA32_MCG_EXT_CTL, val);
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val &= ~MCG_EXT_CTL_LMCE_EN;
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wrmsrl(MSR_IA32_MCG_EXT_CTL, val);
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}
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static void intel_ppin_init(struct cpuinfo_x86 *c)
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{
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unsigned long long val;
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/*
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* Even if testing the presence of the MSR would be enough, we don't
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* want to risk the situation where other models reuse this MSR for
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* other purposes.
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*/
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switch (c->x86_model) {
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case INTEL_FAM6_IVYBRIDGE_X:
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case INTEL_FAM6_HASWELL_X:
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case INTEL_FAM6_BROADWELL_XEON_D:
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case INTEL_FAM6_BROADWELL_X:
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case INTEL_FAM6_SKYLAKE_X:
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if (rdmsrl_safe(MSR_PPIN_CTL, &val))
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return;
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if ((val & 3UL) == 1UL) {
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/* PPIN available but disabled: */
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return;
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}
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/* If PPIN is disabled, but not locked, try to enable: */
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if (!(val & 3UL)) {
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wrmsrl_safe(MSR_PPIN_CTL, val | 2UL);
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rdmsrl_safe(MSR_PPIN_CTL, &val);
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}
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if ((val & 3UL) == 2UL)
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set_cpu_cap(c, X86_FEATURE_INTEL_PPIN);
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}
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}
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void mce_intel_feature_init(struct cpuinfo_x86 *c)
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{
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intel_init_thermal(c);
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intel_init_cmci();
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intel_init_lmce();
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intel_ppin_init(c);
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}
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void mce_intel_feature_clear(struct cpuinfo_x86 *c)
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{
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intel_clear_lmce();
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}
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