mirror of https://gitee.com/openkylin/linux.git
615 lines
16 KiB
C
615 lines
16 KiB
C
/*
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* Copyright (c) 2010 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "hw.h"
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#include "ar9003_mac.h"
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static void ar9003_hw_rx_enable(struct ath_hw *hw)
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{
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REG_WRITE(hw, AR_CR, 0);
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}
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static u16 ar9003_calc_ptr_chksum(struct ar9003_txc *ads)
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{
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int checksum;
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checksum = ads->info + ads->link
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+ ads->data0 + ads->ctl3
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+ ads->data1 + ads->ctl5
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+ ads->data2 + ads->ctl7
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+ ads->data3 + ads->ctl9;
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return ((checksum & 0xffff) + (checksum >> 16)) & AR_TxPtrChkSum;
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}
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static void ar9003_hw_set_desc_link(void *ds, u32 ds_link)
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{
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struct ar9003_txc *ads = ds;
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ads->link = ds_link;
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ads->ctl10 &= ~AR_TxPtrChkSum;
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ads->ctl10 |= ar9003_calc_ptr_chksum(ads);
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}
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static void ar9003_hw_get_desc_link(void *ds, u32 **ds_link)
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{
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struct ar9003_txc *ads = ds;
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*ds_link = &ads->link;
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}
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static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
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{
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u32 isr = 0;
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u32 mask2 = 0;
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struct ath9k_hw_capabilities *pCap = &ah->caps;
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u32 sync_cause = 0;
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struct ath_common *common = ath9k_hw_common(ah);
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if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
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if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
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== AR_RTC_STATUS_ON)
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isr = REG_READ(ah, AR_ISR);
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}
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sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
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*masked = 0;
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if (!isr && !sync_cause)
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return false;
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if (isr) {
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if (isr & AR_ISR_BCNMISC) {
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u32 isr2;
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isr2 = REG_READ(ah, AR_ISR_S2);
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mask2 |= ((isr2 & AR_ISR_S2_TIM) >>
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MAP_ISR_S2_TIM);
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mask2 |= ((isr2 & AR_ISR_S2_DTIM) >>
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MAP_ISR_S2_DTIM);
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mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >>
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MAP_ISR_S2_DTIMSYNC);
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mask2 |= ((isr2 & AR_ISR_S2_CABEND) >>
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MAP_ISR_S2_CABEND);
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mask2 |= ((isr2 & AR_ISR_S2_GTT) <<
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MAP_ISR_S2_GTT);
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mask2 |= ((isr2 & AR_ISR_S2_CST) <<
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MAP_ISR_S2_CST);
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mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >>
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MAP_ISR_S2_TSFOOR);
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if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
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REG_WRITE(ah, AR_ISR_S2, isr2);
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isr &= ~AR_ISR_BCNMISC;
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}
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}
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if ((pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED))
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isr = REG_READ(ah, AR_ISR_RAC);
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if (isr == 0xffffffff) {
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*masked = 0;
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return false;
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}
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*masked = isr & ATH9K_INT_COMMON;
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if (ah->config.rx_intr_mitigation)
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if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
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*masked |= ATH9K_INT_RXLP;
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if (ah->config.tx_intr_mitigation)
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if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM))
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*masked |= ATH9K_INT_TX;
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if (isr & (AR_ISR_LP_RXOK | AR_ISR_RXERR))
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*masked |= ATH9K_INT_RXLP;
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if (isr & AR_ISR_HP_RXOK)
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*masked |= ATH9K_INT_RXHP;
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if (isr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) {
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*masked |= ATH9K_INT_TX;
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if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
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u32 s0, s1;
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s0 = REG_READ(ah, AR_ISR_S0);
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REG_WRITE(ah, AR_ISR_S0, s0);
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s1 = REG_READ(ah, AR_ISR_S1);
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REG_WRITE(ah, AR_ISR_S1, s1);
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isr &= ~(AR_ISR_TXOK | AR_ISR_TXERR |
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AR_ISR_TXEOL);
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}
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}
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if (isr & AR_ISR_GENTMR) {
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u32 s5;
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if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)
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s5 = REG_READ(ah, AR_ISR_S5_S);
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else
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s5 = REG_READ(ah, AR_ISR_S5);
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ah->intr_gen_timer_trigger =
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MS(s5, AR_ISR_S5_GENTIMER_TRIG);
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ah->intr_gen_timer_thresh =
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MS(s5, AR_ISR_S5_GENTIMER_THRESH);
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if (ah->intr_gen_timer_trigger)
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*masked |= ATH9K_INT_GENTIMER;
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if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
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REG_WRITE(ah, AR_ISR_S5, s5);
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isr &= ~AR_ISR_GENTMR;
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}
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}
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*masked |= mask2;
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if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
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REG_WRITE(ah, AR_ISR, isr);
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(void) REG_READ(ah, AR_ISR);
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}
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}
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if (sync_cause) {
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if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
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REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
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REG_WRITE(ah, AR_RC, 0);
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*masked |= ATH9K_INT_FATAL;
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}
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if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
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ath_print(common, ATH_DBG_INTERRUPT,
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"AR_INTR_SYNC_LOCAL_TIMEOUT\n");
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REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
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(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
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}
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return true;
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}
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static void ar9003_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
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bool is_firstseg, bool is_lastseg,
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const void *ds0, dma_addr_t buf_addr,
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unsigned int qcu)
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{
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struct ar9003_txc *ads = (struct ar9003_txc *) ds;
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unsigned int descid = 0;
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ads->info = (ATHEROS_VENDOR_ID << AR_DescId_S) |
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(1 << AR_TxRxDesc_S) |
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(1 << AR_CtrlStat_S) |
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(qcu << AR_TxQcuNum_S) | 0x17;
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ads->data0 = buf_addr;
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ads->data1 = 0;
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ads->data2 = 0;
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ads->data3 = 0;
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ads->ctl3 = (seglen << AR_BufLen_S);
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ads->ctl3 &= AR_BufLen;
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/* Fill in pointer checksum and descriptor id */
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ads->ctl10 = ar9003_calc_ptr_chksum(ads);
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ads->ctl10 |= (descid << AR_TxDescId_S);
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if (is_firstseg) {
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ads->ctl12 |= (is_lastseg ? 0 : AR_TxMore);
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} else if (is_lastseg) {
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ads->ctl11 = 0;
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ads->ctl12 = 0;
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ads->ctl13 = AR9003TXC_CONST(ds0)->ctl13;
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ads->ctl14 = AR9003TXC_CONST(ds0)->ctl14;
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} else {
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/* XXX Intermediate descriptor in a multi-descriptor frame.*/
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ads->ctl11 = 0;
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ads->ctl12 = AR_TxMore;
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ads->ctl13 = 0;
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ads->ctl14 = 0;
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}
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}
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static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
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struct ath_tx_status *ts)
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{
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struct ar9003_txs *ads;
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ads = &ah->ts_ring[ah->ts_tail];
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if ((ads->status8 & AR_TxDone) == 0)
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return -EINPROGRESS;
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ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size;
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if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) ||
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(MS(ads->ds_info, AR_TxRxDesc) != 1)) {
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ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
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"Tx Descriptor error %x\n", ads->ds_info);
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memset(ads, 0, sizeof(*ads));
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return -EIO;
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}
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ts->qid = MS(ads->ds_info, AR_TxQcuNum);
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ts->desc_id = MS(ads->status1, AR_TxDescId);
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ts->ts_seqnum = MS(ads->status8, AR_SeqNum);
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ts->ts_tstamp = ads->status4;
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ts->ts_status = 0;
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ts->ts_flags = 0;
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if (ads->status3 & AR_ExcessiveRetries)
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ts->ts_status |= ATH9K_TXERR_XRETRY;
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if (ads->status3 & AR_Filtered)
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ts->ts_status |= ATH9K_TXERR_FILT;
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if (ads->status3 & AR_FIFOUnderrun) {
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ts->ts_status |= ATH9K_TXERR_FIFO;
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ath9k_hw_updatetxtriglevel(ah, true);
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}
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if (ads->status8 & AR_TxOpExceeded)
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ts->ts_status |= ATH9K_TXERR_XTXOP;
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if (ads->status3 & AR_TxTimerExpired)
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ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
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if (ads->status3 & AR_DescCfgErr)
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ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
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if (ads->status3 & AR_TxDataUnderrun) {
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ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
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ath9k_hw_updatetxtriglevel(ah, true);
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}
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if (ads->status3 & AR_TxDelimUnderrun) {
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ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
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ath9k_hw_updatetxtriglevel(ah, true);
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}
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if (ads->status2 & AR_TxBaStatus) {
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ts->ts_flags |= ATH9K_TX_BA;
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ts->ba_low = ads->status5;
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ts->ba_high = ads->status6;
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}
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ts->ts_rateindex = MS(ads->status8, AR_FinalTxIdx);
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ts->ts_rssi = MS(ads->status7, AR_TxRSSICombined);
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ts->ts_rssi_ctl0 = MS(ads->status2, AR_TxRSSIAnt00);
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ts->ts_rssi_ctl1 = MS(ads->status2, AR_TxRSSIAnt01);
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ts->ts_rssi_ctl2 = MS(ads->status2, AR_TxRSSIAnt02);
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ts->ts_rssi_ext0 = MS(ads->status7, AR_TxRSSIAnt10);
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ts->ts_rssi_ext1 = MS(ads->status7, AR_TxRSSIAnt11);
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ts->ts_rssi_ext2 = MS(ads->status7, AR_TxRSSIAnt12);
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ts->ts_shortretry = MS(ads->status3, AR_RTSFailCnt);
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ts->ts_longretry = MS(ads->status3, AR_DataFailCnt);
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ts->ts_virtcol = MS(ads->status3, AR_VirtRetryCnt);
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ts->ts_antenna = 0;
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ts->tid = MS(ads->status8, AR_TxTid);
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memset(ads, 0, sizeof(*ads));
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return 0;
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}
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static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
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u32 pktlen, enum ath9k_pkt_type type, u32 txpower,
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u32 keyIx, enum ath9k_key_type keyType, u32 flags)
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{
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struct ar9003_txc *ads = (struct ar9003_txc *) ds;
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if (txpower > ah->txpower_limit)
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txpower = ah->txpower_limit;
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txpower += ah->txpower_indexoffset;
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if (txpower > 63)
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txpower = 63;
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ads->ctl11 = (pktlen & AR_FrameLen)
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| (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
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| SM(txpower, AR_XmitPower)
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| (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
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| (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
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| (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
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| (flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0);
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ads->ctl12 =
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(keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
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| SM(type, AR_FrameType)
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| (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
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| (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
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| (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
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ads->ctl17 = SM(keyType, AR_EncrType) |
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(flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0);
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ads->ctl18 = 0;
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ads->ctl19 = AR_Not_Sounding;
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ads->ctl20 = 0;
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ads->ctl21 = 0;
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ads->ctl22 = 0;
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}
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static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
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void *lastds,
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u32 durUpdateEn, u32 rtsctsRate,
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u32 rtsctsDuration,
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struct ath9k_11n_rate_series series[],
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u32 nseries, u32 flags)
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{
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struct ar9003_txc *ads = (struct ar9003_txc *) ds;
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struct ar9003_txc *last_ads = (struct ar9003_txc *) lastds;
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u_int32_t ctl11;
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if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
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ctl11 = ads->ctl11;
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if (flags & ATH9K_TXDESC_RTSENA) {
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ctl11 &= ~AR_CTSEnable;
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ctl11 |= AR_RTSEnable;
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} else {
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ctl11 &= ~AR_RTSEnable;
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ctl11 |= AR_CTSEnable;
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}
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ads->ctl11 = ctl11;
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} else {
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ads->ctl11 = (ads->ctl11 & ~(AR_RTSEnable | AR_CTSEnable));
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}
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ads->ctl13 = set11nTries(series, 0)
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| set11nTries(series, 1)
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| set11nTries(series, 2)
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| set11nTries(series, 3)
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| (durUpdateEn ? AR_DurUpdateEna : 0)
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| SM(0, AR_BurstDur);
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ads->ctl14 = set11nRate(series, 0)
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| set11nRate(series, 1)
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| set11nRate(series, 2)
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| set11nRate(series, 3);
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ads->ctl15 = set11nPktDurRTSCTS(series, 0)
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| set11nPktDurRTSCTS(series, 1);
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ads->ctl16 = set11nPktDurRTSCTS(series, 2)
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| set11nPktDurRTSCTS(series, 3);
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ads->ctl18 = set11nRateFlags(series, 0)
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| set11nRateFlags(series, 1)
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| set11nRateFlags(series, 2)
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| set11nRateFlags(series, 3)
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| SM(rtsctsRate, AR_RTSCTSRate);
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ads->ctl19 = AR_Not_Sounding;
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last_ads->ctl13 = ads->ctl13;
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last_ads->ctl14 = ads->ctl14;
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}
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static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
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u32 aggrLen)
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{
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struct ar9003_txc *ads = (struct ar9003_txc *) ds;
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ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
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ads->ctl17 &= ~AR_AggrLen;
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ads->ctl17 |= SM(aggrLen, AR_AggrLen);
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}
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static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
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u32 numDelims)
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{
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struct ar9003_txc *ads = (struct ar9003_txc *) ds;
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unsigned int ctl17;
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ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
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/*
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* We use a stack variable to manipulate ctl6 to reduce uncached
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* read modify, modfiy, write.
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*/
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ctl17 = ads->ctl17;
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ctl17 &= ~AR_PadDelim;
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ctl17 |= SM(numDelims, AR_PadDelim);
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ads->ctl17 = ctl17;
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}
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static void ar9003_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
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{
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struct ar9003_txc *ads = (struct ar9003_txc *) ds;
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ads->ctl12 |= AR_IsAggr;
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ads->ctl12 &= ~AR_MoreAggr;
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ads->ctl17 &= ~AR_PadDelim;
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}
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static void ar9003_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
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{
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struct ar9003_txc *ads = (struct ar9003_txc *) ds;
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ads->ctl12 &= (~AR_IsAggr & ~AR_MoreAggr);
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}
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static void ar9003_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
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u32 burstDuration)
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{
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|
struct ar9003_txc *ads = (struct ar9003_txc *) ds;
|
|
|
|
ads->ctl13 &= ~AR_BurstDur;
|
|
ads->ctl13 |= SM(burstDuration, AR_BurstDur);
|
|
|
|
}
|
|
|
|
static void ar9003_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
|
|
u32 vmf)
|
|
{
|
|
struct ar9003_txc *ads = (struct ar9003_txc *) ds;
|
|
|
|
if (vmf)
|
|
ads->ctl11 |= AR_VirtMoreFrag;
|
|
else
|
|
ads->ctl11 &= ~AR_VirtMoreFrag;
|
|
}
|
|
|
|
void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
|
|
{
|
|
struct ath_hw_ops *ops = ath9k_hw_ops(hw);
|
|
|
|
ops->rx_enable = ar9003_hw_rx_enable;
|
|
ops->set_desc_link = ar9003_hw_set_desc_link;
|
|
ops->get_desc_link = ar9003_hw_get_desc_link;
|
|
ops->get_isr = ar9003_hw_get_isr;
|
|
ops->fill_txdesc = ar9003_hw_fill_txdesc;
|
|
ops->proc_txdesc = ar9003_hw_proc_txdesc;
|
|
ops->set11n_txdesc = ar9003_hw_set11n_txdesc;
|
|
ops->set11n_ratescenario = ar9003_hw_set11n_ratescenario;
|
|
ops->set11n_aggr_first = ar9003_hw_set11n_aggr_first;
|
|
ops->set11n_aggr_middle = ar9003_hw_set11n_aggr_middle;
|
|
ops->set11n_aggr_last = ar9003_hw_set11n_aggr_last;
|
|
ops->clr11n_aggr = ar9003_hw_clr11n_aggr;
|
|
ops->set11n_burstduration = ar9003_hw_set11n_burstduration;
|
|
ops->set11n_virtualmorefrag = ar9003_hw_set11n_virtualmorefrag;
|
|
}
|
|
|
|
void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
|
|
{
|
|
REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK);
|
|
}
|
|
EXPORT_SYMBOL(ath9k_hw_set_rx_bufsize);
|
|
|
|
void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
|
|
enum ath9k_rx_qtype qtype)
|
|
{
|
|
if (qtype == ATH9K_RX_QUEUE_HP)
|
|
REG_WRITE(ah, AR_HP_RXDP, rxdp);
|
|
else
|
|
REG_WRITE(ah, AR_LP_RXDP, rxdp);
|
|
}
|
|
EXPORT_SYMBOL(ath9k_hw_addrxbuf_edma);
|
|
|
|
int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
|
|
void *buf_addr)
|
|
{
|
|
struct ar9003_rxs *rxsp = (struct ar9003_rxs *) buf_addr;
|
|
unsigned int phyerr;
|
|
|
|
/* TODO: byte swap on big endian for ar9300_10 */
|
|
|
|
if ((rxsp->status11 & AR_RxDone) == 0)
|
|
return -EINPROGRESS;
|
|
|
|
if (MS(rxsp->ds_info, AR_DescId) != 0x168c)
|
|
return -EINVAL;
|
|
|
|
if ((rxsp->ds_info & (AR_TxRxDesc | AR_CtrlStat)) != 0)
|
|
return -EINPROGRESS;
|
|
|
|
if (!rxs)
|
|
return 0;
|
|
|
|
rxs->rs_status = 0;
|
|
rxs->rs_flags = 0;
|
|
|
|
rxs->rs_datalen = rxsp->status2 & AR_DataLen;
|
|
rxs->rs_tstamp = rxsp->status3;
|
|
|
|
/* XXX: Keycache */
|
|
rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined);
|
|
rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00);
|
|
rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01);
|
|
rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02);
|
|
rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10);
|
|
rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11);
|
|
rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12);
|
|
|
|
if (rxsp->status11 & AR_RxKeyIdxValid)
|
|
rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx);
|
|
else
|
|
rxs->rs_keyix = ATH9K_RXKEYIX_INVALID;
|
|
|
|
rxs->rs_rate = MS(rxsp->status1, AR_RxRate);
|
|
rxs->rs_more = (rxsp->status2 & AR_RxMore) ? 1 : 0;
|
|
|
|
rxs->rs_isaggr = (rxsp->status11 & AR_RxAggr) ? 1 : 0;
|
|
rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0;
|
|
rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7);
|
|
rxs->rs_flags = (rxsp->status4 & AR_GI) ? ATH9K_RX_GI : 0;
|
|
rxs->rs_flags |= (rxsp->status4 & AR_2040) ? ATH9K_RX_2040 : 0;
|
|
|
|
rxs->evm0 = rxsp->status6;
|
|
rxs->evm1 = rxsp->status7;
|
|
rxs->evm2 = rxsp->status8;
|
|
rxs->evm3 = rxsp->status9;
|
|
rxs->evm4 = (rxsp->status10 & 0xffff);
|
|
|
|
if (rxsp->status11 & AR_PreDelimCRCErr)
|
|
rxs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
|
|
|
|
if (rxsp->status11 & AR_PostDelimCRCErr)
|
|
rxs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
|
|
|
|
if (rxsp->status11 & AR_DecryptBusyErr)
|
|
rxs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
|
|
|
|
if ((rxsp->status11 & AR_RxFrameOK) == 0) {
|
|
if (rxsp->status11 & AR_CRCErr) {
|
|
rxs->rs_status |= ATH9K_RXERR_CRC;
|
|
} else if (rxsp->status11 & AR_PHYErr) {
|
|
rxs->rs_status |= ATH9K_RXERR_PHY;
|
|
phyerr = MS(rxsp->status11, AR_PHYErrCode);
|
|
rxs->rs_phyerr = phyerr;
|
|
} else if (rxsp->status11 & AR_DecryptCRCErr) {
|
|
rxs->rs_status |= ATH9K_RXERR_DECRYPT;
|
|
} else if (rxsp->status11 & AR_MichaelErr) {
|
|
rxs->rs_status |= ATH9K_RXERR_MIC;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(ath9k_hw_process_rxdesc_edma);
|
|
|
|
void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
|
|
{
|
|
ah->ts_tail = 0;
|
|
|
|
memset((void *) ah->ts_ring, 0,
|
|
ah->ts_size * sizeof(struct ar9003_txs));
|
|
|
|
ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
|
|
"TS Start 0x%x End 0x%x Virt %p, Size %d\n",
|
|
ah->ts_paddr_start, ah->ts_paddr_end,
|
|
ah->ts_ring, ah->ts_size);
|
|
|
|
REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start);
|
|
REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end);
|
|
}
|
|
|
|
void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
|
|
u32 ts_paddr_start,
|
|
u8 size)
|
|
{
|
|
|
|
ah->ts_paddr_start = ts_paddr_start;
|
|
ah->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9003_txs));
|
|
ah->ts_size = size;
|
|
ah->ts_ring = (struct ar9003_txs *) ts_start;
|
|
|
|
ath9k_hw_reset_txstatus_ring(ah);
|
|
}
|
|
EXPORT_SYMBOL(ath9k_hw_setup_statusring);
|