mirror of https://gitee.com/openkylin/linux.git
873 lines
20 KiB
C
873 lines
20 KiB
C
/*
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* drivers/video/pnx4008/sdum.c
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*
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* Display Update Master support
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*
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* Authors: Grigory Tolstolytkin <gtolstolytkin@ru.mvista.com>
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* Vitaly Wool <vitalywool@gmail.com>
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* Based on Philips Semiconductors's code
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*
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* Copyrght (c) 2005-2006 MontaVista Software, Inc.
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* Copyright (c) 2005 Philips Semiconductors
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/tty.h>
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#include <linux/vmalloc.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/fb.h>
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#include <linux/init.h>
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#include <linux/dma-mapping.h>
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#include <linux/clk.h>
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#include <linux/gfp.h>
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#include <asm/uaccess.h>
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#include <asm/gpio.h>
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#include "sdum.h"
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#include "fbcommon.h"
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#include "dum.h"
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/* Framebuffers we have */
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static struct pnx4008_fb_addr {
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int fb_type;
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long addr_offset;
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long fb_length;
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} fb_addr[] = {
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[0] = {
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FB_TYPE_YUV, 0, 0xB0000
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},
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[1] = {
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FB_TYPE_RGB, 0xB0000, 0x50000
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},
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};
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static struct dum_data {
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u32 lcd_phys_start;
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u32 lcd_virt_start;
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u32 slave_phys_base;
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u32 *slave_virt_base;
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int fb_owning_channel[MAX_DUM_CHANNELS];
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struct dumchannel_uf chan_uf_store[MAX_DUM_CHANNELS];
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} dum_data;
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/* Different local helper functions */
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static u32 nof_pixels_dx(struct dum_ch_setup *ch_setup)
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{
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return (ch_setup->xmax - ch_setup->xmin + 1);
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}
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static u32 nof_pixels_dy(struct dum_ch_setup *ch_setup)
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{
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return (ch_setup->ymax - ch_setup->ymin + 1);
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}
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static u32 nof_pixels_dxy(struct dum_ch_setup *ch_setup)
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{
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return (nof_pixels_dx(ch_setup) * nof_pixels_dy(ch_setup));
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}
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static u32 nof_bytes(struct dum_ch_setup *ch_setup)
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{
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u32 r = nof_pixels_dxy(ch_setup);
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switch (ch_setup->format) {
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case RGB888:
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case RGB666:
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r *= 4;
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break;
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default:
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r *= 2;
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break;
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}
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return r;
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}
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static u32 build_command(int disp_no, u32 reg, u32 val)
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{
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return ((disp_no << 26) | BIT(25) | (val << 16) | (disp_no << 10) |
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(reg << 0));
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}
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static u32 build_double_index(int disp_no, u32 val)
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{
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return ((disp_no << 26) | (val << 16) | (disp_no << 10) | (val << 0));
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}
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static void build_disp_window(struct dum_ch_setup * ch_setup, struct disp_window * dw)
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{
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dw->ymin = ch_setup->ymin;
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dw->ymax = ch_setup->ymax;
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dw->xmin_l = ch_setup->xmin & 0xFF;
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dw->xmin_h = (ch_setup->xmin & BIT(8)) >> 8;
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dw->xmax_l = ch_setup->xmax & 0xFF;
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dw->xmax_h = (ch_setup->xmax & BIT(8)) >> 8;
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}
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static int put_channel(struct dumchannel chan)
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{
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int i = chan.channelnr;
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if (i < 0 || i > MAX_DUM_CHANNELS)
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return -EINVAL;
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else {
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DUM_CH_MIN(i) = chan.dum_ch_min;
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DUM_CH_MAX(i) = chan.dum_ch_max;
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DUM_CH_CONF(i) = chan.dum_ch_conf;
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DUM_CH_CTRL(i) = chan.dum_ch_ctrl;
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}
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return 0;
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}
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static void clear_channel(int channr)
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{
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struct dumchannel chan;
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chan.channelnr = channr;
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chan.dum_ch_min = 0;
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chan.dum_ch_max = 0;
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chan.dum_ch_conf = 0;
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chan.dum_ch_ctrl = 0;
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put_channel(chan);
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}
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static int put_cmd_string(struct cmdstring cmds)
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{
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u16 *cmd_str_virtaddr;
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u32 *cmd_ptr0_virtaddr;
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u32 cmd_str_physaddr;
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int i = cmds.channelnr;
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if (i < 0 || i > MAX_DUM_CHANNELS)
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return -EINVAL;
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else if ((cmd_ptr0_virtaddr =
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(int *)ioremap_nocache(DUM_COM_BASE,
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sizeof(int) * MAX_DUM_CHANNELS)) ==
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NULL)
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return -EIOREMAPFAILED;
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else {
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cmd_str_physaddr = ioread32(&cmd_ptr0_virtaddr[cmds.channelnr]);
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if ((cmd_str_virtaddr =
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(u16 *) ioremap_nocache(cmd_str_physaddr,
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sizeof(cmds))) == NULL) {
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iounmap(cmd_ptr0_virtaddr);
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return -EIOREMAPFAILED;
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} else {
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int t;
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for (t = 0; t < 8; t++)
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iowrite16(*((u16 *)&cmds.prestringlen + t),
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cmd_str_virtaddr + t);
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for (t = 0; t < cmds.prestringlen / 2; t++)
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iowrite16(*((u16 *)&cmds.precmd + t),
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cmd_str_virtaddr + t + 8);
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for (t = 0; t < cmds.poststringlen / 2; t++)
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iowrite16(*((u16 *)&cmds.postcmd + t),
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cmd_str_virtaddr + t + 8 +
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cmds.prestringlen / 2);
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iounmap(cmd_ptr0_virtaddr);
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iounmap(cmd_str_virtaddr);
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}
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}
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return 0;
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}
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static u32 dum_ch_setup(int ch_no, struct dum_ch_setup * ch_setup)
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{
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struct cmdstring cmds_c;
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struct cmdstring *cmds = &cmds_c;
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struct disp_window dw;
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int standard;
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u32 orientation = 0;
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struct dumchannel chan = { 0 };
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int ret;
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if ((ch_setup->xmirror) || (ch_setup->ymirror) || (ch_setup->rotate)) {
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standard = 0;
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orientation = BIT(1); /* always set 9-bit-bus */
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if (ch_setup->xmirror)
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orientation |= BIT(4);
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if (ch_setup->ymirror)
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orientation |= BIT(3);
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if (ch_setup->rotate)
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orientation |= BIT(0);
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} else
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standard = 1;
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cmds->channelnr = ch_no;
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/* build command string header */
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if (standard) {
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cmds->prestringlen = 32;
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cmds->poststringlen = 0;
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} else {
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cmds->prestringlen = 48;
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cmds->poststringlen = 16;
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}
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cmds->format =
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(u16) ((ch_setup->disp_no << 4) | (BIT(3)) | (ch_setup->format));
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cmds->reserved = 0x0;
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cmds->startaddr_low = (ch_setup->minadr & 0xFFFF);
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cmds->startaddr_high = (ch_setup->minadr >> 16);
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if ((ch_setup->minadr == 0) && (ch_setup->maxadr == 0)
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&& (ch_setup->xmin == 0)
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&& (ch_setup->ymin == 0) && (ch_setup->xmax == 0)
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&& (ch_setup->ymax == 0)) {
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cmds->pixdatlen_low = 0;
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cmds->pixdatlen_high = 0;
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} else {
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u32 nbytes = nof_bytes(ch_setup);
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cmds->pixdatlen_low = (nbytes & 0xFFFF);
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cmds->pixdatlen_high = (nbytes >> 16);
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}
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if (ch_setup->slave_trans)
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cmds->pixdatlen_high |= BIT(15);
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/* build pre-string */
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build_disp_window(ch_setup, &dw);
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if (standard) {
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cmds->precmd[0] =
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build_command(ch_setup->disp_no, DISP_XMIN_L_REG, 0x99);
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cmds->precmd[1] =
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build_command(ch_setup->disp_no, DISP_XMIN_L_REG,
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dw.xmin_l);
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cmds->precmd[2] =
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build_command(ch_setup->disp_no, DISP_XMIN_H_REG,
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dw.xmin_h);
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cmds->precmd[3] =
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build_command(ch_setup->disp_no, DISP_YMIN_REG, dw.ymin);
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cmds->precmd[4] =
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build_command(ch_setup->disp_no, DISP_XMAX_L_REG,
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dw.xmax_l);
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cmds->precmd[5] =
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build_command(ch_setup->disp_no, DISP_XMAX_H_REG,
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dw.xmax_h);
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cmds->precmd[6] =
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build_command(ch_setup->disp_no, DISP_YMAX_REG, dw.ymax);
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cmds->precmd[7] =
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build_double_index(ch_setup->disp_no, DISP_PIXEL_REG);
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} else {
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if (dw.xmin_l == ch_no)
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cmds->precmd[0] =
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build_command(ch_setup->disp_no, DISP_XMIN_L_REG,
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0x99);
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else
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cmds->precmd[0] =
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build_command(ch_setup->disp_no, DISP_XMIN_L_REG,
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ch_no);
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cmds->precmd[1] =
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build_command(ch_setup->disp_no, DISP_XMIN_L_REG,
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dw.xmin_l);
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cmds->precmd[2] =
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build_command(ch_setup->disp_no, DISP_XMIN_H_REG,
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dw.xmin_h);
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cmds->precmd[3] =
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build_command(ch_setup->disp_no, DISP_YMIN_REG, dw.ymin);
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cmds->precmd[4] =
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build_command(ch_setup->disp_no, DISP_XMAX_L_REG,
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dw.xmax_l);
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cmds->precmd[5] =
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build_command(ch_setup->disp_no, DISP_XMAX_H_REG,
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dw.xmax_h);
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cmds->precmd[6] =
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build_command(ch_setup->disp_no, DISP_YMAX_REG, dw.ymax);
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cmds->precmd[7] =
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build_command(ch_setup->disp_no, DISP_1_REG, orientation);
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cmds->precmd[8] =
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build_double_index(ch_setup->disp_no, DISP_PIXEL_REG);
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cmds->precmd[9] =
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build_double_index(ch_setup->disp_no, DISP_PIXEL_REG);
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cmds->precmd[0xA] =
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build_double_index(ch_setup->disp_no, DISP_PIXEL_REG);
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cmds->precmd[0xB] =
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build_double_index(ch_setup->disp_no, DISP_PIXEL_REG);
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cmds->postcmd[0] =
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build_command(ch_setup->disp_no, DISP_1_REG, BIT(1));
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cmds->postcmd[1] =
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build_command(ch_setup->disp_no, DISP_DUMMY1_REG, 1);
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cmds->postcmd[2] =
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build_command(ch_setup->disp_no, DISP_DUMMY1_REG, 2);
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cmds->postcmd[3] =
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build_command(ch_setup->disp_no, DISP_DUMMY1_REG, 3);
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}
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if ((ret = put_cmd_string(cmds_c)) != 0) {
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return ret;
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}
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chan.channelnr = cmds->channelnr;
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chan.dum_ch_min = ch_setup->dirtybuffer + ch_setup->minadr;
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chan.dum_ch_max = ch_setup->dirtybuffer + ch_setup->maxadr;
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chan.dum_ch_conf = 0x002;
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chan.dum_ch_ctrl = 0x04;
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put_channel(chan);
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return 0;
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}
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static u32 display_open(int ch_no, int auto_update, u32 * dirty_buffer,
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u32 * frame_buffer, u32 xpos, u32 ypos, u32 w, u32 h)
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{
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struct dum_ch_setup k;
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int ret;
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/* keep width & height within display area */
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if ((xpos + w) > DISP_MAX_X_SIZE)
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w = DISP_MAX_X_SIZE - xpos;
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if ((ypos + h) > DISP_MAX_Y_SIZE)
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h = DISP_MAX_Y_SIZE - ypos;
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/* assume 1 display only */
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k.disp_no = 0;
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k.xmin = xpos;
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k.ymin = ypos;
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k.xmax = xpos + (w - 1);
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k.ymax = ypos + (h - 1);
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/* adjust min and max values if necessary */
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if (k.xmin > DISP_MAX_X_SIZE - 1)
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k.xmin = DISP_MAX_X_SIZE - 1;
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if (k.ymin > DISP_MAX_Y_SIZE - 1)
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k.ymin = DISP_MAX_Y_SIZE - 1;
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if (k.xmax > DISP_MAX_X_SIZE - 1)
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k.xmax = DISP_MAX_X_SIZE - 1;
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if (k.ymax > DISP_MAX_Y_SIZE - 1)
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k.ymax = DISP_MAX_Y_SIZE - 1;
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k.xmirror = 0;
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k.ymirror = 0;
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k.rotate = 0;
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k.minadr = (u32) frame_buffer;
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k.maxadr = (u32) frame_buffer + (((w - 1) << 10) | ((h << 2) - 2));
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k.pad = PAD_1024;
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k.dirtybuffer = (u32) dirty_buffer;
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k.format = RGB888;
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k.hwdirty = 0;
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k.slave_trans = 0;
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ret = dum_ch_setup(ch_no, &k);
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return ret;
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}
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static void lcd_reset(void)
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{
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u32 *dum_pio_base = (u32 *)IO_ADDRESS(PNX4008_PIO_BASE);
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udelay(1);
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iowrite32(BIT(19), &dum_pio_base[2]);
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udelay(1);
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iowrite32(BIT(19), &dum_pio_base[1]);
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udelay(1);
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}
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static int dum_init(struct platform_device *pdev)
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{
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struct clk *clk;
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/* enable DUM clock */
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clk = clk_get(&pdev->dev, "dum_ck");
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if (IS_ERR(clk)) {
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printk(KERN_ERR "pnx4008_dum: Unable to access DUM clock\n");
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return PTR_ERR(clk);
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}
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clk_set_rate(clk, 1);
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clk_put(clk);
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DUM_CTRL = V_DUM_RESET;
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/* set priority to "round-robin". All other params to "false" */
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DUM_CONF = BIT(9);
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/* Display 1 */
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DUM_WTCFG1 = PNX4008_DUM_WT_CFG;
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DUM_RTCFG1 = PNX4008_DUM_RT_CFG;
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DUM_TCFG = PNX4008_DUM_T_CFG;
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return 0;
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}
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static void dum_chan_init(void)
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{
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int i = 0, ch = 0;
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u32 *cmdptrs;
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u32 *cmdstrings;
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DUM_COM_BASE =
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CMDSTRING_BASEADDR + BYTES_PER_CMDSTRING * NR_OF_CMDSTRINGS;
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if ((cmdptrs =
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(u32 *) ioremap_nocache(DUM_COM_BASE,
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sizeof(u32) * NR_OF_CMDSTRINGS)) == NULL)
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return;
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for (ch = 0; ch < NR_OF_CMDSTRINGS; ch++)
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iowrite32(CMDSTRING_BASEADDR + BYTES_PER_CMDSTRING * ch,
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cmdptrs + ch);
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for (ch = 0; ch < MAX_DUM_CHANNELS; ch++)
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clear_channel(ch);
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/* Clear the cmdstrings */
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cmdstrings =
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(u32 *)ioremap_nocache(*cmdptrs,
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BYTES_PER_CMDSTRING * NR_OF_CMDSTRINGS);
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if (!cmdstrings)
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goto out;
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for (i = 0; i < NR_OF_CMDSTRINGS * BYTES_PER_CMDSTRING / sizeof(u32);
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i++)
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iowrite32(0, cmdstrings + i);
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iounmap((u32 *)cmdstrings);
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out:
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iounmap((u32 *)cmdptrs);
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}
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static void lcd_init(void)
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{
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lcd_reset();
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DUM_OUTP_FORMAT1 = 0; /* RGB666 */
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udelay(1);
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iowrite32(V_LCD_STANDBY_OFF, dum_data.slave_virt_base);
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udelay(1);
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iowrite32(V_LCD_USE_9BIT_BUS, dum_data.slave_virt_base);
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udelay(1);
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iowrite32(V_LCD_SYNC_RISE_L, dum_data.slave_virt_base);
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udelay(1);
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iowrite32(V_LCD_SYNC_RISE_H, dum_data.slave_virt_base);
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udelay(1);
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iowrite32(V_LCD_SYNC_FALL_L, dum_data.slave_virt_base);
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udelay(1);
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iowrite32(V_LCD_SYNC_FALL_H, dum_data.slave_virt_base);
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udelay(1);
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iowrite32(V_LCD_SYNC_ENABLE, dum_data.slave_virt_base);
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udelay(1);
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iowrite32(V_LCD_DISPLAY_ON, dum_data.slave_virt_base);
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udelay(1);
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}
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/* Interface exported to framebuffer drivers */
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int pnx4008_get_fb_addresses(int fb_type, void **virt_addr,
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dma_addr_t *phys_addr, int *fb_length)
|
|
{
|
|
int i;
|
|
int ret = -1;
|
|
for (i = 0; i < ARRAY_SIZE(fb_addr); i++)
|
|
if (fb_addr[i].fb_type == fb_type) {
|
|
*virt_addr = (void *)(dum_data.lcd_virt_start +
|
|
fb_addr[i].addr_offset);
|
|
*phys_addr =
|
|
dum_data.lcd_phys_start + fb_addr[i].addr_offset;
|
|
*fb_length = fb_addr[i].fb_length;
|
|
ret = 0;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
EXPORT_SYMBOL(pnx4008_get_fb_addresses);
|
|
|
|
int pnx4008_alloc_dum_channel(int dev_id)
|
|
{
|
|
int i = 0;
|
|
|
|
while ((i < MAX_DUM_CHANNELS) && (dum_data.fb_owning_channel[i] != -1))
|
|
i++;
|
|
|
|
if (i == MAX_DUM_CHANNELS)
|
|
return -ENORESOURCESLEFT;
|
|
else {
|
|
dum_data.fb_owning_channel[i] = dev_id;
|
|
return i;
|
|
}
|
|
}
|
|
|
|
EXPORT_SYMBOL(pnx4008_alloc_dum_channel);
|
|
|
|
int pnx4008_free_dum_channel(int channr, int dev_id)
|
|
{
|
|
if (channr < 0 || channr > MAX_DUM_CHANNELS)
|
|
return -EINVAL;
|
|
else if (dum_data.fb_owning_channel[channr] != dev_id)
|
|
return -EFBNOTOWNER;
|
|
else {
|
|
clear_channel(channr);
|
|
dum_data.fb_owning_channel[channr] = -1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
EXPORT_SYMBOL(pnx4008_free_dum_channel);
|
|
|
|
int pnx4008_put_dum_channel_uf(struct dumchannel_uf chan_uf, int dev_id)
|
|
{
|
|
int i = chan_uf.channelnr;
|
|
int ret;
|
|
|
|
if (i < 0 || i > MAX_DUM_CHANNELS)
|
|
return -EINVAL;
|
|
else if (dum_data.fb_owning_channel[i] != dev_id)
|
|
return -EFBNOTOWNER;
|
|
else if ((ret =
|
|
display_open(chan_uf.channelnr, 0, chan_uf.dirty,
|
|
chan_uf.source, chan_uf.y_offset,
|
|
chan_uf.x_offset, chan_uf.height,
|
|
chan_uf.width)) != 0)
|
|
return ret;
|
|
else {
|
|
dum_data.chan_uf_store[i].dirty = chan_uf.dirty;
|
|
dum_data.chan_uf_store[i].source = chan_uf.source;
|
|
dum_data.chan_uf_store[i].x_offset = chan_uf.x_offset;
|
|
dum_data.chan_uf_store[i].y_offset = chan_uf.y_offset;
|
|
dum_data.chan_uf_store[i].width = chan_uf.width;
|
|
dum_data.chan_uf_store[i].height = chan_uf.height;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
EXPORT_SYMBOL(pnx4008_put_dum_channel_uf);
|
|
|
|
int pnx4008_set_dum_channel_sync(int channr, int val, int dev_id)
|
|
{
|
|
if (channr < 0 || channr > MAX_DUM_CHANNELS)
|
|
return -EINVAL;
|
|
else if (dum_data.fb_owning_channel[channr] != dev_id)
|
|
return -EFBNOTOWNER;
|
|
else {
|
|
if (val == CONF_SYNC_ON) {
|
|
DUM_CH_CONF(channr) |= CONF_SYNCENABLE;
|
|
DUM_CH_CONF(channr) |= DUM_CHANNEL_CFG_SYNC_MASK |
|
|
DUM_CHANNEL_CFG_SYNC_MASK_SET;
|
|
} else if (val == CONF_SYNC_OFF)
|
|
DUM_CH_CONF(channr) &= ~CONF_SYNCENABLE;
|
|
else
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
EXPORT_SYMBOL(pnx4008_set_dum_channel_sync);
|
|
|
|
int pnx4008_set_dum_channel_dirty_detect(int channr, int val, int dev_id)
|
|
{
|
|
if (channr < 0 || channr > MAX_DUM_CHANNELS)
|
|
return -EINVAL;
|
|
else if (dum_data.fb_owning_channel[channr] != dev_id)
|
|
return -EFBNOTOWNER;
|
|
else {
|
|
if (val == CONF_DIRTYDETECTION_ON)
|
|
DUM_CH_CONF(channr) |= CONF_DIRTYENABLE;
|
|
else if (val == CONF_DIRTYDETECTION_OFF)
|
|
DUM_CH_CONF(channr) &= ~CONF_DIRTYENABLE;
|
|
else
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
EXPORT_SYMBOL(pnx4008_set_dum_channel_dirty_detect);
|
|
|
|
#if 0 /* Functions not used currently, but likely to be used in future */
|
|
|
|
static int get_channel(struct dumchannel *p_chan)
|
|
{
|
|
int i = p_chan->channelnr;
|
|
|
|
if (i < 0 || i > MAX_DUM_CHANNELS)
|
|
return -EINVAL;
|
|
else {
|
|
p_chan->dum_ch_min = DUM_CH_MIN(i);
|
|
p_chan->dum_ch_max = DUM_CH_MAX(i);
|
|
p_chan->dum_ch_conf = DUM_CH_CONF(i);
|
|
p_chan->dum_ch_stat = DUM_CH_STAT(i);
|
|
p_chan->dum_ch_ctrl = 0; /* WriteOnly control register */
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int pnx4008_get_dum_channel_uf(struct dumchannel_uf *p_chan_uf, int dev_id)
|
|
{
|
|
int i = p_chan_uf->channelnr;
|
|
|
|
if (i < 0 || i > MAX_DUM_CHANNELS)
|
|
return -EINVAL;
|
|
else if (dum_data.fb_owning_channel[i] != dev_id)
|
|
return -EFBNOTOWNER;
|
|
else {
|
|
p_chan_uf->dirty = dum_data.chan_uf_store[i].dirty;
|
|
p_chan_uf->source = dum_data.chan_uf_store[i].source;
|
|
p_chan_uf->x_offset = dum_data.chan_uf_store[i].x_offset;
|
|
p_chan_uf->y_offset = dum_data.chan_uf_store[i].y_offset;
|
|
p_chan_uf->width = dum_data.chan_uf_store[i].width;
|
|
p_chan_uf->height = dum_data.chan_uf_store[i].height;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
EXPORT_SYMBOL(pnx4008_get_dum_channel_uf);
|
|
|
|
int pnx4008_get_dum_channel_config(int channr, int dev_id)
|
|
{
|
|
int ret;
|
|
struct dumchannel chan;
|
|
|
|
if (channr < 0 || channr > MAX_DUM_CHANNELS)
|
|
return -EINVAL;
|
|
else if (dum_data.fb_owning_channel[channr] != dev_id)
|
|
return -EFBNOTOWNER;
|
|
else {
|
|
chan.channelnr = channr;
|
|
if ((ret = get_channel(&chan)) != 0)
|
|
return ret;
|
|
}
|
|
|
|
return (chan.dum_ch_conf & DUM_CHANNEL_CFG_MASK);
|
|
}
|
|
|
|
EXPORT_SYMBOL(pnx4008_get_dum_channel_config);
|
|
|
|
int pnx4008_force_update_dum_channel(int channr, int dev_id)
|
|
{
|
|
if (channr < 0 || channr > MAX_DUM_CHANNELS)
|
|
return -EINVAL;
|
|
|
|
else if (dum_data.fb_owning_channel[channr] != dev_id)
|
|
return -EFBNOTOWNER;
|
|
else
|
|
DUM_CH_CTRL(channr) = CTRL_SETDIRTY;
|
|
|
|
return 0;
|
|
}
|
|
|
|
EXPORT_SYMBOL(pnx4008_force_update_dum_channel);
|
|
|
|
#endif
|
|
|
|
int pnx4008_sdum_mmap(struct fb_info *info, struct vm_area_struct *vma,
|
|
struct device *dev)
|
|
{
|
|
unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
|
|
|
|
if (off < info->fix.smem_len) {
|
|
vma->vm_pgoff += 1;
|
|
return dma_mmap_writecombine(dev, vma,
|
|
(void *)dum_data.lcd_virt_start,
|
|
dum_data.lcd_phys_start,
|
|
FB_DMA_SIZE);
|
|
}
|
|
return -EINVAL;
|
|
}
|
|
|
|
EXPORT_SYMBOL(pnx4008_sdum_mmap);
|
|
|
|
int pnx4008_set_dum_exit_notification(int dev_id)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < MAX_DUM_CHANNELS; i++)
|
|
if (dum_data.fb_owning_channel[i] == dev_id)
|
|
return -ERESOURCESNOTFREED;
|
|
|
|
return 0;
|
|
}
|
|
|
|
EXPORT_SYMBOL(pnx4008_set_dum_exit_notification);
|
|
|
|
/* Platform device driver for DUM */
|
|
|
|
static int sdum_suspend(struct platform_device *pdev, pm_message_t state)
|
|
{
|
|
int retval = 0;
|
|
struct clk *clk;
|
|
|
|
clk = clk_get(0, "dum_ck");
|
|
if (!IS_ERR(clk)) {
|
|
clk_set_rate(clk, 0);
|
|
clk_put(clk);
|
|
} else
|
|
retval = PTR_ERR(clk);
|
|
|
|
/* disable BAC */
|
|
DUM_CTRL = V_BAC_DISABLE_IDLE;
|
|
|
|
/* LCD standby & turn off display */
|
|
lcd_reset();
|
|
|
|
return retval;
|
|
}
|
|
|
|
static int sdum_resume(struct platform_device *pdev)
|
|
{
|
|
int retval = 0;
|
|
struct clk *clk;
|
|
|
|
clk = clk_get(0, "dum_ck");
|
|
if (!IS_ERR(clk)) {
|
|
clk_set_rate(clk, 1);
|
|
clk_put(clk);
|
|
} else
|
|
retval = PTR_ERR(clk);
|
|
|
|
/* wait for BAC disable */
|
|
DUM_CTRL = V_BAC_DISABLE_TRIG;
|
|
|
|
while (DUM_CTRL & BAC_ENABLED)
|
|
udelay(10);
|
|
|
|
/* re-init LCD */
|
|
lcd_init();
|
|
|
|
/* enable BAC and reset MUX */
|
|
DUM_CTRL = V_BAC_ENABLE;
|
|
udelay(1);
|
|
DUM_CTRL = V_MUX_RESET;
|
|
return 0;
|
|
}
|
|
|
|
static int __devinit sdum_probe(struct platform_device *pdev)
|
|
{
|
|
int ret = 0, i = 0;
|
|
|
|
/* map frame buffer */
|
|
dum_data.lcd_virt_start = (u32) dma_alloc_writecombine(&pdev->dev,
|
|
FB_DMA_SIZE,
|
|
&dum_data.lcd_phys_start,
|
|
GFP_KERNEL);
|
|
|
|
if (!dum_data.lcd_virt_start) {
|
|
ret = -ENOMEM;
|
|
goto out_3;
|
|
}
|
|
|
|
/* map slave registers */
|
|
dum_data.slave_phys_base = PNX4008_DUM_SLAVE_BASE;
|
|
dum_data.slave_virt_base =
|
|
(u32 *) ioremap_nocache(dum_data.slave_phys_base, sizeof(u32));
|
|
|
|
if (dum_data.slave_virt_base == NULL) {
|
|
ret = -ENOMEM;
|
|
goto out_2;
|
|
}
|
|
|
|
/* initialize DUM and LCD display */
|
|
ret = dum_init(pdev);
|
|
if (ret)
|
|
goto out_1;
|
|
|
|
dum_chan_init();
|
|
lcd_init();
|
|
|
|
DUM_CTRL = V_BAC_ENABLE;
|
|
udelay(1);
|
|
DUM_CTRL = V_MUX_RESET;
|
|
|
|
/* set decode address and sync clock divider */
|
|
DUM_DECODE = dum_data.lcd_phys_start & DUM_DECODE_MASK;
|
|
DUM_CLK_DIV = PNX4008_DUM_CLK_DIV;
|
|
|
|
for (i = 0; i < MAX_DUM_CHANNELS; i++)
|
|
dum_data.fb_owning_channel[i] = -1;
|
|
|
|
/*setup wakeup interrupt */
|
|
start_int_set_rising_edge(SE_DISP_SYNC_INT);
|
|
start_int_ack(SE_DISP_SYNC_INT);
|
|
start_int_umask(SE_DISP_SYNC_INT);
|
|
|
|
return 0;
|
|
|
|
out_1:
|
|
iounmap((void *)dum_data.slave_virt_base);
|
|
out_2:
|
|
dma_free_writecombine(&pdev->dev, FB_DMA_SIZE,
|
|
(void *)dum_data.lcd_virt_start,
|
|
dum_data.lcd_phys_start);
|
|
out_3:
|
|
return ret;
|
|
}
|
|
|
|
static int sdum_remove(struct platform_device *pdev)
|
|
{
|
|
struct clk *clk;
|
|
|
|
start_int_mask(SE_DISP_SYNC_INT);
|
|
|
|
clk = clk_get(0, "dum_ck");
|
|
if (!IS_ERR(clk)) {
|
|
clk_set_rate(clk, 0);
|
|
clk_put(clk);
|
|
}
|
|
|
|
iounmap((void *)dum_data.slave_virt_base);
|
|
|
|
dma_free_writecombine(&pdev->dev, FB_DMA_SIZE,
|
|
(void *)dum_data.lcd_virt_start,
|
|
dum_data.lcd_phys_start);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver sdum_driver = {
|
|
.driver = {
|
|
.name = "pnx4008-sdum",
|
|
},
|
|
.probe = sdum_probe,
|
|
.remove = sdum_remove,
|
|
.suspend = sdum_suspend,
|
|
.resume = sdum_resume,
|
|
};
|
|
|
|
int __init sdum_init(void)
|
|
{
|
|
return platform_driver_register(&sdum_driver);
|
|
}
|
|
|
|
static void __exit sdum_exit(void)
|
|
{
|
|
platform_driver_unregister(&sdum_driver);
|
|
};
|
|
|
|
module_init(sdum_init);
|
|
module_exit(sdum_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|