mirror of https://gitee.com/openkylin/linux.git
799 lines
20 KiB
C
799 lines
20 KiB
C
/*
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* Synopsys Designware PCIe host controller driver
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Jingoo Han <jg1.han@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/msi.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/pci.h>
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#include <linux/pci_regs.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include <linux/delay.h>
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#include "pcie-designware.h"
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/* Synopsis specific PCIE configuration registers */
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#define PCIE_PORT_LINK_CONTROL 0x710
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#define PORT_LINK_MODE_MASK (0x3f << 16)
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#define PORT_LINK_MODE_1_LANES (0x1 << 16)
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#define PORT_LINK_MODE_2_LANES (0x3 << 16)
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#define PORT_LINK_MODE_4_LANES (0x7 << 16)
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#define PORT_LINK_MODE_8_LANES (0xf << 16)
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#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
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#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
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#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
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#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
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#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
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#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
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#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
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#define PCIE_MSI_ADDR_LO 0x820
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#define PCIE_MSI_ADDR_HI 0x824
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#define PCIE_MSI_INTR0_ENABLE 0x828
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#define PCIE_MSI_INTR0_MASK 0x82C
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#define PCIE_MSI_INTR0_STATUS 0x830
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#define PCIE_ATU_VIEWPORT 0x900
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#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
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#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
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#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
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#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
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#define PCIE_ATU_CR1 0x904
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#define PCIE_ATU_TYPE_MEM (0x0 << 0)
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#define PCIE_ATU_TYPE_IO (0x2 << 0)
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#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
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#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
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#define PCIE_ATU_CR2 0x908
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#define PCIE_ATU_ENABLE (0x1 << 31)
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#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
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#define PCIE_ATU_LOWER_BASE 0x90C
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#define PCIE_ATU_UPPER_BASE 0x910
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#define PCIE_ATU_LIMIT 0x914
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#define PCIE_ATU_LOWER_TARGET 0x918
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#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
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#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
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#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
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#define PCIE_ATU_UPPER_TARGET 0x91C
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/* PCIe Port Logic registers */
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#define PLR_OFFSET 0x700
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#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
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#define PCIE_PHY_DEBUG_R1_LINK_UP 0x00000010
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static struct pci_ops dw_pcie_ops;
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int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
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{
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if ((uintptr_t)addr & (size - 1)) {
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*val = 0;
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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if (size == 4)
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*val = readl(addr);
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else if (size == 2)
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*val = readw(addr);
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else if (size == 1)
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*val = readb(addr);
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else {
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*val = 0;
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val)
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{
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if ((uintptr_t)addr & (size - 1))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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if (size == 4)
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writel(val, addr);
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else if (size == 2)
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writew(val, addr);
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else if (size == 1)
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writeb(val, addr);
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else
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return PCIBIOS_BAD_REGISTER_NUMBER;
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return PCIBIOS_SUCCESSFUL;
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}
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static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
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{
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if (pp->ops->readl_rc)
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pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
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else
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*val = readl(pp->dbi_base + reg);
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}
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static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
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{
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if (pp->ops->writel_rc)
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pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
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else
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writel(val, pp->dbi_base + reg);
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}
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static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
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u32 *val)
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{
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if (pp->ops->rd_own_conf)
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return pp->ops->rd_own_conf(pp, where, size, val);
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return dw_pcie_cfg_read(pp->dbi_base + where, size, val);
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}
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static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
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u32 val)
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{
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if (pp->ops->wr_own_conf)
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return pp->ops->wr_own_conf(pp, where, size, val);
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return dw_pcie_cfg_write(pp->dbi_base + where, size, val);
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}
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static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
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int type, u64 cpu_addr, u64 pci_addr, u32 size)
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{
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u32 val;
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dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index,
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PCIE_ATU_VIEWPORT);
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dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE);
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dw_pcie_writel_rc(pp, upper_32_bits(cpu_addr), PCIE_ATU_UPPER_BASE);
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dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr + size - 1),
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PCIE_ATU_LIMIT);
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dw_pcie_writel_rc(pp, lower_32_bits(pci_addr), PCIE_ATU_LOWER_TARGET);
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dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET);
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dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1);
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dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
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/*
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* Make sure ATU enable takes effect before any subsequent config
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* and I/O accesses.
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*/
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dw_pcie_readl_rc(pp, PCIE_ATU_CR2, &val);
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}
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static struct irq_chip dw_msi_irq_chip = {
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.name = "PCI-MSI",
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.irq_enable = pci_msi_unmask_irq,
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.irq_disable = pci_msi_mask_irq,
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.irq_mask = pci_msi_mask_irq,
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.irq_unmask = pci_msi_unmask_irq,
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};
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/* MSI int handler */
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irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
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{
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unsigned long val;
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int i, pos, irq;
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irqreturn_t ret = IRQ_NONE;
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for (i = 0; i < MAX_MSI_CTRLS; i++) {
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dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
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(u32 *)&val);
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if (val) {
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ret = IRQ_HANDLED;
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pos = 0;
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while ((pos = find_next_bit(&val, 32, pos)) != 32) {
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irq = irq_find_mapping(pp->irq_domain,
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i * 32 + pos);
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dw_pcie_wr_own_conf(pp,
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PCIE_MSI_INTR0_STATUS + i * 12,
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4, 1 << pos);
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generic_handle_irq(irq);
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pos++;
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}
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}
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}
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return ret;
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}
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void dw_pcie_msi_init(struct pcie_port *pp)
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{
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u64 msi_target;
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pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
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msi_target = virt_to_phys((void *)pp->msi_data);
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/* program the msi_data */
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dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
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(u32)(msi_target & 0xffffffff));
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dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
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(u32)(msi_target >> 32 & 0xffffffff));
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}
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static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
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{
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unsigned int res, bit, val;
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res = (irq / 32) * 12;
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bit = irq % 32;
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dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
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val &= ~(1 << bit);
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dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
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}
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static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
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unsigned int nvec, unsigned int pos)
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{
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unsigned int i;
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for (i = 0; i < nvec; i++) {
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irq_set_msi_desc_off(irq_base, i, NULL);
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/* Disable corresponding interrupt on MSI controller */
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if (pp->ops->msi_clear_irq)
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pp->ops->msi_clear_irq(pp, pos + i);
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else
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dw_pcie_msi_clear_irq(pp, pos + i);
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}
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bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec));
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}
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static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
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{
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unsigned int res, bit, val;
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res = (irq / 32) * 12;
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bit = irq % 32;
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dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
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val |= 1 << bit;
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dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
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}
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static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
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{
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int irq, pos0, i;
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struct pcie_port *pp = (struct pcie_port *) msi_desc_to_pci_sysdata(desc);
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pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
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order_base_2(no_irqs));
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if (pos0 < 0)
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goto no_valid_irq;
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irq = irq_find_mapping(pp->irq_domain, pos0);
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if (!irq)
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goto no_valid_irq;
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/*
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* irq_create_mapping (called from dw_pcie_host_init) pre-allocates
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* descs so there is no need to allocate descs here. We can therefore
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* assume that if irq_find_mapping above returns non-zero, then the
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* descs are also successfully allocated.
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*/
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for (i = 0; i < no_irqs; i++) {
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if (irq_set_msi_desc_off(irq, i, desc) != 0) {
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clear_irq_range(pp, irq, i, pos0);
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goto no_valid_irq;
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}
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/*Enable corresponding interrupt in MSI interrupt controller */
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if (pp->ops->msi_set_irq)
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pp->ops->msi_set_irq(pp, pos0 + i);
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else
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dw_pcie_msi_set_irq(pp, pos0 + i);
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}
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*pos = pos0;
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desc->nvec_used = no_irqs;
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desc->msi_attrib.multiple = order_base_2(no_irqs);
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return irq;
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no_valid_irq:
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*pos = pos0;
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return -ENOSPC;
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}
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static void dw_msi_setup_msg(struct pcie_port *pp, unsigned int irq, u32 pos)
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{
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struct msi_msg msg;
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u64 msi_target;
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if (pp->ops->get_msi_addr)
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msi_target = pp->ops->get_msi_addr(pp);
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else
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msi_target = virt_to_phys((void *)pp->msi_data);
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msg.address_lo = (u32)(msi_target & 0xffffffff);
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msg.address_hi = (u32)(msi_target >> 32 & 0xffffffff);
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if (pp->ops->get_msi_data)
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msg.data = pp->ops->get_msi_data(pp, pos);
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else
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msg.data = pos;
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pci_write_msi_msg(irq, &msg);
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}
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static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
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struct msi_desc *desc)
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{
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int irq, pos;
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struct pcie_port *pp = pdev->bus->sysdata;
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if (desc->msi_attrib.is_msix)
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return -EINVAL;
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irq = assign_irq(1, desc, &pos);
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if (irq < 0)
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return irq;
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dw_msi_setup_msg(pp, irq, pos);
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return 0;
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}
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static int dw_msi_setup_irqs(struct msi_controller *chip, struct pci_dev *pdev,
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int nvec, int type)
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{
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#ifdef CONFIG_PCI_MSI
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int irq, pos;
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struct msi_desc *desc;
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struct pcie_port *pp = pdev->bus->sysdata;
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/* MSI-X interrupts are not supported */
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if (type == PCI_CAP_ID_MSIX)
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return -EINVAL;
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WARN_ON(!list_is_singular(&pdev->dev.msi_list));
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desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list);
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irq = assign_irq(nvec, desc, &pos);
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if (irq < 0)
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return irq;
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dw_msi_setup_msg(pp, irq, pos);
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return 0;
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#else
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return -EINVAL;
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#endif
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}
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static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
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{
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struct irq_data *data = irq_get_irq_data(irq);
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struct msi_desc *msi = irq_data_get_msi_desc(data);
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struct pcie_port *pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
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clear_irq_range(pp, irq, 1, data->hwirq);
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}
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static struct msi_controller dw_pcie_msi_chip = {
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.setup_irq = dw_msi_setup_irq,
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.setup_irqs = dw_msi_setup_irqs,
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.teardown_irq = dw_msi_teardown_irq,
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};
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int dw_pcie_wait_for_link(struct pcie_port *pp)
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{
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int retries;
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/* check if the link is up or not */
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for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
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if (dw_pcie_link_up(pp)) {
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dev_info(pp->dev, "link up\n");
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return 0;
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}
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usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
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}
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dev_err(pp->dev, "phy link never came up\n");
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return -ETIMEDOUT;
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}
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int dw_pcie_link_up(struct pcie_port *pp)
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{
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u32 val;
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if (pp->ops->link_up)
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return pp->ops->link_up(pp);
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val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
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return val & PCIE_PHY_DEBUG_R1_LINK_UP;
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}
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static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
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irq_set_chip_data(irq, domain->host_data);
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return 0;
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}
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static const struct irq_domain_ops msi_domain_ops = {
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.map = dw_pcie_msi_map,
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};
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int dw_pcie_host_init(struct pcie_port *pp)
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{
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struct device_node *np = pp->dev->of_node;
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struct platform_device *pdev = to_platform_device(pp->dev);
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struct pci_bus *bus, *child;
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struct resource *cfg_res;
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int i, ret;
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LIST_HEAD(res);
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struct resource_entry *win;
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cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
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if (cfg_res) {
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pp->cfg0_size = resource_size(cfg_res)/2;
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pp->cfg1_size = resource_size(cfg_res)/2;
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pp->cfg0_base = cfg_res->start;
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pp->cfg1_base = cfg_res->start + pp->cfg0_size;
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} else if (!pp->va_cfg0_base) {
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dev_err(pp->dev, "missing *config* reg space\n");
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}
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ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base);
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if (ret)
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return ret;
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/* Get the I/O and memory ranges from DT */
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resource_list_for_each_entry(win, &res) {
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switch (resource_type(win->res)) {
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case IORESOURCE_IO:
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pp->io = win->res;
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pp->io->name = "I/O";
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pp->io_size = resource_size(pp->io);
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|
pp->io_bus_addr = pp->io->start - win->offset;
|
|
ret = pci_remap_iospace(pp->io, pp->io_base);
|
|
if (ret) {
|
|
dev_warn(pp->dev, "error %d: failed to map resource %pR\n",
|
|
ret, pp->io);
|
|
continue;
|
|
}
|
|
break;
|
|
case IORESOURCE_MEM:
|
|
pp->mem = win->res;
|
|
pp->mem->name = "MEM";
|
|
pp->mem_size = resource_size(pp->mem);
|
|
pp->mem_bus_addr = pp->mem->start - win->offset;
|
|
break;
|
|
case 0:
|
|
pp->cfg = win->res;
|
|
pp->cfg0_size = resource_size(pp->cfg)/2;
|
|
pp->cfg1_size = resource_size(pp->cfg)/2;
|
|
pp->cfg0_base = pp->cfg->start;
|
|
pp->cfg1_base = pp->cfg->start + pp->cfg0_size;
|
|
break;
|
|
case IORESOURCE_BUS:
|
|
pp->busn = win->res;
|
|
break;
|
|
default:
|
|
continue;
|
|
}
|
|
}
|
|
|
|
if (!pp->dbi_base) {
|
|
pp->dbi_base = devm_ioremap(pp->dev, pp->cfg->start,
|
|
resource_size(pp->cfg));
|
|
if (!pp->dbi_base) {
|
|
dev_err(pp->dev, "error with ioremap\n");
|
|
return -ENOMEM;
|
|
}
|
|
}
|
|
|
|
pp->mem_base = pp->mem->start;
|
|
|
|
if (!pp->va_cfg0_base) {
|
|
pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
|
|
pp->cfg0_size);
|
|
if (!pp->va_cfg0_base) {
|
|
dev_err(pp->dev, "error with ioremap in function\n");
|
|
return -ENOMEM;
|
|
}
|
|
}
|
|
|
|
if (!pp->va_cfg1_base) {
|
|
pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
|
|
pp->cfg1_size);
|
|
if (!pp->va_cfg1_base) {
|
|
dev_err(pp->dev, "error with ioremap\n");
|
|
return -ENOMEM;
|
|
}
|
|
}
|
|
|
|
ret = of_property_read_u32(np, "num-lanes", &pp->lanes);
|
|
if (ret)
|
|
pp->lanes = 0;
|
|
|
|
if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
|
if (!pp->ops->msi_host_init) {
|
|
pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
|
|
MAX_MSI_IRQS, &msi_domain_ops,
|
|
&dw_pcie_msi_chip);
|
|
if (!pp->irq_domain) {
|
|
dev_err(pp->dev, "irq domain init failed\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
for (i = 0; i < MAX_MSI_IRQS; i++)
|
|
irq_create_mapping(pp->irq_domain, i);
|
|
} else {
|
|
ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
if (pp->ops->host_init)
|
|
pp->ops->host_init(pp);
|
|
|
|
pp->root_bus_nr = pp->busn->start;
|
|
if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
|
bus = pci_scan_root_bus_msi(pp->dev, pp->root_bus_nr,
|
|
&dw_pcie_ops, pp, &res,
|
|
&dw_pcie_msi_chip);
|
|
dw_pcie_msi_chip.dev = pp->dev;
|
|
} else
|
|
bus = pci_scan_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops,
|
|
pp, &res);
|
|
if (!bus)
|
|
return -ENOMEM;
|
|
|
|
if (pp->ops->scan_bus)
|
|
pp->ops->scan_bus(pp);
|
|
|
|
#ifdef CONFIG_ARM
|
|
/* support old dtbs that incorrectly describe IRQs */
|
|
pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
|
|
#endif
|
|
|
|
pci_bus_size_bridges(bus);
|
|
pci_bus_assign_resources(bus);
|
|
|
|
list_for_each_entry(child, &bus->children, node)
|
|
pcie_bus_configure_settings(child);
|
|
|
|
pci_bus_add_devices(bus);
|
|
return 0;
|
|
}
|
|
|
|
static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
|
|
u32 devfn, int where, int size, u32 *val)
|
|
{
|
|
int ret, type;
|
|
u32 busdev, cfg_size;
|
|
u64 cpu_addr;
|
|
void __iomem *va_cfg_base;
|
|
|
|
if (pp->ops->rd_other_conf)
|
|
return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
|
|
|
|
busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
|
|
PCIE_ATU_FUNC(PCI_FUNC(devfn));
|
|
|
|
if (bus->parent->number == pp->root_bus_nr) {
|
|
type = PCIE_ATU_TYPE_CFG0;
|
|
cpu_addr = pp->cfg0_base;
|
|
cfg_size = pp->cfg0_size;
|
|
va_cfg_base = pp->va_cfg0_base;
|
|
} else {
|
|
type = PCIE_ATU_TYPE_CFG1;
|
|
cpu_addr = pp->cfg1_base;
|
|
cfg_size = pp->cfg1_size;
|
|
va_cfg_base = pp->va_cfg1_base;
|
|
}
|
|
|
|
dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
|
|
type, cpu_addr,
|
|
busdev, cfg_size);
|
|
ret = dw_pcie_cfg_read(va_cfg_base + where, size, val);
|
|
dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
|
|
PCIE_ATU_TYPE_IO, pp->io_base,
|
|
pp->io_bus_addr, pp->io_size);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
|
|
u32 devfn, int where, int size, u32 val)
|
|
{
|
|
int ret, type;
|
|
u32 busdev, cfg_size;
|
|
u64 cpu_addr;
|
|
void __iomem *va_cfg_base;
|
|
|
|
if (pp->ops->wr_other_conf)
|
|
return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
|
|
|
|
busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
|
|
PCIE_ATU_FUNC(PCI_FUNC(devfn));
|
|
|
|
if (bus->parent->number == pp->root_bus_nr) {
|
|
type = PCIE_ATU_TYPE_CFG0;
|
|
cpu_addr = pp->cfg0_base;
|
|
cfg_size = pp->cfg0_size;
|
|
va_cfg_base = pp->va_cfg0_base;
|
|
} else {
|
|
type = PCIE_ATU_TYPE_CFG1;
|
|
cpu_addr = pp->cfg1_base;
|
|
cfg_size = pp->cfg1_size;
|
|
va_cfg_base = pp->va_cfg1_base;
|
|
}
|
|
|
|
dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
|
|
type, cpu_addr,
|
|
busdev, cfg_size);
|
|
ret = dw_pcie_cfg_write(va_cfg_base + where, size, val);
|
|
dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
|
|
PCIE_ATU_TYPE_IO, pp->io_base,
|
|
pp->io_bus_addr, pp->io_size);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dw_pcie_valid_config(struct pcie_port *pp,
|
|
struct pci_bus *bus, int dev)
|
|
{
|
|
/* If there is no link, then there is no device */
|
|
if (bus->number != pp->root_bus_nr) {
|
|
if (!dw_pcie_link_up(pp))
|
|
return 0;
|
|
}
|
|
|
|
/* access only one slot on each root port */
|
|
if (bus->number == pp->root_bus_nr && dev > 0)
|
|
return 0;
|
|
|
|
/*
|
|
* do not read more than one device on the bus directly attached
|
|
* to RC's (Virtual Bridge's) DS side.
|
|
*/
|
|
if (bus->primary == pp->root_bus_nr && dev > 0)
|
|
return 0;
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
|
|
int size, u32 *val)
|
|
{
|
|
struct pcie_port *pp = bus->sysdata;
|
|
|
|
if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
|
|
*val = 0xffffffff;
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
}
|
|
|
|
if (bus->number == pp->root_bus_nr)
|
|
return dw_pcie_rd_own_conf(pp, where, size, val);
|
|
|
|
return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
|
|
}
|
|
|
|
static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
|
|
int where, int size, u32 val)
|
|
{
|
|
struct pcie_port *pp = bus->sysdata;
|
|
|
|
if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
if (bus->number == pp->root_bus_nr)
|
|
return dw_pcie_wr_own_conf(pp, where, size, val);
|
|
|
|
return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
|
|
}
|
|
|
|
static struct pci_ops dw_pcie_ops = {
|
|
.read = dw_pcie_rd_conf,
|
|
.write = dw_pcie_wr_conf,
|
|
};
|
|
|
|
void dw_pcie_setup_rc(struct pcie_port *pp)
|
|
{
|
|
u32 val;
|
|
|
|
/* set the number of lanes */
|
|
dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
|
|
val &= ~PORT_LINK_MODE_MASK;
|
|
switch (pp->lanes) {
|
|
case 1:
|
|
val |= PORT_LINK_MODE_1_LANES;
|
|
break;
|
|
case 2:
|
|
val |= PORT_LINK_MODE_2_LANES;
|
|
break;
|
|
case 4:
|
|
val |= PORT_LINK_MODE_4_LANES;
|
|
break;
|
|
case 8:
|
|
val |= PORT_LINK_MODE_8_LANES;
|
|
break;
|
|
default:
|
|
dev_err(pp->dev, "num-lanes %u: invalid value\n", pp->lanes);
|
|
return;
|
|
}
|
|
dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
|
|
|
|
/* set link width speed control register */
|
|
dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
|
|
val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
|
|
switch (pp->lanes) {
|
|
case 1:
|
|
val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
|
|
break;
|
|
case 2:
|
|
val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
|
|
break;
|
|
case 4:
|
|
val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
|
|
break;
|
|
case 8:
|
|
val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
|
|
break;
|
|
}
|
|
dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
|
|
|
|
/* setup RC BARs */
|
|
dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
|
|
dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
|
|
|
|
/* setup interrupt pins */
|
|
dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
|
|
val &= 0xffff00ff;
|
|
val |= 0x00000100;
|
|
dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
|
|
|
|
/* setup bus numbers */
|
|
dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
|
|
val &= 0xff000000;
|
|
val |= 0x00010100;
|
|
dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
|
|
|
|
/* setup command register */
|
|
dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
|
|
val &= 0xffff0000;
|
|
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
|
|
PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
|
|
dw_pcie_writel_rc(pp, val, PCI_COMMAND);
|
|
|
|
/*
|
|
* If the platform provides ->rd_other_conf, it means the platform
|
|
* uses its own address translation component rather than ATU, so
|
|
* we should not program the ATU here.
|
|
*/
|
|
if (!pp->ops->rd_other_conf)
|
|
dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
|
|
PCIE_ATU_TYPE_MEM, pp->mem_base,
|
|
pp->mem_bus_addr, pp->mem_size);
|
|
|
|
dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
|
|
|
|
/* program correct class for RC */
|
|
dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
|
|
|
|
dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
|
|
val |= PORT_LOGIC_SPEED_CHANGE;
|
|
dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
|
|
}
|
|
|
|
MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
|
|
MODULE_DESCRIPTION("Designware PCIe host controller driver");
|
|
MODULE_LICENSE("GPL v2");
|