mirror of https://gitee.com/openkylin/linux.git
292 lines
6.4 KiB
C
292 lines
6.4 KiB
C
#ifndef _ASM_X86_SPECIAL_INSNS_H
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#define _ASM_X86_SPECIAL_INSNS_H
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#ifdef __KERNEL__
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#include <asm/nops.h>
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static inline void native_clts(void)
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{
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asm volatile("clts");
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}
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/*
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* Volatile isn't enough to prevent the compiler from reordering the
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* read/write functions for the control registers and messing everything up.
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* A memory clobber would solve the problem, but would prevent reordering of
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* all loads stores around it, which can hurt performance. Solution is to
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* use a variable and mimic reads and writes to it to enforce serialization
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*/
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extern unsigned long __force_order;
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static inline unsigned long native_read_cr0(void)
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{
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unsigned long val;
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asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order));
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return val;
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}
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static inline void native_write_cr0(unsigned long val)
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{
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asm volatile("mov %0,%%cr0": : "r" (val), "m" (__force_order));
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}
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static inline unsigned long native_read_cr2(void)
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{
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unsigned long val;
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asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order));
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return val;
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}
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static inline void native_write_cr2(unsigned long val)
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{
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asm volatile("mov %0,%%cr2": : "r" (val), "m" (__force_order));
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}
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static inline unsigned long native_read_cr3(void)
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{
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unsigned long val;
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asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order));
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return val;
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}
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static inline void native_write_cr3(unsigned long val)
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{
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asm volatile("mov %0,%%cr3": : "r" (val), "m" (__force_order));
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}
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static inline unsigned long native_read_cr4(void)
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{
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unsigned long val;
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asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order));
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return val;
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}
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static inline unsigned long native_read_cr4_safe(void)
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{
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unsigned long val;
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/* This could fault if %cr4 does not exist. In x86_64, a cr4 always
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* exists, so it will never fail. */
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#ifdef CONFIG_X86_32
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asm volatile("1: mov %%cr4, %0\n"
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"2:\n"
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_ASM_EXTABLE(1b, 2b)
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: "=r" (val), "=m" (__force_order) : "0" (0));
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#else
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val = native_read_cr4();
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#endif
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return val;
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}
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static inline void native_write_cr4(unsigned long val)
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{
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asm volatile("mov %0,%%cr4": : "r" (val), "m" (__force_order));
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}
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#ifdef CONFIG_X86_64
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static inline unsigned long native_read_cr8(void)
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{
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unsigned long cr8;
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asm volatile("movq %%cr8,%0" : "=r" (cr8));
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return cr8;
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}
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static inline void native_write_cr8(unsigned long val)
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{
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asm volatile("movq %0,%%cr8" :: "r" (val) : "memory");
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}
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#endif
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#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
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static inline u32 __read_pkru(void)
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{
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u32 ecx = 0;
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u32 edx, pkru;
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/*
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* "rdpkru" instruction. Places PKRU contents in to EAX,
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* clears EDX and requires that ecx=0.
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*/
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asm volatile(".byte 0x0f,0x01,0xee\n\t"
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: "=a" (pkru), "=d" (edx)
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: "c" (ecx));
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return pkru;
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}
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#else
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static inline u32 __read_pkru(void)
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{
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return 0;
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}
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#endif
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static inline void native_wbinvd(void)
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{
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asm volatile("wbinvd": : :"memory");
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}
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extern asmlinkage void native_load_gs_index(unsigned);
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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static inline unsigned long read_cr0(void)
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{
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return native_read_cr0();
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}
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static inline void write_cr0(unsigned long x)
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{
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native_write_cr0(x);
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}
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static inline unsigned long read_cr2(void)
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{
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return native_read_cr2();
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}
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static inline void write_cr2(unsigned long x)
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{
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native_write_cr2(x);
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}
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static inline unsigned long read_cr3(void)
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{
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return native_read_cr3();
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}
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static inline void write_cr3(unsigned long x)
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{
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native_write_cr3(x);
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}
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static inline unsigned long __read_cr4(void)
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{
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return native_read_cr4();
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}
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static inline unsigned long __read_cr4_safe(void)
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{
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return native_read_cr4_safe();
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}
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static inline void __write_cr4(unsigned long x)
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{
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native_write_cr4(x);
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}
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static inline void wbinvd(void)
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{
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native_wbinvd();
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}
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#ifdef CONFIG_X86_64
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static inline unsigned long read_cr8(void)
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{
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return native_read_cr8();
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}
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static inline void write_cr8(unsigned long x)
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{
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native_write_cr8(x);
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}
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static inline void load_gs_index(unsigned selector)
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{
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native_load_gs_index(selector);
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}
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#endif
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/* Clear the 'TS' bit */
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static inline void clts(void)
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{
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native_clts();
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}
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#endif/* CONFIG_PARAVIRT */
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#define stts() write_cr0(read_cr0() | X86_CR0_TS)
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static inline void clflush(volatile void *__p)
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{
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asm volatile("clflush %0" : "+m" (*(volatile char __force *)__p));
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}
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static inline void clflushopt(volatile void *__p)
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{
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alternative_io(".byte " __stringify(NOP_DS_PREFIX) "; clflush %P0",
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".byte 0x66; clflush %P0",
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X86_FEATURE_CLFLUSHOPT,
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"+m" (*(volatile char __force *)__p));
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}
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static inline void clwb(volatile void *__p)
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{
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volatile struct { char x[64]; } *p = __p;
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asm volatile(ALTERNATIVE_2(
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".byte " __stringify(NOP_DS_PREFIX) "; clflush (%[pax])",
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".byte 0x66; clflush (%[pax])", /* clflushopt (%%rax) */
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X86_FEATURE_CLFLUSHOPT,
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".byte 0x66, 0x0f, 0xae, 0x30", /* clwb (%%rax) */
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X86_FEATURE_CLWB)
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: [p] "+m" (*p)
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: [pax] "a" (p));
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}
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/**
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* pcommit_sfence() - persistent commit and fence
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*
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* The PCOMMIT instruction ensures that data that has been flushed from the
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* processor's cache hierarchy with CLWB, CLFLUSHOPT or CLFLUSH is accepted to
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* memory and is durable on the DIMM. The primary use case for this is
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* persistent memory.
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*
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* This function shows how to properly use CLWB/CLFLUSHOPT/CLFLUSH and PCOMMIT
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* with appropriate fencing.
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*
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* Example:
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* void flush_and_commit_buffer(void *vaddr, unsigned int size)
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* {
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* unsigned long clflush_mask = boot_cpu_data.x86_clflush_size - 1;
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* void *vend = vaddr + size;
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* void *p;
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*
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* for (p = (void *)((unsigned long)vaddr & ~clflush_mask);
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* p < vend; p += boot_cpu_data.x86_clflush_size)
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* clwb(p);
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*
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* // SFENCE to order CLWB/CLFLUSHOPT/CLFLUSH cache flushes
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* // MFENCE via mb() also works
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* wmb();
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*
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* // PCOMMIT and the required SFENCE for ordering
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* pcommit_sfence();
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* }
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*
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* After this function completes the data pointed to by 'vaddr' has been
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* accepted to memory and will be durable if the 'vaddr' points to persistent
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* memory.
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*
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* PCOMMIT must always be ordered by an MFENCE or SFENCE, so to help simplify
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* things we include both the PCOMMIT and the required SFENCE in the
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* alternatives generated by pcommit_sfence().
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*/
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static inline void pcommit_sfence(void)
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{
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alternative(ASM_NOP7,
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".byte 0x66, 0x0f, 0xae, 0xf8\n\t" /* pcommit */
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"sfence",
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X86_FEATURE_PCOMMIT);
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}
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#define nop() asm volatile ("nop")
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#endif /* __KERNEL__ */
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#endif /* _ASM_X86_SPECIAL_INSNS_H */
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