mirror of https://gitee.com/openkylin/linux.git
731 lines
18 KiB
C
731 lines
18 KiB
C
/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/fs.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/smp.h>
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#include <linux/sysfs.h>
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#include <linux/stat.h>
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#include <linux/pm_runtime.h>
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#include <linux/cpu.h>
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#include <linux/of.h>
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#include <linux/coresight.h>
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#include <linux/amba/bus.h>
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#include <linux/seq_file.h>
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#include <linux/uaccess.h>
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#include <linux/clk.h>
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#include <asm/sections.h>
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#include "coresight-etm.h"
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static int boot_enable;
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module_param_named(boot_enable, boot_enable, int, S_IRUGO);
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/* The number of ETM/PTM currently registered */
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static int etm_count;
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static struct etm_drvdata *etmdrvdata[NR_CPUS];
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static void etm_init_default_data(struct etm_config *config);
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/*
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* Memory mapped writes to clear os lock are not supported on some processors
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* and OS lock must be unlocked before any memory mapped access on such
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* processors, otherwise memory mapped reads/writes will be invalid.
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*/
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static void etm_os_unlock(struct etm_drvdata *drvdata)
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{
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/* Writing any value to ETMOSLAR unlocks the trace registers */
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etm_writel(drvdata, 0x0, ETMOSLAR);
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drvdata->os_unlock = true;
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isb();
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}
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static void etm_set_pwrdwn(struct etm_drvdata *drvdata)
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{
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u32 etmcr;
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/* Ensure pending cp14 accesses complete before setting pwrdwn */
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mb();
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isb();
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etmcr = etm_readl(drvdata, ETMCR);
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etmcr |= ETMCR_PWD_DWN;
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etm_writel(drvdata, etmcr, ETMCR);
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}
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static void etm_clr_pwrdwn(struct etm_drvdata *drvdata)
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{
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u32 etmcr;
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etmcr = etm_readl(drvdata, ETMCR);
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etmcr &= ~ETMCR_PWD_DWN;
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etm_writel(drvdata, etmcr, ETMCR);
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/* Ensure pwrup completes before subsequent cp14 accesses */
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mb();
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isb();
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}
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static void etm_set_pwrup(struct etm_drvdata *drvdata)
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{
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u32 etmpdcr;
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etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
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etmpdcr |= ETMPDCR_PWD_UP;
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writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
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/* Ensure pwrup completes before subsequent cp14 accesses */
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mb();
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isb();
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}
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static void etm_clr_pwrup(struct etm_drvdata *drvdata)
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{
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u32 etmpdcr;
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/* Ensure pending cp14 accesses complete before clearing pwrup */
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mb();
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isb();
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etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
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etmpdcr &= ~ETMPDCR_PWD_UP;
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writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
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}
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/**
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* coresight_timeout_etm - loop until a bit has changed to a specific state.
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* @drvdata: etm's private data structure.
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* @offset: address of a register, starting from @addr.
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* @position: the position of the bit of interest.
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* @value: the value the bit should have.
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*
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* Basically the same as @coresight_timeout except for the register access
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* method where we have to account for CP14 configurations.
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* Return: 0 as soon as the bit has taken the desired state or -EAGAIN if
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* TIMEOUT_US has elapsed, which ever happens first.
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*/
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static int coresight_timeout_etm(struct etm_drvdata *drvdata, u32 offset,
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int position, int value)
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{
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int i;
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u32 val;
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for (i = TIMEOUT_US; i > 0; i--) {
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val = etm_readl(drvdata, offset);
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/* Waiting on the bit to go from 0 to 1 */
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if (value) {
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if (val & BIT(position))
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return 0;
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/* Waiting on the bit to go from 1 to 0 */
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} else {
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if (!(val & BIT(position)))
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return 0;
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}
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/*
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* Delay is arbitrary - the specification doesn't say how long
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* we are expected to wait. Extra check required to make sure
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* we don't wait needlessly on the last iteration.
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*/
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if (i - 1)
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udelay(1);
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}
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return -EAGAIN;
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}
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static void etm_set_prog(struct etm_drvdata *drvdata)
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{
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u32 etmcr;
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etmcr = etm_readl(drvdata, ETMCR);
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etmcr |= ETMCR_ETM_PRG;
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etm_writel(drvdata, etmcr, ETMCR);
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/*
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* Recommended by spec for cp14 accesses to ensure etmcr write is
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* complete before polling etmsr
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*/
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isb();
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if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 1)) {
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dev_err(drvdata->dev,
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"%s: timeout observed when probing at offset %#x\n",
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__func__, ETMSR);
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}
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}
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static void etm_clr_prog(struct etm_drvdata *drvdata)
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{
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u32 etmcr;
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etmcr = etm_readl(drvdata, ETMCR);
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etmcr &= ~ETMCR_ETM_PRG;
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etm_writel(drvdata, etmcr, ETMCR);
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/*
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* Recommended by spec for cp14 accesses to ensure etmcr write is
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* complete before polling etmsr
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*/
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isb();
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if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 0)) {
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dev_err(drvdata->dev,
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"%s: timeout observed when probing at offset %#x\n",
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__func__, ETMSR);
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}
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}
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void etm_set_default(struct etm_config *config)
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{
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int i;
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if (WARN_ON_ONCE(!config))
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return;
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config->trigger_event = ETM_DEFAULT_EVENT_VAL;
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config->enable_event = ETM_HARD_WIRE_RES_A;
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config->seq_12_event = ETM_DEFAULT_EVENT_VAL;
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config->seq_21_event = ETM_DEFAULT_EVENT_VAL;
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config->seq_23_event = ETM_DEFAULT_EVENT_VAL;
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config->seq_31_event = ETM_DEFAULT_EVENT_VAL;
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config->seq_32_event = ETM_DEFAULT_EVENT_VAL;
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config->seq_13_event = ETM_DEFAULT_EVENT_VAL;
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config->timestamp_event = ETM_DEFAULT_EVENT_VAL;
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for (i = 0; i < ETM_MAX_CNTR; i++) {
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config->cntr_rld_val[i] = 0x0;
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config->cntr_event[i] = ETM_DEFAULT_EVENT_VAL;
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config->cntr_rld_event[i] = ETM_DEFAULT_EVENT_VAL;
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config->cntr_val[i] = 0x0;
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}
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config->seq_curr_state = 0x0;
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config->ctxid_idx = 0x0;
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for (i = 0; i < ETM_MAX_CTXID_CMP; i++) {
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config->ctxid_pid[i] = 0x0;
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config->ctxid_vpid[i] = 0x0;
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}
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config->ctxid_mask = 0x0;
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}
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static void etm_enable_hw(void *info)
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{
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int i;
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u32 etmcr;
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struct etm_drvdata *drvdata = info;
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struct etm_config *config = &drvdata->config;
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CS_UNLOCK(drvdata->base);
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/* Turn engine on */
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etm_clr_pwrdwn(drvdata);
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/* Apply power to trace registers */
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etm_set_pwrup(drvdata);
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/* Make sure all registers are accessible */
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etm_os_unlock(drvdata);
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etm_set_prog(drvdata);
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etmcr = etm_readl(drvdata, ETMCR);
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etmcr &= (ETMCR_PWD_DWN | ETMCR_ETM_PRG);
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etmcr |= drvdata->port_size;
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etm_writel(drvdata, config->ctrl | etmcr, ETMCR);
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etm_writel(drvdata, config->trigger_event, ETMTRIGGER);
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etm_writel(drvdata, config->startstop_ctrl, ETMTSSCR);
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etm_writel(drvdata, config->enable_event, ETMTEEVR);
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etm_writel(drvdata, config->enable_ctrl1, ETMTECR1);
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etm_writel(drvdata, config->fifofull_level, ETMFFLR);
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for (i = 0; i < drvdata->nr_addr_cmp; i++) {
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etm_writel(drvdata, config->addr_val[i], ETMACVRn(i));
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etm_writel(drvdata, config->addr_acctype[i], ETMACTRn(i));
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}
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for (i = 0; i < drvdata->nr_cntr; i++) {
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etm_writel(drvdata, config->cntr_rld_val[i], ETMCNTRLDVRn(i));
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etm_writel(drvdata, config->cntr_event[i], ETMCNTENRn(i));
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etm_writel(drvdata, config->cntr_rld_event[i],
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ETMCNTRLDEVRn(i));
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etm_writel(drvdata, config->cntr_val[i], ETMCNTVRn(i));
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}
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etm_writel(drvdata, config->seq_12_event, ETMSQ12EVR);
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etm_writel(drvdata, config->seq_21_event, ETMSQ21EVR);
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etm_writel(drvdata, config->seq_23_event, ETMSQ23EVR);
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etm_writel(drvdata, config->seq_31_event, ETMSQ31EVR);
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etm_writel(drvdata, config->seq_32_event, ETMSQ32EVR);
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etm_writel(drvdata, config->seq_13_event, ETMSQ13EVR);
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etm_writel(drvdata, config->seq_curr_state, ETMSQR);
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for (i = 0; i < drvdata->nr_ext_out; i++)
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etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i));
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for (i = 0; i < drvdata->nr_ctxid_cmp; i++)
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etm_writel(drvdata, config->ctxid_pid[i], ETMCIDCVRn(i));
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etm_writel(drvdata, config->ctxid_mask, ETMCIDCMR);
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etm_writel(drvdata, config->sync_freq, ETMSYNCFR);
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/* No external input selected */
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etm_writel(drvdata, 0x0, ETMEXTINSELR);
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etm_writel(drvdata, config->timestamp_event, ETMTSEVR);
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/* No auxiliary control selected */
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etm_writel(drvdata, 0x0, ETMAUXCR);
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etm_writel(drvdata, drvdata->traceid, ETMTRACEIDR);
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/* No VMID comparator value selected */
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etm_writel(drvdata, 0x0, ETMVMIDCVR);
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/* Ensures trace output is enabled from this ETM */
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etm_writel(drvdata, config->ctrl | ETMCR_ETM_EN | etmcr, ETMCR);
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etm_clr_prog(drvdata);
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CS_LOCK(drvdata->base);
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dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
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}
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static int etm_cpu_id(struct coresight_device *csdev)
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{
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struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
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return drvdata->cpu;
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}
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int etm_get_trace_id(struct etm_drvdata *drvdata)
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{
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unsigned long flags;
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int trace_id = -1;
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if (!drvdata)
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goto out;
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if (!drvdata->enable)
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return drvdata->traceid;
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pm_runtime_get_sync(drvdata->dev);
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spin_lock_irqsave(&drvdata->spinlock, flags);
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CS_UNLOCK(drvdata->base);
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trace_id = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK);
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CS_LOCK(drvdata->base);
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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pm_runtime_put(drvdata->dev);
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out:
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return trace_id;
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}
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static int etm_trace_id(struct coresight_device *csdev)
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{
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struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
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return etm_get_trace_id(drvdata);
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}
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static int etm_enable(struct coresight_device *csdev)
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{
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struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
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int ret;
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spin_lock(&drvdata->spinlock);
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/*
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* Configure the ETM only if the CPU is online. If it isn't online
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* hw configuration will take place when 'CPU_STARTING' is received
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* in @etm_cpu_callback.
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*/
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if (cpu_online(drvdata->cpu)) {
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ret = smp_call_function_single(drvdata->cpu,
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etm_enable_hw, drvdata, 1);
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if (ret)
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goto err;
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}
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drvdata->enable = true;
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drvdata->sticky_enable = true;
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spin_unlock(&drvdata->spinlock);
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dev_info(drvdata->dev, "ETM tracing enabled\n");
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return 0;
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err:
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spin_unlock(&drvdata->spinlock);
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return ret;
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}
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static void etm_disable_hw(void *info)
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{
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int i;
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struct etm_drvdata *drvdata = info;
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struct etm_config *config = &drvdata->config;
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CS_UNLOCK(drvdata->base);
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etm_set_prog(drvdata);
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/* Program trace enable to low by using always false event */
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etm_writel(drvdata, ETM_HARD_WIRE_RES_A | ETM_EVENT_NOT_A, ETMTEEVR);
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/* Read back sequencer and counters for post trace analysis */
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config->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
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for (i = 0; i < drvdata->nr_cntr; i++)
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config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
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etm_set_pwrdwn(drvdata);
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CS_LOCK(drvdata->base);
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dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
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}
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static void etm_disable(struct coresight_device *csdev)
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{
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struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
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/*
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* Taking hotplug lock here protects from clocks getting disabled
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* with tracing being left on (crash scenario) if user disable occurs
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* after cpu online mask indicates the cpu is offline but before the
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* DYING hotplug callback is serviced by the ETM driver.
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*/
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get_online_cpus();
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spin_lock(&drvdata->spinlock);
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/*
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* Executing etm_disable_hw on the cpu whose ETM is being disabled
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* ensures that register writes occur when cpu is powered.
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*/
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smp_call_function_single(drvdata->cpu, etm_disable_hw, drvdata, 1);
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drvdata->enable = false;
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spin_unlock(&drvdata->spinlock);
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put_online_cpus();
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dev_info(drvdata->dev, "ETM tracing disabled\n");
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}
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static const struct coresight_ops_source etm_source_ops = {
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.cpu_id = etm_cpu_id,
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.trace_id = etm_trace_id,
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.enable = etm_enable,
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.disable = etm_disable,
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};
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static const struct coresight_ops etm_cs_ops = {
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.source_ops = &etm_source_ops,
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};
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static int etm_cpu_callback(struct notifier_block *nfb, unsigned long action,
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void *hcpu)
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{
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unsigned int cpu = (unsigned long)hcpu;
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if (!etmdrvdata[cpu])
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goto out;
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switch (action & (~CPU_TASKS_FROZEN)) {
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case CPU_STARTING:
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spin_lock(&etmdrvdata[cpu]->spinlock);
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if (!etmdrvdata[cpu]->os_unlock) {
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etm_os_unlock(etmdrvdata[cpu]);
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etmdrvdata[cpu]->os_unlock = true;
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}
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if (etmdrvdata[cpu]->enable)
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etm_enable_hw(etmdrvdata[cpu]);
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spin_unlock(&etmdrvdata[cpu]->spinlock);
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break;
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case CPU_ONLINE:
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if (etmdrvdata[cpu]->boot_enable &&
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!etmdrvdata[cpu]->sticky_enable)
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coresight_enable(etmdrvdata[cpu]->csdev);
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break;
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case CPU_DYING:
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spin_lock(&etmdrvdata[cpu]->spinlock);
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if (etmdrvdata[cpu]->enable)
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etm_disable_hw(etmdrvdata[cpu]);
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spin_unlock(&etmdrvdata[cpu]->spinlock);
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break;
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}
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out:
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return NOTIFY_OK;
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}
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static struct notifier_block etm_cpu_notifier = {
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.notifier_call = etm_cpu_callback,
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};
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static bool etm_arch_supported(u8 arch)
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{
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switch (arch) {
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case ETM_ARCH_V3_3:
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break;
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case ETM_ARCH_V3_5:
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break;
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case PFT_ARCH_V1_0:
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break;
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case PFT_ARCH_V1_1:
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break;
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default:
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return false;
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}
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return true;
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}
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static void etm_init_arch_data(void *info)
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{
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u32 etmidr;
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u32 etmccr;
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struct etm_drvdata *drvdata = info;
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|
|
/* Make sure all registers are accessible */
|
|
etm_os_unlock(drvdata);
|
|
|
|
CS_UNLOCK(drvdata->base);
|
|
|
|
/* First dummy read */
|
|
(void)etm_readl(drvdata, ETMPDSR);
|
|
/* Provide power to ETM: ETMPDCR[3] == 1 */
|
|
etm_set_pwrup(drvdata);
|
|
/*
|
|
* Clear power down bit since when this bit is set writes to
|
|
* certain registers might be ignored.
|
|
*/
|
|
etm_clr_pwrdwn(drvdata);
|
|
/*
|
|
* Set prog bit. It will be set from reset but this is included to
|
|
* ensure it is set
|
|
*/
|
|
etm_set_prog(drvdata);
|
|
|
|
/* Find all capabilities */
|
|
etmidr = etm_readl(drvdata, ETMIDR);
|
|
drvdata->arch = BMVAL(etmidr, 4, 11);
|
|
drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
|
|
|
|
drvdata->etmccer = etm_readl(drvdata, ETMCCER);
|
|
etmccr = etm_readl(drvdata, ETMCCR);
|
|
drvdata->etmccr = etmccr;
|
|
drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
|
|
drvdata->nr_cntr = BMVAL(etmccr, 13, 15);
|
|
drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19);
|
|
drvdata->nr_ext_out = BMVAL(etmccr, 20, 22);
|
|
drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
|
|
|
|
etm_set_pwrdwn(drvdata);
|
|
etm_clr_pwrup(drvdata);
|
|
CS_LOCK(drvdata->base);
|
|
}
|
|
|
|
static void etm_init_default_data(struct etm_config *config)
|
|
{
|
|
u32 flags = (1 << 0 | /* instruction execute*/
|
|
3 << 3 | /* ARM instruction */
|
|
0 << 5 | /* No data value comparison */
|
|
0 << 7 | /* No exact mach */
|
|
0 << 8 | /* Ignore context ID */
|
|
0 << 10); /* Security ignored */
|
|
|
|
if (WARN_ON_ONCE(!config))
|
|
return;
|
|
|
|
config->ctrl = (ETMCR_CYC_ACC | ETMCR_TIMESTAMP_EN);
|
|
config->enable_ctrl1 = ETMTECR1_ADDR_COMP_1;
|
|
config->addr_val[0] = (u32) _stext;
|
|
config->addr_val[1] = (u32) _etext;
|
|
config->addr_acctype[0] = flags;
|
|
config->addr_acctype[1] = flags;
|
|
config->addr_type[0] = ETM_ADDR_TYPE_RANGE;
|
|
config->addr_type[1] = ETM_ADDR_TYPE_RANGE;
|
|
|
|
etm_set_default(config);
|
|
}
|
|
|
|
static void etm_init_trace_id(struct etm_drvdata *drvdata)
|
|
{
|
|
/*
|
|
* A trace ID of value 0 is invalid, so let's start at some
|
|
* random value that fits in 7 bits and go from there.
|
|
*/
|
|
drvdata->traceid = 0x10 + drvdata->cpu;
|
|
}
|
|
|
|
static int etm_probe(struct amba_device *adev, const struct amba_id *id)
|
|
{
|
|
int ret;
|
|
void __iomem *base;
|
|
struct device *dev = &adev->dev;
|
|
struct coresight_platform_data *pdata = NULL;
|
|
struct etm_drvdata *drvdata;
|
|
struct resource *res = &adev->res;
|
|
struct coresight_desc *desc;
|
|
struct device_node *np = adev->dev.of_node;
|
|
|
|
desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
|
|
if (!desc)
|
|
return -ENOMEM;
|
|
|
|
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
|
|
if (!drvdata)
|
|
return -ENOMEM;
|
|
|
|
if (np) {
|
|
pdata = of_get_coresight_platform_data(dev, np);
|
|
if (IS_ERR(pdata))
|
|
return PTR_ERR(pdata);
|
|
|
|
adev->dev.platform_data = pdata;
|
|
drvdata->use_cp14 = of_property_read_bool(np, "arm,cp14");
|
|
}
|
|
|
|
drvdata->dev = &adev->dev;
|
|
dev_set_drvdata(dev, drvdata);
|
|
|
|
/* Validity for the resource is already checked by the AMBA core */
|
|
base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
drvdata->base = base;
|
|
|
|
spin_lock_init(&drvdata->spinlock);
|
|
|
|
drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
|
|
if (!IS_ERR(drvdata->atclk)) {
|
|
ret = clk_prepare_enable(drvdata->atclk);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
drvdata->cpu = pdata ? pdata->cpu : 0;
|
|
|
|
get_online_cpus();
|
|
etmdrvdata[drvdata->cpu] = drvdata;
|
|
|
|
if (smp_call_function_single(drvdata->cpu,
|
|
etm_init_arch_data, drvdata, 1))
|
|
dev_err(dev, "ETM arch init failed\n");
|
|
|
|
if (!etm_count++)
|
|
register_hotcpu_notifier(&etm_cpu_notifier);
|
|
|
|
put_online_cpus();
|
|
|
|
if (etm_arch_supported(drvdata->arch) == false) {
|
|
ret = -EINVAL;
|
|
goto err_arch_supported;
|
|
}
|
|
|
|
etm_init_trace_id(drvdata);
|
|
etm_init_default_data(&drvdata->config);
|
|
|
|
desc->type = CORESIGHT_DEV_TYPE_SOURCE;
|
|
desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
|
|
desc->ops = &etm_cs_ops;
|
|
desc->pdata = pdata;
|
|
desc->dev = dev;
|
|
desc->groups = coresight_etm_groups;
|
|
drvdata->csdev = coresight_register(desc);
|
|
if (IS_ERR(drvdata->csdev)) {
|
|
ret = PTR_ERR(drvdata->csdev);
|
|
goto err_arch_supported;
|
|
}
|
|
|
|
pm_runtime_put(&adev->dev);
|
|
dev_info(dev, "%s initialized\n", (char *)id->data);
|
|
|
|
if (boot_enable) {
|
|
coresight_enable(drvdata->csdev);
|
|
drvdata->boot_enable = true;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_arch_supported:
|
|
if (--etm_count == 0)
|
|
unregister_hotcpu_notifier(&etm_cpu_notifier);
|
|
return ret;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int etm_runtime_suspend(struct device *dev)
|
|
{
|
|
struct etm_drvdata *drvdata = dev_get_drvdata(dev);
|
|
|
|
if (drvdata && !IS_ERR(drvdata->atclk))
|
|
clk_disable_unprepare(drvdata->atclk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int etm_runtime_resume(struct device *dev)
|
|
{
|
|
struct etm_drvdata *drvdata = dev_get_drvdata(dev);
|
|
|
|
if (drvdata && !IS_ERR(drvdata->atclk))
|
|
clk_prepare_enable(drvdata->atclk);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static const struct dev_pm_ops etm_dev_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(etm_runtime_suspend, etm_runtime_resume, NULL)
|
|
};
|
|
|
|
static struct amba_id etm_ids[] = {
|
|
{ /* ETM 3.3 */
|
|
.id = 0x0003b921,
|
|
.mask = 0x0003ffff,
|
|
.data = "ETM 3.3",
|
|
},
|
|
{ /* ETM 3.5 */
|
|
.id = 0x0003b956,
|
|
.mask = 0x0003ffff,
|
|
.data = "ETM 3.5",
|
|
},
|
|
{ /* PTM 1.0 */
|
|
.id = 0x0003b950,
|
|
.mask = 0x0003ffff,
|
|
.data = "PTM 1.0",
|
|
},
|
|
{ /* PTM 1.1 */
|
|
.id = 0x0003b95f,
|
|
.mask = 0x0003ffff,
|
|
.data = "PTM 1.1",
|
|
},
|
|
{ /* PTM 1.1 Qualcomm */
|
|
.id = 0x0003006f,
|
|
.mask = 0x0003ffff,
|
|
.data = "PTM 1.1",
|
|
},
|
|
{ 0, 0},
|
|
};
|
|
|
|
static struct amba_driver etm_driver = {
|
|
.drv = {
|
|
.name = "coresight-etm3x",
|
|
.owner = THIS_MODULE,
|
|
.pm = &etm_dev_pm_ops,
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
.probe = etm_probe,
|
|
.id_table = etm_ids,
|
|
};
|
|
|
|
module_amba_driver(etm_driver);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("CoreSight Program Flow Trace driver");
|