mirror of https://gitee.com/openkylin/linux.git
62 lines
1.9 KiB
Plaintext
62 lines
1.9 KiB
Plaintext
Binding for a type of STMicroelectronics clock crossbar (VCC).
|
|
|
|
The crossbar can take up to 4 input clocks and control up to 16
|
|
output clocks. Not all inputs or outputs have to be in use in a
|
|
particular instantiation. Each output can be individually enabled,
|
|
select any of the input clocks and apply a divide (by 1,2,4 or 8) to
|
|
that selected clock.
|
|
|
|
This binding uses the common clock binding[1].
|
|
|
|
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
|
|
|
Required properties:
|
|
|
|
- compatible : shall be:
|
|
"st,stih416-clkgenc", "st,vcc"
|
|
"st,stih416-clkgenf", "st,vcc"
|
|
|
|
- #clock-cells : from common clock binding; shall be set to 1.
|
|
|
|
- reg : A Base address and length of the register set.
|
|
|
|
- clocks : from common clock binding
|
|
|
|
- clock-output-names : From common clock binding. The block has 16
|
|
clock outputs but not all of them in a specific instance
|
|
have to be used in the SoC. If a clock name is left as
|
|
an empty string then no clock will be created for the
|
|
output associated with that string index. If fewer than
|
|
16 strings are provided then no clocks will be created
|
|
for the remaining outputs.
|
|
|
|
Example:
|
|
|
|
clockgen_c_vcc: clockgen-c-vcc@0xfe8308ac {
|
|
#clock-cells = <1>;
|
|
compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
|
|
reg = <0xfe8308ac 12>;
|
|
|
|
clocks = <&clk_s_vcc_hd>,
|
|
<&clockgen_c 1>,
|
|
<&clk_s_tmds_fromphy>,
|
|
<&clockgen_c 2>;
|
|
|
|
clock-output-names = "clk-s-pix-hdmi",
|
|
"clk-s-pix-dvo",
|
|
"clk-s-out-dvo",
|
|
"clk-s-pix-hd",
|
|
"clk-s-hddac",
|
|
"clk-s-denc",
|
|
"clk-s-sddac",
|
|
"clk-s-pix-main",
|
|
"clk-s-pix-aux",
|
|
"clk-s-stfe-frc-0",
|
|
"clk-s-ref-mcru",
|
|
"clk-s-slave-mcru",
|
|
"clk-s-tmds-hdmi",
|
|
"clk-s-hdmi-reject-pll",
|
|
"clk-s-thsens";
|
|
};
|
|
|