mirror of https://gitee.com/openkylin/linux.git
201 lines
6.8 KiB
C
201 lines
6.8 KiB
C
/*
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* arch/sh/kernel/cpu/sh4a/clock-sh7786.c
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*
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* SH7786 support for the clock framework
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*
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* Copyright (C) 2010 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/clkdev.h>
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#include <asm/clock.h>
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#include <asm/freq.h>
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/*
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* Default rate for the root input clock, reset this with clk_set_rate()
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* from the platform code.
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*/
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static struct clk extal_clk = {
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.rate = 33333333,
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};
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static unsigned long pll_recalc(struct clk *clk)
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{
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int multiplier;
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/*
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* Clock modes 0, 1, and 2 use an x64 multiplier against PLL1,
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* while modes 3, 4, and 5 use an x32.
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*/
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multiplier = (sh_mv.mv_mode_pins() & 0xf) < 3 ? 64 : 32;
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return clk->parent->rate * multiplier;
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}
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static struct sh_clk_ops pll_clk_ops = {
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.recalc = pll_recalc,
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};
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static struct clk pll_clk = {
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.ops = &pll_clk_ops,
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.parent = &extal_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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static struct clk *clks[] = {
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&extal_clk,
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&pll_clk,
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};
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static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
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24, 32, 36, 48 };
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static struct clk_div_mult_table div4_div_mult_table = {
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.divisors = div2,
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.nr_divisors = ARRAY_SIZE(div2),
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};
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static struct clk_div4_table div4_table = {
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.div_mult_table = &div4_div_mult_table,
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};
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enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR };
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#define DIV4(_bit, _mask, _flags) \
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SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
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struct clk div4_clks[DIV4_NR] = {
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[DIV4_P] = DIV4(0, 0x0b40, 0),
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[DIV4_DU] = DIV4(4, 0x0010, 0),
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[DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),
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[DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
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[DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
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};
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#define MSTPCR0 0xffc40030
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#define MSTPCR1 0xffc40034
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enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
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MSTP023, MSTP022, MSTP021, MSTP020, MSTP017, MSTP016,
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MSTP015, MSTP014, MSTP011, MSTP010, MSTP009, MSTP008,
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MSTP005, MSTP004, MSTP002,
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MSTP112, MSTP110, MSTP109, MSTP108,
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MSTP105, MSTP104, MSTP103, MSTP102,
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MSTP_NR };
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static struct clk mstp_clks[MSTP_NR] = {
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/* MSTPCR0 */
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[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
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[MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
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[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
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[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
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[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
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[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
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[MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
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[MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
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[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
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[MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
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[MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
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[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
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[MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
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[MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
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[MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
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[MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
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[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
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[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
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[MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
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[MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
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[MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
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/* MSTPCR1 */
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[MSTP112] = SH_CLK_MSTP32(NULL, MSTPCR1, 12, 0),
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[MSTP110] = SH_CLK_MSTP32(NULL, MSTPCR1, 10, 0),
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[MSTP109] = SH_CLK_MSTP32(NULL, MSTPCR1, 9, 0),
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[MSTP108] = SH_CLK_MSTP32(NULL, MSTPCR1, 8, 0),
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[MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
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[MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
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[MSTP103] = SH_CLK_MSTP32(NULL, MSTPCR1, 3, 0),
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[MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0),
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};
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static struct clk_lookup lookups[] = {
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/* main clocks */
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CLKDEV_CON_ID("extal", &extal_clk),
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CLKDEV_CON_ID("pll_clk", &pll_clk),
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/* DIV4 clocks */
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CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
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CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
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CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
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CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
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CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
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CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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/* MSTP32 clocks */
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CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP029]),
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CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP028]),
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CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP027]),
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CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP026]),
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CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP025]),
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CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP024]),
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CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]),
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CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]),
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CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
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CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
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CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
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CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
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CLKDEV_CON_ID("i2c1_fck", &mstp_clks[MSTP015]),
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CLKDEV_CON_ID("i2c0_fck", &mstp_clks[MSTP014]),
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CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[MSTP008]),
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CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[MSTP008]),
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CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[MSTP008]),
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CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[MSTP009]),
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CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[MSTP009]),
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CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[MSTP009]),
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CLKDEV_ICK_ID("tmu_fck", "sh_tmu.6", &mstp_clks[MSTP010]),
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CLKDEV_ICK_ID("tmu_fck", "sh_tmu.7", &mstp_clks[MSTP010]),
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CLKDEV_ICK_ID("tmu_fck", "sh_tmu.8", &mstp_clks[MSTP010]),
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CLKDEV_ICK_ID("tmu_fck", "sh_tmu.9", &mstp_clks[MSTP011]),
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CLKDEV_ICK_ID("tmu_fck", "sh_tmu.10", &mstp_clks[MSTP011]),
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CLKDEV_ICK_ID("tmu_fck", "sh_tmu.11", &mstp_clks[MSTP011]),
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CLKDEV_CON_ID("sdif1_fck", &mstp_clks[MSTP005]),
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CLKDEV_CON_ID("sdif0_fck", &mstp_clks[MSTP004]),
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CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
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CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP112]),
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CLKDEV_CON_ID("pcie2_fck", &mstp_clks[MSTP110]),
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CLKDEV_CON_ID("pcie1_fck", &mstp_clks[MSTP109]),
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CLKDEV_CON_ID("pcie0_fck", &mstp_clks[MSTP108]),
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CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
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CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
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CLKDEV_CON_ID("du_fck", &mstp_clks[MSTP103]),
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CLKDEV_CON_ID("ether_fck", &mstp_clks[MSTP102]),
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};
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int __init arch_clk_init(void)
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{
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int i, ret = 0;
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for (i = 0; i < ARRAY_SIZE(clks); i++)
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ret |= clk_register(clks[i]);
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for (i = 0; i < ARRAY_SIZE(lookups); i++)
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clkdev_add(&lookups[i]);
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if (!ret)
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ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
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&div4_table);
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if (!ret)
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ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
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return ret;
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}
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