mirror of https://gitee.com/openkylin/linux.git
303 lines
7.4 KiB
C
303 lines
7.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* motu-protocol-v2.c - a part of driver for MOTU FireWire series
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*
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* Copyright (c) 2015-2017 Takashi Sakamoto <o-takashi@sakamocchi.jp>
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*/
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#include "motu.h"
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#define V2_CLOCK_STATUS_OFFSET 0x0b14
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#define V2_CLOCK_RATE_MASK 0x00000038
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#define V2_CLOCK_RATE_SHIFT 3
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#define V2_CLOCK_SRC_MASK 0x00000007
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#define V2_CLOCK_SRC_SHIFT 0
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#define V2_CLOCK_FETCH_ENABLE 0x02000000
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#define V2_CLOCK_MODEL_SPECIFIC 0x04000000
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#define V2_IN_OUT_CONF_OFFSET 0x0c04
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#define V2_OPT_OUT_IFACE_MASK 0x00000c00
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#define V2_OPT_OUT_IFACE_SHIFT 10
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#define V2_OPT_IN_IFACE_MASK 0x00000300
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#define V2_OPT_IN_IFACE_SHIFT 8
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#define V2_OPT_IFACE_MODE_NONE 0
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#define V2_OPT_IFACE_MODE_ADAT 1
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#define V2_OPT_IFACE_MODE_SPDIF 2
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static int get_clock_rate(u32 data, unsigned int *rate)
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{
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unsigned int index = (data & V2_CLOCK_RATE_MASK) >> V2_CLOCK_RATE_SHIFT;
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if (index >= ARRAY_SIZE(snd_motu_clock_rates))
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return -EIO;
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*rate = snd_motu_clock_rates[index];
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return 0;
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}
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static int v2_get_clock_rate(struct snd_motu *motu, unsigned int *rate)
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{
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__be32 reg;
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int err;
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err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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return get_clock_rate(be32_to_cpu(reg), rate);
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}
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static int v2_set_clock_rate(struct snd_motu *motu, unsigned int rate)
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{
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__be32 reg;
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u32 data;
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int i;
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int err;
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for (i = 0; i < ARRAY_SIZE(snd_motu_clock_rates); ++i) {
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if (snd_motu_clock_rates[i] == rate)
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break;
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}
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if (i == ARRAY_SIZE(snd_motu_clock_rates))
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return -EINVAL;
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err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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data = be32_to_cpu(reg);
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data &= ~V2_CLOCK_RATE_MASK;
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data |= i << V2_CLOCK_RATE_SHIFT;
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reg = cpu_to_be32(data);
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return snd_motu_transaction_write(motu, V2_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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}
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static int get_clock_source(struct snd_motu *motu, u32 data,
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enum snd_motu_clock_source *src)
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{
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unsigned int index = data & V2_CLOCK_SRC_MASK;
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if (index > 5)
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return -EIO;
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switch (index) {
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case 0:
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*src = SND_MOTU_CLOCK_SOURCE_INTERNAL;
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break;
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case 1:
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{
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__be32 reg;
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// To check the configuration of optical interface.
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int err = snd_motu_transaction_read(motu, V2_IN_OUT_CONF_OFFSET,
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®, sizeof(reg));
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if (err < 0)
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return err;
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if (be32_to_cpu(reg) & 0x00000200)
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*src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_OPT;
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else
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*src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT;
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break;
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}
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case 2:
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*src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_COAX;
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break;
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case 3:
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*src = SND_MOTU_CLOCK_SOURCE_SPH;
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break;
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case 4:
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*src = SND_MOTU_CLOCK_SOURCE_WORD_ON_BNC;
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break;
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case 5:
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*src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_DSUB;
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break;
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default:
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return -EIO;
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}
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return 0;
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}
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static int v2_get_clock_source(struct snd_motu *motu,
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enum snd_motu_clock_source *src)
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{
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__be32 reg;
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int err;
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err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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return get_clock_source(motu, be32_to_cpu(reg), src);
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}
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static int v2_switch_fetching_mode(struct snd_motu *motu, bool enable)
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{
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enum snd_motu_clock_source src;
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__be32 reg;
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u32 data;
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int err = 0;
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// 828mkII implements Altera ACEX 1K EP1K30. Nothing to do.
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if (motu->spec == &snd_motu_spec_828mk2)
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return 0;
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err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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data = be32_to_cpu(reg);
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err = get_clock_source(motu, data, &src);
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if (err < 0)
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return err;
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data &= ~(V2_CLOCK_FETCH_ENABLE | V2_CLOCK_MODEL_SPECIFIC);
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if (enable)
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data |= V2_CLOCK_FETCH_ENABLE;
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if (motu->spec->flags & SND_MOTU_SPEC_SUPPORT_CLOCK_X4) {
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// Expected for Traveler and 896HD, which implements Altera
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// Cyclone EP1C3.
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data |= V2_CLOCK_MODEL_SPECIFIC;
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} else {
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// For UltraLite and 8pre, which implements Xilinx Spartan
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// XC3S200.
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unsigned int rate;
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err = get_clock_rate(data, &rate);
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if (err < 0)
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return err;
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if (src == SND_MOTU_CLOCK_SOURCE_SPH && rate > 48000)
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data |= V2_CLOCK_MODEL_SPECIFIC;
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}
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reg = cpu_to_be32(data);
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return snd_motu_transaction_write(motu, V2_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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}
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static void calculate_fixed_part(struct snd_motu_packet_format *formats,
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enum amdtp_stream_direction dir,
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enum snd_motu_spec_flags flags,
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unsigned char analog_ports)
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{
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unsigned char pcm_chunks[3] = {0, 0, 0};
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formats->msg_chunks = 2;
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pcm_chunks[0] = analog_ports;
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pcm_chunks[1] = analog_ports;
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if (flags & SND_MOTU_SPEC_SUPPORT_CLOCK_X4)
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pcm_chunks[2] = analog_ports;
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if (dir == AMDTP_IN_STREAM) {
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if (flags & SND_MOTU_SPEC_TX_MICINST_CHUNK) {
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pcm_chunks[0] += 2;
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pcm_chunks[1] += 2;
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}
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if (flags & SND_MOTU_SPEC_TX_RETURN_CHUNK) {
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pcm_chunks[0] += 2;
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pcm_chunks[1] += 2;
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}
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} else {
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if (flags & SND_MOTU_SPEC_RX_SEPARATED_MAIN) {
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pcm_chunks[0] += 2;
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pcm_chunks[1] += 2;
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}
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// Packets to v2 units include 2 chunks for phone 1/2, except
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// for 176.4/192.0 kHz.
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pcm_chunks[0] += 2;
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pcm_chunks[1] += 2;
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}
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if (flags & SND_MOTU_SPEC_HAS_AESEBU_IFACE) {
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pcm_chunks[0] += 2;
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pcm_chunks[1] += 2;
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}
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/*
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* All of v2 models have a pair of coaxial interfaces for digital in/out
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* port. At 44.1/48.0/88.2/96.0 kHz, packets includes PCM from these
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* ports.
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*/
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pcm_chunks[0] += 2;
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pcm_chunks[1] += 2;
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formats->fixed_part_pcm_chunks[0] = pcm_chunks[0];
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formats->fixed_part_pcm_chunks[1] = pcm_chunks[1];
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formats->fixed_part_pcm_chunks[2] = pcm_chunks[2];
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}
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static void calculate_differed_part(struct snd_motu_packet_format *formats,
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enum snd_motu_spec_flags flags,
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u32 data, u32 mask, u32 shift)
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{
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unsigned char pcm_chunks[2] = {0, 0};
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/*
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* When optical interfaces are configured for S/PDIF (TOSLINK),
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* the above PCM frames come from them, instead of coaxial
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* interfaces.
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*/
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data = (data & mask) >> shift;
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if (data == V2_OPT_IFACE_MODE_ADAT) {
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if (flags & SND_MOTU_SPEC_HAS_OPT_IFACE_A) {
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pcm_chunks[0] += 8;
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pcm_chunks[1] += 4;
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}
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// 8pre has two sets of optical interface and doesn't reduce
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// chunks for ADAT signals.
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if (flags & SND_MOTU_SPEC_HAS_OPT_IFACE_B) {
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pcm_chunks[1] += 4;
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}
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}
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/* At mode x4, no data chunks are supported in this part. */
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formats->differed_part_pcm_chunks[0] = pcm_chunks[0];
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formats->differed_part_pcm_chunks[1] = pcm_chunks[1];
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}
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static int v2_cache_packet_formats(struct snd_motu *motu)
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{
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__be32 reg;
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u32 data;
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int err;
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err = snd_motu_transaction_read(motu, V2_IN_OUT_CONF_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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data = be32_to_cpu(reg);
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calculate_fixed_part(&motu->tx_packet_formats, AMDTP_IN_STREAM,
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motu->spec->flags, motu->spec->analog_in_ports);
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calculate_differed_part(&motu->tx_packet_formats, motu->spec->flags,
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data, V2_OPT_IN_IFACE_MASK, V2_OPT_IN_IFACE_SHIFT);
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calculate_fixed_part(&motu->rx_packet_formats, AMDTP_OUT_STREAM,
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motu->spec->flags, motu->spec->analog_out_ports);
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calculate_differed_part(&motu->rx_packet_formats, motu->spec->flags,
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data, V2_OPT_OUT_IFACE_MASK, V2_OPT_OUT_IFACE_SHIFT);
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motu->tx_packet_formats.pcm_byte_offset = 10;
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motu->rx_packet_formats.pcm_byte_offset = 10;
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return 0;
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}
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const struct snd_motu_protocol snd_motu_protocol_v2 = {
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.get_clock_rate = v2_get_clock_rate,
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.set_clock_rate = v2_set_clock_rate,
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.get_clock_source = v2_get_clock_source,
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.switch_fetching_mode = v2_switch_fetching_mode,
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.cache_packet_formats = v2_cache_packet_formats,
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};
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