mirror of https://gitee.com/openkylin/linux.git
210 lines
5.8 KiB
C
210 lines
5.8 KiB
C
/*
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* Copyright (c) 2010 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "hw.h"
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#include "hw-ops.h"
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#include "ar9003_phy.h"
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static void ar9003_hw_setup_calibration(struct ath_hw *ah,
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struct ath9k_cal_list *currCal)
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{
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/* TODO */
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}
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static bool ar9003_hw_calibrate(struct ath_hw *ah,
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struct ath9k_channel *chan,
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u8 rxchainmask,
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bool longcal)
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{
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/* TODO */
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return false;
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}
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static bool ar9003_hw_init_cal(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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/* TODO */
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return false;
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}
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static void ar9003_hw_iqcal_collect(struct ath_hw *ah)
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{
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int i;
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/* Accumulate IQ cal measures for active chains */
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for (i = 0; i < AR5416_MAX_CHAINS; i++) {
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ah->totalPowerMeasI[i] +=
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REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
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ah->totalPowerMeasQ[i] +=
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REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
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ah->totalIqCorrMeas[i] +=
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(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
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ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
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"%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
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ah->cal_samples, i, ah->totalPowerMeasI[i],
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ah->totalPowerMeasQ[i],
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ah->totalIqCorrMeas[i]);
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}
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}
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static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
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{
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struct ath_common *common = ath9k_hw_common(ah);
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u32 powerMeasQ, powerMeasI, iqCorrMeas;
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u32 qCoffDenom, iCoffDenom;
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int32_t qCoff, iCoff;
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int iqCorrNeg, i;
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const u_int32_t offset_array[3] = {
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AR_PHY_RX_IQCAL_CORR_B0,
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AR_PHY_RX_IQCAL_CORR_B1,
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AR_PHY_RX_IQCAL_CORR_B2,
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};
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for (i = 0; i < numChains; i++) {
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powerMeasI = ah->totalPowerMeasI[i];
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powerMeasQ = ah->totalPowerMeasQ[i];
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iqCorrMeas = ah->totalIqCorrMeas[i];
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ath_print(common, ATH_DBG_CALIBRATE,
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"Starting IQ Cal and Correction for Chain %d\n",
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i);
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ath_print(common, ATH_DBG_CALIBRATE,
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"Orignal: Chn %diq_corr_meas = 0x%08x\n",
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i, ah->totalIqCorrMeas[i]);
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iqCorrNeg = 0;
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if (iqCorrMeas > 0x80000000) {
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iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
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iqCorrNeg = 1;
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}
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ath_print(common, ATH_DBG_CALIBRATE,
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"Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
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ath_print(common, ATH_DBG_CALIBRATE,
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"Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
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ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
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iqCorrNeg);
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iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 256;
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qCoffDenom = powerMeasQ / 64;
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if ((iCoffDenom != 0) && (qCoffDenom != 0)) {
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iCoff = iqCorrMeas / iCoffDenom;
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qCoff = powerMeasI / qCoffDenom - 64;
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ath_print(common, ATH_DBG_CALIBRATE,
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"Chn %d iCoff = 0x%08x\n", i, iCoff);
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ath_print(common, ATH_DBG_CALIBRATE,
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"Chn %d qCoff = 0x%08x\n", i, qCoff);
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/* Force bounds on iCoff */
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if (iCoff >= 63)
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iCoff = 63;
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else if (iCoff <= -63)
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iCoff = -63;
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/* Negate iCoff if iqCorrNeg == 0 */
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if (iqCorrNeg == 0x0)
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iCoff = -iCoff;
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/* Force bounds on qCoff */
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if (qCoff >= 63)
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qCoff = 63;
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else if (qCoff <= -63)
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qCoff = -63;
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iCoff = iCoff & 0x7f;
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qCoff = qCoff & 0x7f;
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ath_print(common, ATH_DBG_CALIBRATE,
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"Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
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i, iCoff, qCoff);
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ath_print(common, ATH_DBG_CALIBRATE,
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"Register offset (0x%04x) "
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"before update = 0x%x\n",
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offset_array[i],
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REG_READ(ah, offset_array[i]));
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REG_RMW_FIELD(ah, offset_array[i],
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AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
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iCoff);
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REG_RMW_FIELD(ah, offset_array[i],
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AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
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qCoff);
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ath_print(common, ATH_DBG_CALIBRATE,
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"Register offset (0x%04x) QI COFF "
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"(bitfields 0x%08x) after update = 0x%x\n",
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offset_array[i],
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AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
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REG_READ(ah, offset_array[i]));
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ath_print(common, ATH_DBG_CALIBRATE,
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"Register offset (0x%04x) QQ COFF "
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"(bitfields 0x%08x) after update = 0x%x\n",
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offset_array[i],
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AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
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REG_READ(ah, offset_array[i]));
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ath_print(common, ATH_DBG_CALIBRATE,
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"IQ Cal and Correction done for Chain %d\n",
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i);
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}
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}
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REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0,
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AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE);
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ath_print(common, ATH_DBG_CALIBRATE,
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"IQ Cal and Correction (offset 0x%04x) enabled "
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"(bit position 0x%08x). New Value 0x%08x\n",
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(unsigned) (AR_PHY_RX_IQCAL_CORR_B0),
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AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE,
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REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
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}
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static const struct ath9k_percal_data iq_cal_single_sample = {
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IQ_MISMATCH_CAL,
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MIN_CAL_SAMPLES,
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PER_MAX_LOG_COUNT,
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ar9003_hw_iqcal_collect,
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ar9003_hw_iqcalibrate
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};
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static void ar9003_hw_init_cal_settings(struct ath_hw *ah)
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{
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ah->iq_caldata.calData = &iq_cal_single_sample;
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ah->supp_cals = IQ_MISMATCH_CAL;
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}
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static bool ar9003_hw_iscal_supported(struct ath_hw *ah,
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enum ath9k_cal_types calType)
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{
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/* TODO */
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return false;
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}
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void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
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{
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struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
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struct ath_hw_ops *ops = ath9k_hw_ops(ah);
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priv_ops->init_cal_settings = ar9003_hw_init_cal_settings;
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priv_ops->init_cal = ar9003_hw_init_cal;
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priv_ops->setup_calibration = ar9003_hw_setup_calibration;
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priv_ops->iscal_supported = ar9003_hw_iscal_supported;
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ops->calibrate = ar9003_hw_calibrate;
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}
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