mirror of https://gitee.com/openkylin/linux.git
672 lines
18 KiB
C
672 lines
18 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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// Copyright (c) 2017 Synopsys, Inc. and/or its affiliates.
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// stmmac Support for 5.xx Ethernet QoS cores
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#include <linux/bitops.h>
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#include <linux/iopoll.h>
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#include "common.h"
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#include "dwmac4.h"
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#include "dwmac5.h"
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#include "stmmac.h"
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#include "stmmac_ptp.h"
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struct dwmac5_error_desc {
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bool valid;
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const char *desc;
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const char *detailed_desc;
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};
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#define STAT_OFF(field) offsetof(struct stmmac_safety_stats, field)
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static void dwmac5_log_error(struct net_device *ndev, u32 value, bool corr,
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const char *module_name, const struct dwmac5_error_desc *desc,
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unsigned long field_offset, struct stmmac_safety_stats *stats)
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{
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unsigned long loc, mask;
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u8 *bptr = (u8 *)stats;
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unsigned long *ptr;
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ptr = (unsigned long *)(bptr + field_offset);
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mask = value;
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for_each_set_bit(loc, &mask, 32) {
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netdev_err(ndev, "Found %s error in %s: '%s: %s'\n", corr ?
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"correctable" : "uncorrectable", module_name,
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desc[loc].desc, desc[loc].detailed_desc);
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/* Update counters */
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ptr[loc]++;
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}
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}
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static const struct dwmac5_error_desc dwmac5_mac_errors[32]= {
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{ true, "ATPES", "Application Transmit Interface Parity Check Error" },
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{ true, "TPES", "TSO Data Path Parity Check Error" },
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{ true, "RDPES", "Read Descriptor Parity Check Error" },
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{ true, "MPES", "MTL Data Path Parity Check Error" },
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{ true, "MTSPES", "MTL TX Status Data Path Parity Check Error" },
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{ true, "ARPES", "Application Receive Interface Data Path Parity Check Error" },
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{ true, "CWPES", "CSR Write Data Path Parity Check Error" },
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{ true, "ASRPES", "AXI Slave Read Data Path Parity Check Error" },
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{ true, "TTES", "TX FSM Timeout Error" },
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{ true, "RTES", "RX FSM Timeout Error" },
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{ true, "CTES", "CSR FSM Timeout Error" },
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{ true, "ATES", "APP FSM Timeout Error" },
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{ true, "PTES", "PTP FSM Timeout Error" },
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{ true, "T125ES", "TX125 FSM Timeout Error" },
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{ true, "R125ES", "RX125 FSM Timeout Error" },
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{ true, "RVCTES", "REV MDC FSM Timeout Error" },
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{ true, "MSTTES", "Master Read/Write Timeout Error" },
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{ true, "SLVTES", "Slave Read/Write Timeout Error" },
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{ true, "ATITES", "Application Timeout on ATI Interface Error" },
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{ true, "ARITES", "Application Timeout on ARI Interface Error" },
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{ false, "UNKNOWN", "Unknown Error" }, /* 20 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 21 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 22 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 23 */
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{ true, "FSMPES", "FSM State Parity Error" },
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{ false, "UNKNOWN", "Unknown Error" }, /* 25 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 26 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 27 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 28 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 29 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 30 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 31 */
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};
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static void dwmac5_handle_mac_err(struct net_device *ndev,
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void __iomem *ioaddr, bool correctable,
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struct stmmac_safety_stats *stats)
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{
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u32 value;
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value = readl(ioaddr + MAC_DPP_FSM_INT_STATUS);
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writel(value, ioaddr + MAC_DPP_FSM_INT_STATUS);
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dwmac5_log_error(ndev, value, correctable, "MAC", dwmac5_mac_errors,
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STAT_OFF(mac_errors), stats);
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}
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static const struct dwmac5_error_desc dwmac5_mtl_errors[32]= {
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{ true, "TXCES", "MTL TX Memory Error" },
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{ true, "TXAMS", "MTL TX Memory Address Mismatch Error" },
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{ true, "TXUES", "MTL TX Memory Error" },
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{ false, "UNKNOWN", "Unknown Error" }, /* 3 */
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{ true, "RXCES", "MTL RX Memory Error" },
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{ true, "RXAMS", "MTL RX Memory Address Mismatch Error" },
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{ true, "RXUES", "MTL RX Memory Error" },
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{ false, "UNKNOWN", "Unknown Error" }, /* 7 */
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{ true, "ECES", "MTL EST Memory Error" },
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{ true, "EAMS", "MTL EST Memory Address Mismatch Error" },
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{ true, "EUES", "MTL EST Memory Error" },
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{ false, "UNKNOWN", "Unknown Error" }, /* 11 */
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{ true, "RPCES", "MTL RX Parser Memory Error" },
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{ true, "RPAMS", "MTL RX Parser Memory Address Mismatch Error" },
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{ true, "RPUES", "MTL RX Parser Memory Error" },
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{ false, "UNKNOWN", "Unknown Error" }, /* 15 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 16 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 17 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 18 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 19 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 20 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 21 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 22 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 23 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 24 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 25 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 26 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 27 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 28 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 29 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 30 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 31 */
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};
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static void dwmac5_handle_mtl_err(struct net_device *ndev,
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void __iomem *ioaddr, bool correctable,
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struct stmmac_safety_stats *stats)
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{
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u32 value;
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value = readl(ioaddr + MTL_ECC_INT_STATUS);
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writel(value, ioaddr + MTL_ECC_INT_STATUS);
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dwmac5_log_error(ndev, value, correctable, "MTL", dwmac5_mtl_errors,
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STAT_OFF(mtl_errors), stats);
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}
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static const struct dwmac5_error_desc dwmac5_dma_errors[32]= {
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{ true, "TCES", "DMA TSO Memory Error" },
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{ true, "TAMS", "DMA TSO Memory Address Mismatch Error" },
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{ true, "TUES", "DMA TSO Memory Error" },
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{ false, "UNKNOWN", "Unknown Error" }, /* 3 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 4 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 5 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 6 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 7 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 8 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 9 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 10 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 11 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 12 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 13 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 14 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 15 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 16 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 17 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 18 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 19 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 20 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 21 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 22 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 23 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 24 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 25 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 26 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 27 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 28 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 29 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 30 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 31 */
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};
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static void dwmac5_handle_dma_err(struct net_device *ndev,
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void __iomem *ioaddr, bool correctable,
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struct stmmac_safety_stats *stats)
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{
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u32 value;
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value = readl(ioaddr + DMA_ECC_INT_STATUS);
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writel(value, ioaddr + DMA_ECC_INT_STATUS);
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dwmac5_log_error(ndev, value, correctable, "DMA", dwmac5_dma_errors,
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STAT_OFF(dma_errors), stats);
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}
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int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigned int asp)
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{
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u32 value;
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if (!asp)
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return -EINVAL;
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/* 1. Enable Safety Features */
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value = readl(ioaddr + MTL_ECC_CONTROL);
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value |= TSOEE; /* TSO ECC */
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value |= MRXPEE; /* MTL RX Parser ECC */
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value |= MESTEE; /* MTL EST ECC */
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value |= MRXEE; /* MTL RX FIFO ECC */
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value |= MTXEE; /* MTL TX FIFO ECC */
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writel(value, ioaddr + MTL_ECC_CONTROL);
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/* 2. Enable MTL Safety Interrupts */
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value = readl(ioaddr + MTL_ECC_INT_ENABLE);
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value |= RPCEIE; /* RX Parser Memory Correctable Error */
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value |= ECEIE; /* EST Memory Correctable Error */
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value |= RXCEIE; /* RX Memory Correctable Error */
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value |= TXCEIE; /* TX Memory Correctable Error */
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writel(value, ioaddr + MTL_ECC_INT_ENABLE);
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/* 3. Enable DMA Safety Interrupts */
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value = readl(ioaddr + DMA_ECC_INT_ENABLE);
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value |= TCEIE; /* TSO Memory Correctable Error */
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writel(value, ioaddr + DMA_ECC_INT_ENABLE);
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/* Only ECC Protection for External Memory feature is selected */
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if (asp <= 0x1)
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return 0;
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/* 5. Enable Parity and Timeout for FSM */
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value = readl(ioaddr + MAC_FSM_CONTROL);
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value |= PRTYEN; /* FSM Parity Feature */
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value |= TMOUTEN; /* FSM Timeout Feature */
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writel(value, ioaddr + MAC_FSM_CONTROL);
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/* 4. Enable Data Parity Protection */
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value = readl(ioaddr + MTL_DPP_CONTROL);
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value |= EDPP;
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writel(value, ioaddr + MTL_DPP_CONTROL);
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/*
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* All the Automotive Safety features are selected without the "Parity
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* Port Enable for external interface" feature.
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*/
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if (asp <= 0x2)
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return 0;
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value |= EPSI;
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writel(value, ioaddr + MTL_DPP_CONTROL);
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return 0;
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}
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int dwmac5_safety_feat_irq_status(struct net_device *ndev,
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void __iomem *ioaddr, unsigned int asp,
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struct stmmac_safety_stats *stats)
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{
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bool err, corr;
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u32 mtl, dma;
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int ret = 0;
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if (!asp)
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return -EINVAL;
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mtl = readl(ioaddr + MTL_SAFETY_INT_STATUS);
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dma = readl(ioaddr + DMA_SAFETY_INT_STATUS);
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err = (mtl & MCSIS) || (dma & MCSIS);
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corr = false;
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if (err) {
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dwmac5_handle_mac_err(ndev, ioaddr, corr, stats);
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ret |= !corr;
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}
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err = (mtl & (MEUIS | MECIS)) || (dma & (MSUIS | MSCIS));
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corr = (mtl & MECIS) || (dma & MSCIS);
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if (err) {
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dwmac5_handle_mtl_err(ndev, ioaddr, corr, stats);
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ret |= !corr;
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}
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err = dma & (DEUIS | DECIS);
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corr = dma & DECIS;
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if (err) {
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dwmac5_handle_dma_err(ndev, ioaddr, corr, stats);
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ret |= !corr;
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}
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return ret;
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}
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static const struct dwmac5_error {
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const struct dwmac5_error_desc *desc;
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} dwmac5_all_errors[] = {
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{ dwmac5_mac_errors },
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{ dwmac5_mtl_errors },
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{ dwmac5_dma_errors },
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};
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int dwmac5_safety_feat_dump(struct stmmac_safety_stats *stats,
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int index, unsigned long *count, const char **desc)
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{
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int module = index / 32, offset = index % 32;
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unsigned long *ptr = (unsigned long *)stats;
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if (module >= ARRAY_SIZE(dwmac5_all_errors))
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return -EINVAL;
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if (!dwmac5_all_errors[module].desc[offset].valid)
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return -EINVAL;
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if (count)
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*count = *(ptr + index);
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if (desc)
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*desc = dwmac5_all_errors[module].desc[offset].desc;
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return 0;
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}
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static int dwmac5_rxp_disable(void __iomem *ioaddr)
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{
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u32 val;
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int ret;
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val = readl(ioaddr + MTL_OPERATION_MODE);
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val &= ~MTL_FRPE;
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writel(val, ioaddr + MTL_OPERATION_MODE);
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ret = readl_poll_timeout(ioaddr + MTL_RXP_CONTROL_STATUS, val,
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val & RXPI, 1, 10000);
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if (ret)
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return ret;
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return 0;
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}
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static void dwmac5_rxp_enable(void __iomem *ioaddr)
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{
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u32 val;
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val = readl(ioaddr + MTL_OPERATION_MODE);
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val |= MTL_FRPE;
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writel(val, ioaddr + MTL_OPERATION_MODE);
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}
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static int dwmac5_rxp_update_single_entry(void __iomem *ioaddr,
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struct stmmac_tc_entry *entry,
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int pos)
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{
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int ret, i;
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for (i = 0; i < (sizeof(entry->val) / sizeof(u32)); i++) {
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int real_pos = pos * (sizeof(entry->val) / sizeof(u32)) + i;
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u32 val;
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/* Wait for ready */
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ret = readl_poll_timeout(ioaddr + MTL_RXP_IACC_CTRL_STATUS,
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val, !(val & STARTBUSY), 1, 10000);
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if (ret)
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return ret;
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/* Write data */
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val = *((u32 *)&entry->val + i);
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writel(val, ioaddr + MTL_RXP_IACC_DATA);
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/* Write pos */
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val = real_pos & ADDR;
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writel(val, ioaddr + MTL_RXP_IACC_CTRL_STATUS);
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/* Write OP */
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val |= WRRDN;
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writel(val, ioaddr + MTL_RXP_IACC_CTRL_STATUS);
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/* Start Write */
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val |= STARTBUSY;
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writel(val, ioaddr + MTL_RXP_IACC_CTRL_STATUS);
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/* Wait for done */
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ret = readl_poll_timeout(ioaddr + MTL_RXP_IACC_CTRL_STATUS,
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val, !(val & STARTBUSY), 1, 10000);
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if (ret)
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return ret;
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}
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return 0;
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}
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static struct stmmac_tc_entry *
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dwmac5_rxp_get_next_entry(struct stmmac_tc_entry *entries, unsigned int count,
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u32 curr_prio)
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{
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struct stmmac_tc_entry *entry;
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u32 min_prio = ~0x0;
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int i, min_prio_idx;
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bool found = false;
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for (i = count - 1; i >= 0; i--) {
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entry = &entries[i];
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/* Do not update unused entries */
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if (!entry->in_use)
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continue;
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/* Do not update already updated entries (i.e. fragments) */
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if (entry->in_hw)
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continue;
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/* Let last entry be updated last */
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if (entry->is_last)
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continue;
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/* Do not return fragments */
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if (entry->is_frag)
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continue;
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/* Check if we already checked this prio */
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if (entry->prio < curr_prio)
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continue;
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/* Check if this is the minimum prio */
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if (entry->prio < min_prio) {
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min_prio = entry->prio;
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min_prio_idx = i;
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found = true;
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}
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}
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if (found)
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return &entries[min_prio_idx];
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return NULL;
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}
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int dwmac5_rxp_config(void __iomem *ioaddr, struct stmmac_tc_entry *entries,
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unsigned int count)
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{
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struct stmmac_tc_entry *entry, *frag;
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int i, ret, nve = 0;
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u32 curr_prio = 0;
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u32 old_val, val;
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/* Force disable RX */
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old_val = readl(ioaddr + GMAC_CONFIG);
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val = old_val & ~GMAC_CONFIG_RE;
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writel(val, ioaddr + GMAC_CONFIG);
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/* Disable RX Parser */
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ret = dwmac5_rxp_disable(ioaddr);
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if (ret)
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goto re_enable;
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/* Set all entries as NOT in HW */
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for (i = 0; i < count; i++) {
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entry = &entries[i];
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entry->in_hw = false;
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}
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/* Update entries by reverse order */
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while (1) {
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entry = dwmac5_rxp_get_next_entry(entries, count, curr_prio);
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if (!entry)
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break;
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curr_prio = entry->prio;
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frag = entry->frag_ptr;
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/* Set special fragment requirements */
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if (frag) {
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entry->val.af = 0;
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entry->val.rf = 0;
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entry->val.nc = 1;
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entry->val.ok_index = nve + 2;
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}
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ret = dwmac5_rxp_update_single_entry(ioaddr, entry, nve);
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if (ret)
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goto re_enable;
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entry->table_pos = nve++;
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entry->in_hw = true;
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if (frag && !frag->in_hw) {
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ret = dwmac5_rxp_update_single_entry(ioaddr, frag, nve);
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if (ret)
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goto re_enable;
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frag->table_pos = nve++;
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frag->in_hw = true;
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}
|
|
}
|
|
|
|
if (!nve)
|
|
goto re_enable;
|
|
|
|
/* Update all pass entry */
|
|
for (i = 0; i < count; i++) {
|
|
entry = &entries[i];
|
|
if (!entry->is_last)
|
|
continue;
|
|
|
|
ret = dwmac5_rxp_update_single_entry(ioaddr, entry, nve);
|
|
if (ret)
|
|
goto re_enable;
|
|
|
|
entry->table_pos = nve++;
|
|
}
|
|
|
|
/* Assume n. of parsable entries == n. of valid entries */
|
|
val = (nve << 16) & NPE;
|
|
val |= nve & NVE;
|
|
writel(val, ioaddr + MTL_RXP_CONTROL_STATUS);
|
|
|
|
/* Enable RX Parser */
|
|
dwmac5_rxp_enable(ioaddr);
|
|
|
|
re_enable:
|
|
/* Re-enable RX */
|
|
writel(old_val, ioaddr + GMAC_CONFIG);
|
|
return ret;
|
|
}
|
|
|
|
int dwmac5_flex_pps_config(void __iomem *ioaddr, int index,
|
|
struct stmmac_pps_cfg *cfg, bool enable,
|
|
u32 sub_second_inc, u32 systime_flags)
|
|
{
|
|
u32 tnsec = readl(ioaddr + MAC_PPSx_TARGET_TIME_NSEC(index));
|
|
u32 val = readl(ioaddr + MAC_PPS_CONTROL);
|
|
u64 period;
|
|
|
|
if (!cfg->available)
|
|
return -EINVAL;
|
|
if (tnsec & TRGTBUSY0)
|
|
return -EBUSY;
|
|
if (!sub_second_inc || !systime_flags)
|
|
return -EINVAL;
|
|
|
|
val &= ~PPSx_MASK(index);
|
|
|
|
if (!enable) {
|
|
val |= PPSCMDx(index, 0x5);
|
|
val |= PPSEN0;
|
|
writel(val, ioaddr + MAC_PPS_CONTROL);
|
|
return 0;
|
|
}
|
|
|
|
val |= PPSCMDx(index, 0x2);
|
|
val |= TRGTMODSELx(index, 0x2);
|
|
val |= PPSEN0;
|
|
|
|
writel(cfg->start.tv_sec, ioaddr + MAC_PPSx_TARGET_TIME_SEC(index));
|
|
|
|
if (!(systime_flags & PTP_TCR_TSCTRLSSR))
|
|
cfg->start.tv_nsec = (cfg->start.tv_nsec * 1000) / 465;
|
|
writel(cfg->start.tv_nsec, ioaddr + MAC_PPSx_TARGET_TIME_NSEC(index));
|
|
|
|
period = cfg->period.tv_sec * 1000000000;
|
|
period += cfg->period.tv_nsec;
|
|
|
|
do_div(period, sub_second_inc);
|
|
|
|
if (period <= 1)
|
|
return -EINVAL;
|
|
|
|
writel(period - 1, ioaddr + MAC_PPSx_INTERVAL(index));
|
|
|
|
period >>= 1;
|
|
if (period <= 1)
|
|
return -EINVAL;
|
|
|
|
writel(period - 1, ioaddr + MAC_PPSx_WIDTH(index));
|
|
|
|
/* Finally, activate it */
|
|
writel(val, ioaddr + MAC_PPS_CONTROL);
|
|
return 0;
|
|
}
|
|
|
|
static int dwmac5_est_write(void __iomem *ioaddr, u32 reg, u32 val, bool gcl)
|
|
{
|
|
u32 ctrl;
|
|
|
|
writel(val, ioaddr + MTL_EST_GCL_DATA);
|
|
|
|
ctrl = (reg << ADDR_SHIFT);
|
|
ctrl |= gcl ? 0 : GCRR;
|
|
|
|
writel(ctrl, ioaddr + MTL_EST_GCL_CONTROL);
|
|
|
|
ctrl |= SRWO;
|
|
writel(ctrl, ioaddr + MTL_EST_GCL_CONTROL);
|
|
|
|
return readl_poll_timeout(ioaddr + MTL_EST_GCL_CONTROL,
|
|
ctrl, !(ctrl & SRWO), 100, 5000);
|
|
}
|
|
|
|
int dwmac5_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg,
|
|
unsigned int ptp_rate)
|
|
{
|
|
u32 speed, total_offset, offset, ctrl, ctr_low;
|
|
u32 extcfg = readl(ioaddr + GMAC_EXT_CONFIG);
|
|
u32 mac_cfg = readl(ioaddr + GMAC_CONFIG);
|
|
int i, ret = 0x0;
|
|
u64 total_ctr;
|
|
|
|
if (extcfg & GMAC_CONFIG_EIPG_EN) {
|
|
offset = (extcfg & GMAC_CONFIG_EIPG) >> GMAC_CONFIG_EIPG_SHIFT;
|
|
offset = 104 + (offset * 8);
|
|
} else {
|
|
offset = (mac_cfg & GMAC_CONFIG_IPG) >> GMAC_CONFIG_IPG_SHIFT;
|
|
offset = 96 - (offset * 8);
|
|
}
|
|
|
|
speed = mac_cfg & (GMAC_CONFIG_PS | GMAC_CONFIG_FES);
|
|
speed = speed >> GMAC_CONFIG_FES_SHIFT;
|
|
|
|
switch (speed) {
|
|
case 0x0:
|
|
offset = offset * 1000; /* 1G */
|
|
break;
|
|
case 0x1:
|
|
offset = offset * 400; /* 2.5G */
|
|
break;
|
|
case 0x2:
|
|
offset = offset * 100000; /* 10M */
|
|
break;
|
|
case 0x3:
|
|
offset = offset * 10000; /* 100M */
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
offset = offset / 1000;
|
|
|
|
ret |= dwmac5_est_write(ioaddr, BTR_LOW, cfg->btr[0], false);
|
|
ret |= dwmac5_est_write(ioaddr, BTR_HIGH, cfg->btr[1], false);
|
|
ret |= dwmac5_est_write(ioaddr, TER, cfg->ter, false);
|
|
ret |= dwmac5_est_write(ioaddr, LLR, cfg->gcl_size, false);
|
|
if (ret)
|
|
return ret;
|
|
|
|
total_offset = 0;
|
|
for (i = 0; i < cfg->gcl_size; i++) {
|
|
ret = dwmac5_est_write(ioaddr, i, cfg->gcl[i] + offset, true);
|
|
if (ret)
|
|
return ret;
|
|
|
|
total_offset += offset;
|
|
}
|
|
|
|
total_ctr = cfg->ctr[0] + cfg->ctr[1] * 1000000000;
|
|
total_ctr += total_offset;
|
|
|
|
ctr_low = do_div(total_ctr, 1000000000);
|
|
|
|
ret |= dwmac5_est_write(ioaddr, CTR_LOW, ctr_low, false);
|
|
ret |= dwmac5_est_write(ioaddr, CTR_HIGH, total_ctr, false);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ctrl = readl(ioaddr + MTL_EST_CONTROL);
|
|
ctrl &= ~PTOV;
|
|
ctrl |= ((1000000000 / ptp_rate) * 6) << PTOV_SHIFT;
|
|
if (cfg->enable)
|
|
ctrl |= EEST | SSWL;
|
|
else
|
|
ctrl &= ~EEST;
|
|
|
|
writel(ctrl, ioaddr + MTL_EST_CONTROL);
|
|
return 0;
|
|
}
|
|
|
|
void dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num_rxq,
|
|
bool enable)
|
|
{
|
|
u32 value;
|
|
|
|
if (!enable) {
|
|
value = readl(ioaddr + MAC_FPE_CTRL_STS);
|
|
|
|
value &= ~EFPE;
|
|
|
|
writel(value, ioaddr + MAC_FPE_CTRL_STS);
|
|
return;
|
|
}
|
|
|
|
value = readl(ioaddr + GMAC_RXQ_CTRL1);
|
|
value &= ~GMAC_RXQCTRL_FPRQ;
|
|
value |= (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT;
|
|
writel(value, ioaddr + GMAC_RXQ_CTRL1);
|
|
|
|
value = readl(ioaddr + MAC_FPE_CTRL_STS);
|
|
value |= EFPE;
|
|
writel(value, ioaddr + MAC_FPE_CTRL_STS);
|
|
}
|