mirror of https://gitee.com/openkylin/linux.git
282 lines
6.3 KiB
C
282 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/at91_pmc.h>
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#include <linux/of.h>
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#include <linux/mfd/syscon.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/syscore_ops.h>
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#include <asm/proc-fns.h>
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#include <dt-bindings/clock/at91.h>
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#include "pmc.h"
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#define PMC_MAX_IDS 128
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#define PMC_MAX_PCKS 8
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int of_at91_get_clk_range(struct device_node *np, const char *propname,
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struct clk_range *range)
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{
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u32 min, max;
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int ret;
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ret = of_property_read_u32_index(np, propname, 0, &min);
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if (ret)
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return ret;
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ret = of_property_read_u32_index(np, propname, 1, &max);
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if (ret)
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return ret;
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if (range) {
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range->min = min;
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range->max = max;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(of_at91_get_clk_range);
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struct clk_hw *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data)
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{
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unsigned int type = clkspec->args[0];
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unsigned int idx = clkspec->args[1];
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struct pmc_data *pmc_data = data;
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switch (type) {
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case PMC_TYPE_CORE:
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if (idx < pmc_data->ncore)
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return pmc_data->chws[idx];
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break;
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case PMC_TYPE_SYSTEM:
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if (idx < pmc_data->nsystem)
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return pmc_data->shws[idx];
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break;
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case PMC_TYPE_PERIPHERAL:
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if (idx < pmc_data->nperiph)
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return pmc_data->phws[idx];
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break;
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case PMC_TYPE_GCK:
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if (idx < pmc_data->ngck)
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return pmc_data->ghws[idx];
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break;
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case PMC_TYPE_PROGRAMMABLE:
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if (idx < pmc_data->npck)
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return pmc_data->pchws[idx];
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break;
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default:
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break;
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}
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pr_err("%s: invalid type (%u) or index (%u)\n", __func__, type, idx);
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return ERR_PTR(-EINVAL);
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}
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struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem,
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unsigned int nperiph, unsigned int ngck,
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unsigned int npck)
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{
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unsigned int num_clks = ncore + nsystem + nperiph + ngck + npck;
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struct pmc_data *pmc_data;
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pmc_data = kzalloc(struct_size(pmc_data, hwtable, num_clks),
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GFP_KERNEL);
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if (!pmc_data)
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return NULL;
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pmc_data->ncore = ncore;
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pmc_data->chws = pmc_data->hwtable;
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pmc_data->nsystem = nsystem;
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pmc_data->shws = pmc_data->chws + ncore;
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pmc_data->nperiph = nperiph;
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pmc_data->phws = pmc_data->shws + nsystem;
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pmc_data->ngck = ngck;
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pmc_data->ghws = pmc_data->phws + nperiph;
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pmc_data->npck = npck;
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pmc_data->pchws = pmc_data->ghws + ngck;
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return pmc_data;
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}
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#ifdef CONFIG_PM
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static struct regmap *pmcreg;
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static u8 registered_ids[PMC_MAX_IDS];
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static u8 registered_pcks[PMC_MAX_PCKS];
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static struct
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{
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u32 scsr;
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u32 pcsr0;
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u32 uckr;
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u32 mor;
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u32 mcfr;
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u32 pllar;
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u32 mckr;
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u32 usb;
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u32 imr;
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u32 pcsr1;
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u32 pcr[PMC_MAX_IDS];
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u32 audio_pll0;
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u32 audio_pll1;
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u32 pckr[PMC_MAX_PCKS];
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} pmc_cache;
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/*
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* As Peripheral ID 0 is invalid on AT91 chips, the identifier is stored
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* without alteration in the table, and 0 is for unused clocks.
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*/
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void pmc_register_id(u8 id)
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{
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int i;
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for (i = 0; i < PMC_MAX_IDS; i++) {
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if (registered_ids[i] == 0) {
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registered_ids[i] = id;
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break;
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}
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if (registered_ids[i] == id)
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break;
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}
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}
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/*
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* As Programmable Clock 0 is valid on AT91 chips, there is an offset
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* of 1 between the stored value and the real clock ID.
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*/
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void pmc_register_pck(u8 pck)
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{
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int i;
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for (i = 0; i < PMC_MAX_PCKS; i++) {
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if (registered_pcks[i] == 0) {
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registered_pcks[i] = pck + 1;
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break;
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}
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if (registered_pcks[i] == (pck + 1))
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break;
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}
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}
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static int pmc_suspend(void)
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{
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int i;
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u8 num;
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regmap_read(pmcreg, AT91_PMC_SCSR, &pmc_cache.scsr);
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regmap_read(pmcreg, AT91_PMC_PCSR, &pmc_cache.pcsr0);
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regmap_read(pmcreg, AT91_CKGR_UCKR, &pmc_cache.uckr);
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regmap_read(pmcreg, AT91_CKGR_MOR, &pmc_cache.mor);
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regmap_read(pmcreg, AT91_CKGR_MCFR, &pmc_cache.mcfr);
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regmap_read(pmcreg, AT91_CKGR_PLLAR, &pmc_cache.pllar);
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regmap_read(pmcreg, AT91_PMC_MCKR, &pmc_cache.mckr);
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regmap_read(pmcreg, AT91_PMC_USB, &pmc_cache.usb);
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regmap_read(pmcreg, AT91_PMC_IMR, &pmc_cache.imr);
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regmap_read(pmcreg, AT91_PMC_PCSR1, &pmc_cache.pcsr1);
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for (i = 0; registered_ids[i]; i++) {
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regmap_write(pmcreg, AT91_PMC_PCR,
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(registered_ids[i] & AT91_PMC_PCR_PID_MASK));
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regmap_read(pmcreg, AT91_PMC_PCR,
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&pmc_cache.pcr[registered_ids[i]]);
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}
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for (i = 0; registered_pcks[i]; i++) {
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num = registered_pcks[i] - 1;
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regmap_read(pmcreg, AT91_PMC_PCKR(num), &pmc_cache.pckr[num]);
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}
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return 0;
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}
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static bool pmc_ready(unsigned int mask)
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{
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unsigned int status;
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regmap_read(pmcreg, AT91_PMC_SR, &status);
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return ((status & mask) == mask) ? 1 : 0;
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}
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static void pmc_resume(void)
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{
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int i;
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u8 num;
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u32 tmp;
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u32 mask = AT91_PMC_MCKRDY | AT91_PMC_LOCKA;
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regmap_read(pmcreg, AT91_PMC_MCKR, &tmp);
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if (pmc_cache.mckr != tmp)
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pr_warn("MCKR was not configured properly by the firmware\n");
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regmap_read(pmcreg, AT91_CKGR_PLLAR, &tmp);
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if (pmc_cache.pllar != tmp)
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pr_warn("PLLAR was not configured properly by the firmware\n");
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regmap_write(pmcreg, AT91_PMC_SCER, pmc_cache.scsr);
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regmap_write(pmcreg, AT91_PMC_PCER, pmc_cache.pcsr0);
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regmap_write(pmcreg, AT91_CKGR_UCKR, pmc_cache.uckr);
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regmap_write(pmcreg, AT91_CKGR_MOR, pmc_cache.mor);
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regmap_write(pmcreg, AT91_CKGR_MCFR, pmc_cache.mcfr);
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regmap_write(pmcreg, AT91_PMC_USB, pmc_cache.usb);
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regmap_write(pmcreg, AT91_PMC_IMR, pmc_cache.imr);
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regmap_write(pmcreg, AT91_PMC_PCER1, pmc_cache.pcsr1);
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for (i = 0; registered_ids[i]; i++) {
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regmap_write(pmcreg, AT91_PMC_PCR,
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pmc_cache.pcr[registered_ids[i]] |
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AT91_PMC_PCR_CMD);
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}
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for (i = 0; registered_pcks[i]; i++) {
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num = registered_pcks[i] - 1;
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regmap_write(pmcreg, AT91_PMC_PCKR(num), pmc_cache.pckr[num]);
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}
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if (pmc_cache.uckr & AT91_PMC_UPLLEN)
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mask |= AT91_PMC_LOCKU;
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while (!pmc_ready(mask))
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cpu_relax();
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}
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static struct syscore_ops pmc_syscore_ops = {
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.suspend = pmc_suspend,
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.resume = pmc_resume,
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};
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static const struct of_device_id sama5d2_pmc_dt_ids[] = {
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{ .compatible = "atmel,sama5d2-pmc" },
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{ /* sentinel */ }
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};
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static int __init pmc_register_ops(void)
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{
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struct device_node *np;
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np = of_find_matching_node(NULL, sama5d2_pmc_dt_ids);
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if (!np)
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return -ENODEV;
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pmcreg = device_node_to_regmap(np);
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of_node_put(np);
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if (IS_ERR(pmcreg))
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return PTR_ERR(pmcreg);
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register_syscore_ops(&pmc_syscore_ops);
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return 0;
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}
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/* This has to happen before arch_initcall because of the tcb_clksrc driver */
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postcore_initcall(pmc_register_ops);
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#endif
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