..
Makefile
clk: socfpga: agilex: add clock driver for the Agilex platform
2020-05-26 19:13:05 -07:00
clk-agilex.c
clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk
2020-06-19 19:27:33 -07:00
clk-gate-a10.c
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201
2019-05-30 11:29:52 -07:00
clk-gate-s10.c
clk: socfpga: stratix10: use new parent data scheme
2020-05-26 19:13:05 -07:00
clk-gate.c
clk: socfpga: deindent code to proper indentation
2019-08-16 10:20:07 -07:00
clk-periph-a10.c
clk: socfpga: Don't reference clk_init_data after registration
2019-08-16 10:20:07 -07:00
clk-periph-s10.c
clk: socfpga: stratix10: use new parent data scheme
2020-05-26 19:13:05 -07:00
clk-periph.c
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157
2019-05-30 11:26:37 -07:00
clk-pll-a10.c
clk: socfpga: add const to _ops data structures
2020-05-26 19:13:05 -07:00
clk-pll-s10.c
clk: socfpga: agilex: add clock driver for the Agilex platform
2020-05-26 19:13:05 -07:00
clk-pll.c
clk: socfpga: add const to _ops data structures
2020-05-26 19:13:05 -07:00
clk-s10.c
clk: socfpga: stratix10: use new parent data scheme
2020-05-26 19:13:05 -07:00
clk.c
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13
2019-05-21 11:28:45 +02:00
clk.h
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288
2019-06-05 17:36:37 +02:00
stratix10-clk.h
clk: socfpga: agilex: add clock driver for the Agilex platform
2020-05-26 19:13:05 -07:00