mirror of https://gitee.com/openkylin/linux.git
580 lines
14 KiB
C
580 lines
14 KiB
C
/*
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* regmap based irq_chip
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*
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* Copyright 2011 Wolfson Microelectronics plc
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*
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* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/export.h>
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#include <linux/device.h>
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#include <linux/regmap.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include "internal.h"
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struct regmap_irq_chip_data {
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struct mutex lock;
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struct irq_chip irq_chip;
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struct regmap *map;
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const struct regmap_irq_chip *chip;
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int irq_base;
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struct irq_domain *domain;
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int irq;
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int wake_count;
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void *status_reg_buf;
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unsigned int *status_buf;
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unsigned int *mask_buf;
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unsigned int *mask_buf_def;
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unsigned int *wake_buf;
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unsigned int irq_reg_stride;
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};
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static inline const
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struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data,
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int irq)
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{
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return &data->chip->irqs[irq];
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}
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static void regmap_irq_lock(struct irq_data *data)
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{
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struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
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mutex_lock(&d->lock);
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}
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static void regmap_irq_sync_unlock(struct irq_data *data)
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{
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struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
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struct regmap *map = d->map;
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int i, ret;
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u32 reg;
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if (d->chip->runtime_pm) {
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ret = pm_runtime_get_sync(map->dev);
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if (ret < 0)
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dev_err(map->dev, "IRQ sync failed to resume: %d\n",
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ret);
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}
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/*
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* If there's been a change in the mask write it back to the
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* hardware. We rely on the use of the regmap core cache to
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* suppress pointless writes.
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*/
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for (i = 0; i < d->chip->num_regs; i++) {
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reg = d->chip->mask_base +
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(i * map->reg_stride * d->irq_reg_stride);
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if (d->chip->mask_invert)
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ret = regmap_update_bits(d->map, reg,
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d->mask_buf_def[i], ~d->mask_buf[i]);
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else
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ret = regmap_update_bits(d->map, reg,
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d->mask_buf_def[i], d->mask_buf[i]);
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if (ret != 0)
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dev_err(d->map->dev, "Failed to sync masks in %x\n",
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reg);
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reg = d->chip->wake_base +
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(i * map->reg_stride * d->irq_reg_stride);
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if (d->wake_buf) {
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if (d->chip->wake_invert)
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ret = regmap_update_bits(d->map, reg,
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d->mask_buf_def[i],
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~d->wake_buf[i]);
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else
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ret = regmap_update_bits(d->map, reg,
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d->mask_buf_def[i],
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d->wake_buf[i]);
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if (ret != 0)
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dev_err(d->map->dev,
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"Failed to sync wakes in %x: %d\n",
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reg, ret);
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}
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}
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if (d->chip->runtime_pm)
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pm_runtime_put(map->dev);
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/* If we've changed our wakeup count propagate it to the parent */
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if (d->wake_count < 0)
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for (i = d->wake_count; i < 0; i++)
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irq_set_irq_wake(d->irq, 0);
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else if (d->wake_count > 0)
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for (i = 0; i < d->wake_count; i++)
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irq_set_irq_wake(d->irq, 1);
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d->wake_count = 0;
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mutex_unlock(&d->lock);
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}
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static void regmap_irq_enable(struct irq_data *data)
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{
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struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
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struct regmap *map = d->map;
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const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
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d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~irq_data->mask;
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}
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static void regmap_irq_disable(struct irq_data *data)
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{
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struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
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struct regmap *map = d->map;
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const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
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d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;
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}
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static int regmap_irq_set_wake(struct irq_data *data, unsigned int on)
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{
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struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
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struct regmap *map = d->map;
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const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
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if (on) {
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if (d->wake_buf)
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d->wake_buf[irq_data->reg_offset / map->reg_stride]
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&= ~irq_data->mask;
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d->wake_count++;
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} else {
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if (d->wake_buf)
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d->wake_buf[irq_data->reg_offset / map->reg_stride]
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|= irq_data->mask;
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d->wake_count--;
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}
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return 0;
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}
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static const struct irq_chip regmap_irq_chip = {
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.irq_bus_lock = regmap_irq_lock,
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.irq_bus_sync_unlock = regmap_irq_sync_unlock,
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.irq_disable = regmap_irq_disable,
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.irq_enable = regmap_irq_enable,
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.irq_set_wake = regmap_irq_set_wake,
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};
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static irqreturn_t regmap_irq_thread(int irq, void *d)
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{
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struct regmap_irq_chip_data *data = d;
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const struct regmap_irq_chip *chip = data->chip;
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struct regmap *map = data->map;
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int ret, i;
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bool handled = false;
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u32 reg;
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if (chip->runtime_pm) {
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ret = pm_runtime_get_sync(map->dev);
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if (ret < 0) {
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dev_err(map->dev, "IRQ thread failed to resume: %d\n",
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ret);
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pm_runtime_put(map->dev);
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return IRQ_NONE;
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}
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}
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/*
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* Read in the statuses, using a single bulk read if possible
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* in order to reduce the I/O overheads.
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*/
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if (!map->use_single_rw && map->reg_stride == 1 &&
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data->irq_reg_stride == 1) {
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u8 *buf8 = data->status_reg_buf;
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u16 *buf16 = data->status_reg_buf;
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u32 *buf32 = data->status_reg_buf;
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BUG_ON(!data->status_reg_buf);
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ret = regmap_bulk_read(map, chip->status_base,
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data->status_reg_buf,
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chip->num_regs);
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if (ret != 0) {
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dev_err(map->dev, "Failed to read IRQ status: %d\n",
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ret);
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return IRQ_NONE;
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}
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for (i = 0; i < data->chip->num_regs; i++) {
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switch (map->format.val_bytes) {
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case 1:
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data->status_buf[i] = buf8[i];
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break;
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case 2:
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data->status_buf[i] = buf16[i];
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break;
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case 4:
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data->status_buf[i] = buf32[i];
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break;
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default:
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BUG();
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return IRQ_NONE;
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}
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}
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} else {
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for (i = 0; i < data->chip->num_regs; i++) {
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ret = regmap_read(map, chip->status_base +
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(i * map->reg_stride
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* data->irq_reg_stride),
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&data->status_buf[i]);
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if (ret != 0) {
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dev_err(map->dev,
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"Failed to read IRQ status: %d\n",
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ret);
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if (chip->runtime_pm)
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pm_runtime_put(map->dev);
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return IRQ_NONE;
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}
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}
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}
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/*
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* Ignore masked IRQs and ack if we need to; we ack early so
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* there is no race between handling and acknowleding the
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* interrupt. We assume that typically few of the interrupts
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* will fire simultaneously so don't worry about overhead from
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* doing a write per register.
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*/
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for (i = 0; i < data->chip->num_regs; i++) {
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data->status_buf[i] &= ~data->mask_buf[i];
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if (data->status_buf[i] && chip->ack_base) {
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reg = chip->ack_base +
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(i * map->reg_stride * data->irq_reg_stride);
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ret = regmap_write(map, reg, data->status_buf[i]);
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if (ret != 0)
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dev_err(map->dev, "Failed to ack 0x%x: %d\n",
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reg, ret);
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}
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}
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for (i = 0; i < chip->num_irqs; i++) {
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if (data->status_buf[chip->irqs[i].reg_offset /
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map->reg_stride] & chip->irqs[i].mask) {
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handle_nested_irq(irq_find_mapping(data->domain, i));
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handled = true;
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}
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}
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if (chip->runtime_pm)
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pm_runtime_put(map->dev);
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if (handled)
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return IRQ_HANDLED;
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else
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return IRQ_NONE;
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}
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static int regmap_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct regmap_irq_chip_data *data = h->host_data;
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irq_set_chip_data(virq, data);
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irq_set_chip(virq, &data->irq_chip);
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irq_set_nested_thread(virq, 1);
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/* ARM needs us to explicitly flag the IRQ as valid
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* and will set them noprobe when we do so. */
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#ifdef CONFIG_ARM
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set_irq_flags(virq, IRQF_VALID);
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#else
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irq_set_noprobe(virq);
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#endif
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return 0;
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}
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static struct irq_domain_ops regmap_domain_ops = {
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.map = regmap_irq_map,
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.xlate = irq_domain_xlate_twocell,
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};
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/**
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* regmap_add_irq_chip(): Use standard regmap IRQ controller handling
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*
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* map: The regmap for the device.
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* irq: The IRQ the device uses to signal interrupts
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* irq_flags: The IRQF_ flags to use for the primary interrupt.
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* chip: Configuration for the interrupt controller.
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* data: Runtime data structure for the controller, allocated on success
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*
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* Returns 0 on success or an errno on failure.
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*
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* In order for this to be efficient the chip really should use a
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* register cache. The chip driver is responsible for restoring the
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* register values used by the IRQ controller over suspend and resume.
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*/
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int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
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int irq_base, const struct regmap_irq_chip *chip,
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struct regmap_irq_chip_data **data)
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{
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struct regmap_irq_chip_data *d;
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int i;
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int ret = -ENOMEM;
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u32 reg;
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for (i = 0; i < chip->num_irqs; i++) {
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if (chip->irqs[i].reg_offset % map->reg_stride)
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return -EINVAL;
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if (chip->irqs[i].reg_offset / map->reg_stride >=
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chip->num_regs)
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return -EINVAL;
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}
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if (irq_base) {
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irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
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if (irq_base < 0) {
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dev_warn(map->dev, "Failed to allocate IRQs: %d\n",
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irq_base);
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return irq_base;
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}
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}
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d = kzalloc(sizeof(*d), GFP_KERNEL);
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if (!d)
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return -ENOMEM;
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*data = d;
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d->status_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
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GFP_KERNEL);
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if (!d->status_buf)
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goto err_alloc;
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d->mask_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
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GFP_KERNEL);
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if (!d->mask_buf)
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goto err_alloc;
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d->mask_buf_def = kzalloc(sizeof(unsigned int) * chip->num_regs,
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GFP_KERNEL);
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if (!d->mask_buf_def)
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goto err_alloc;
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if (chip->wake_base) {
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d->wake_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
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GFP_KERNEL);
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if (!d->wake_buf)
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goto err_alloc;
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}
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d->irq_chip = regmap_irq_chip;
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d->irq_chip.name = chip->name;
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d->irq = irq;
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d->map = map;
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d->chip = chip;
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d->irq_base = irq_base;
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if (chip->irq_reg_stride)
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d->irq_reg_stride = chip->irq_reg_stride;
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else
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d->irq_reg_stride = 1;
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if (!map->use_single_rw && map->reg_stride == 1 &&
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d->irq_reg_stride == 1) {
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d->status_reg_buf = kmalloc(map->format.val_bytes *
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chip->num_regs, GFP_KERNEL);
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if (!d->status_reg_buf)
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goto err_alloc;
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}
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mutex_init(&d->lock);
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for (i = 0; i < chip->num_irqs; i++)
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d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]
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|= chip->irqs[i].mask;
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/* Mask all the interrupts by default */
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for (i = 0; i < chip->num_regs; i++) {
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d->mask_buf[i] = d->mask_buf_def[i];
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reg = chip->mask_base +
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(i * map->reg_stride * d->irq_reg_stride);
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if (chip->mask_invert)
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ret = regmap_update_bits(map, reg,
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d->mask_buf[i], ~d->mask_buf[i]);
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else
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ret = regmap_update_bits(map, reg,
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d->mask_buf[i], d->mask_buf[i]);
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if (ret != 0) {
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dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
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reg, ret);
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goto err_alloc;
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}
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if (!chip->init_ack_masked)
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continue;
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/* Ack masked but set interrupts */
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reg = chip->status_base +
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(i * map->reg_stride * d->irq_reg_stride);
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ret = regmap_read(map, reg, &d->status_buf[i]);
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if (ret != 0) {
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dev_err(map->dev, "Failed to read IRQ status: %d\n",
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ret);
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goto err_alloc;
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}
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if (d->status_buf[i] && chip->ack_base) {
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reg = chip->ack_base +
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(i * map->reg_stride * d->irq_reg_stride);
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ret = regmap_write(map, reg,
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d->status_buf[i] & d->mask_buf[i]);
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if (ret != 0) {
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dev_err(map->dev, "Failed to ack 0x%x: %d\n",
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reg, ret);
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goto err_alloc;
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}
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}
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}
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/* Wake is disabled by default */
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if (d->wake_buf) {
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for (i = 0; i < chip->num_regs; i++) {
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d->wake_buf[i] = d->mask_buf_def[i];
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reg = chip->wake_base +
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(i * map->reg_stride * d->irq_reg_stride);
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if (chip->wake_invert)
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ret = regmap_update_bits(map, reg,
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d->mask_buf_def[i],
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0);
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else
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ret = regmap_update_bits(map, reg,
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d->mask_buf_def[i],
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d->wake_buf[i]);
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if (ret != 0) {
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dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
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reg, ret);
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goto err_alloc;
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}
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}
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}
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if (irq_base)
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d->domain = irq_domain_add_legacy(map->dev->of_node,
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chip->num_irqs, irq_base, 0,
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®map_domain_ops, d);
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else
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d->domain = irq_domain_add_linear(map->dev->of_node,
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chip->num_irqs,
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®map_domain_ops, d);
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if (!d->domain) {
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dev_err(map->dev, "Failed to create IRQ domain\n");
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ret = -ENOMEM;
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goto err_alloc;
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}
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ret = request_threaded_irq(irq, NULL, regmap_irq_thread, irq_flags,
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chip->name, d);
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if (ret != 0) {
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dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n",
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irq, chip->name, ret);
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goto err_domain;
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}
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return 0;
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err_domain:
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/* Should really dispose of the domain but... */
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err_alloc:
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kfree(d->wake_buf);
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kfree(d->mask_buf_def);
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kfree(d->mask_buf);
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kfree(d->status_buf);
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kfree(d->status_reg_buf);
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kfree(d);
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return ret;
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}
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EXPORT_SYMBOL_GPL(regmap_add_irq_chip);
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/**
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* regmap_del_irq_chip(): Stop interrupt handling for a regmap IRQ chip
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*
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* @irq: Primary IRQ for the device
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* @d: regmap_irq_chip_data allocated by regmap_add_irq_chip()
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*/
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void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
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{
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if (!d)
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return;
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|
|
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free_irq(irq, d);
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/* We should unmap the domain but... */
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|
kfree(d->wake_buf);
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kfree(d->mask_buf_def);
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kfree(d->mask_buf);
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kfree(d->status_reg_buf);
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|
kfree(d->status_buf);
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|
kfree(d);
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}
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EXPORT_SYMBOL_GPL(regmap_del_irq_chip);
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|
|
|
/**
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|
* regmap_irq_chip_get_base(): Retrieve interrupt base for a regmap IRQ chip
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|
*
|
|
* Useful for drivers to request their own IRQs.
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|
*
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|
* @data: regmap_irq controller to operate on.
|
|
*/
|
|
int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data)
|
|
{
|
|
WARN_ON(!data->irq_base);
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|
return data->irq_base;
|
|
}
|
|
EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);
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|
|
|
/**
|
|
* regmap_irq_get_virq(): Map an interrupt on a chip to a virtual IRQ
|
|
*
|
|
* Useful for drivers to request their own IRQs.
|
|
*
|
|
* @data: regmap_irq controller to operate on.
|
|
* @irq: index of the interrupt requested in the chip IRQs
|
|
*/
|
|
int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq)
|
|
{
|
|
/* Handle holes in the IRQ list */
|
|
if (!data->chip->irqs[irq].mask)
|
|
return -EINVAL;
|
|
|
|
return irq_create_mapping(data->domain, irq);
|
|
}
|
|
EXPORT_SYMBOL_GPL(regmap_irq_get_virq);
|
|
|
|
/**
|
|
* regmap_irq_get_domain(): Retrieve the irq_domain for the chip
|
|
*
|
|
* Useful for drivers to request their own IRQs and for integration
|
|
* with subsystems. For ease of integration NULL is accepted as a
|
|
* domain, allowing devices to just call this even if no domain is
|
|
* allocated.
|
|
*
|
|
* @data: regmap_irq controller to operate on.
|
|
*/
|
|
struct irq_domain *regmap_irq_get_domain(struct regmap_irq_chip_data *data)
|
|
{
|
|
if (data)
|
|
return data->domain;
|
|
else
|
|
return NULL;
|
|
}
|
|
EXPORT_SYMBOL_GPL(regmap_irq_get_domain);
|