mirror of https://gitee.com/openkylin/linux.git
620 lines
15 KiB
C
620 lines
15 KiB
C
/*
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* Support for Marvell's Cryptographic Engine and Security Accelerator (CESA)
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* that can be found on the following platform: Orion, Kirkwood, Armada. This
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* driver supports the TDMA engine on platforms on which it is available.
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*
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* Author: Boris Brezillon <boris.brezillon@free-electrons.com>
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* Author: Arnaud Ebalard <arno@natisbad.org>
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*
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* This work is based on an initial version written by
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* Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/genalloc.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kthread.h>
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#include <linux/mbus.h>
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#include <linux/platform_device.h>
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#include <linux/scatterlist.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/dma-direct.h> /* XXX: drivers shall never use this directly! */
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/of_irq.h>
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#include "cesa.h"
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/* Limit of the crypto queue before reaching the backlog */
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#define CESA_CRYPTO_DEFAULT_MAX_QLEN 128
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struct mv_cesa_dev *cesa_dev;
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struct crypto_async_request *
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mv_cesa_dequeue_req_locked(struct mv_cesa_engine *engine,
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struct crypto_async_request **backlog)
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{
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struct crypto_async_request *req;
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*backlog = crypto_get_backlog(&engine->queue);
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req = crypto_dequeue_request(&engine->queue);
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if (!req)
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return NULL;
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return req;
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}
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static void mv_cesa_rearm_engine(struct mv_cesa_engine *engine)
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{
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struct crypto_async_request *req = NULL, *backlog = NULL;
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struct mv_cesa_ctx *ctx;
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spin_lock_bh(&engine->lock);
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if (!engine->req) {
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req = mv_cesa_dequeue_req_locked(engine, &backlog);
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engine->req = req;
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}
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spin_unlock_bh(&engine->lock);
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if (!req)
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return;
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if (backlog)
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backlog->complete(backlog, -EINPROGRESS);
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ctx = crypto_tfm_ctx(req->tfm);
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ctx->ops->step(req);
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}
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static int mv_cesa_std_process(struct mv_cesa_engine *engine, u32 status)
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{
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struct crypto_async_request *req;
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struct mv_cesa_ctx *ctx;
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int res;
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req = engine->req;
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ctx = crypto_tfm_ctx(req->tfm);
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res = ctx->ops->process(req, status);
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if (res == 0) {
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ctx->ops->complete(req);
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mv_cesa_engine_enqueue_complete_request(engine, req);
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} else if (res == -EINPROGRESS) {
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ctx->ops->step(req);
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}
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return res;
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}
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static int mv_cesa_int_process(struct mv_cesa_engine *engine, u32 status)
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{
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if (engine->chain.first && engine->chain.last)
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return mv_cesa_tdma_process(engine, status);
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return mv_cesa_std_process(engine, status);
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}
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static inline void
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mv_cesa_complete_req(struct mv_cesa_ctx *ctx, struct crypto_async_request *req,
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int res)
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{
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ctx->ops->cleanup(req);
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local_bh_disable();
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req->complete(req, res);
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local_bh_enable();
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}
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static irqreturn_t mv_cesa_int(int irq, void *priv)
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{
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struct mv_cesa_engine *engine = priv;
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struct crypto_async_request *req;
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struct mv_cesa_ctx *ctx;
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u32 status, mask;
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irqreturn_t ret = IRQ_NONE;
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while (true) {
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int res;
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mask = mv_cesa_get_int_mask(engine);
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status = readl(engine->regs + CESA_SA_INT_STATUS);
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if (!(status & mask))
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break;
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/*
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* TODO: avoid clearing the FPGA_INT_STATUS if this not
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* relevant on some platforms.
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*/
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writel(~status, engine->regs + CESA_SA_FPGA_INT_STATUS);
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writel(~status, engine->regs + CESA_SA_INT_STATUS);
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/* Process fetched requests */
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res = mv_cesa_int_process(engine, status & mask);
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ret = IRQ_HANDLED;
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spin_lock_bh(&engine->lock);
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req = engine->req;
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if (res != -EINPROGRESS)
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engine->req = NULL;
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spin_unlock_bh(&engine->lock);
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ctx = crypto_tfm_ctx(req->tfm);
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if (res && res != -EINPROGRESS)
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mv_cesa_complete_req(ctx, req, res);
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/* Launch the next pending request */
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mv_cesa_rearm_engine(engine);
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/* Iterate over the complete queue */
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while (true) {
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req = mv_cesa_engine_dequeue_complete_request(engine);
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if (!req)
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break;
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ctx = crypto_tfm_ctx(req->tfm);
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mv_cesa_complete_req(ctx, req, 0);
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}
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}
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return ret;
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}
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int mv_cesa_queue_req(struct crypto_async_request *req,
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struct mv_cesa_req *creq)
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{
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int ret;
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struct mv_cesa_engine *engine = creq->engine;
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spin_lock_bh(&engine->lock);
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ret = crypto_enqueue_request(&engine->queue, req);
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if ((mv_cesa_req_get_type(creq) == CESA_DMA_REQ) &&
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(ret == -EINPROGRESS || ret == -EBUSY))
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mv_cesa_tdma_chain(engine, creq);
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spin_unlock_bh(&engine->lock);
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if (ret != -EINPROGRESS)
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return ret;
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mv_cesa_rearm_engine(engine);
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return -EINPROGRESS;
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}
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static int mv_cesa_add_algs(struct mv_cesa_dev *cesa)
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{
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int ret;
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int i, j;
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for (i = 0; i < cesa->caps->ncipher_algs; i++) {
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ret = crypto_register_skcipher(cesa->caps->cipher_algs[i]);
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if (ret)
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goto err_unregister_crypto;
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}
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for (i = 0; i < cesa->caps->nahash_algs; i++) {
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ret = crypto_register_ahash(cesa->caps->ahash_algs[i]);
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if (ret)
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goto err_unregister_ahash;
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}
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return 0;
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err_unregister_ahash:
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for (j = 0; j < i; j++)
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crypto_unregister_ahash(cesa->caps->ahash_algs[j]);
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i = cesa->caps->ncipher_algs;
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err_unregister_crypto:
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for (j = 0; j < i; j++)
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crypto_unregister_skcipher(cesa->caps->cipher_algs[j]);
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return ret;
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}
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static void mv_cesa_remove_algs(struct mv_cesa_dev *cesa)
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{
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int i;
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for (i = 0; i < cesa->caps->nahash_algs; i++)
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crypto_unregister_ahash(cesa->caps->ahash_algs[i]);
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for (i = 0; i < cesa->caps->ncipher_algs; i++)
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crypto_unregister_skcipher(cesa->caps->cipher_algs[i]);
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}
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static struct skcipher_alg *orion_cipher_algs[] = {
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&mv_cesa_ecb_des_alg,
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&mv_cesa_cbc_des_alg,
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&mv_cesa_ecb_des3_ede_alg,
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&mv_cesa_cbc_des3_ede_alg,
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&mv_cesa_ecb_aes_alg,
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&mv_cesa_cbc_aes_alg,
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};
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static struct ahash_alg *orion_ahash_algs[] = {
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&mv_md5_alg,
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&mv_sha1_alg,
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&mv_ahmac_md5_alg,
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&mv_ahmac_sha1_alg,
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};
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static struct skcipher_alg *armada_370_cipher_algs[] = {
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&mv_cesa_ecb_des_alg,
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&mv_cesa_cbc_des_alg,
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&mv_cesa_ecb_des3_ede_alg,
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&mv_cesa_cbc_des3_ede_alg,
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&mv_cesa_ecb_aes_alg,
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&mv_cesa_cbc_aes_alg,
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};
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static struct ahash_alg *armada_370_ahash_algs[] = {
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&mv_md5_alg,
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&mv_sha1_alg,
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&mv_sha256_alg,
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&mv_ahmac_md5_alg,
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&mv_ahmac_sha1_alg,
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&mv_ahmac_sha256_alg,
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};
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static const struct mv_cesa_caps orion_caps = {
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.nengines = 1,
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.cipher_algs = orion_cipher_algs,
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.ncipher_algs = ARRAY_SIZE(orion_cipher_algs),
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.ahash_algs = orion_ahash_algs,
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.nahash_algs = ARRAY_SIZE(orion_ahash_algs),
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.has_tdma = false,
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};
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static const struct mv_cesa_caps kirkwood_caps = {
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.nengines = 1,
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.cipher_algs = orion_cipher_algs,
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.ncipher_algs = ARRAY_SIZE(orion_cipher_algs),
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.ahash_algs = orion_ahash_algs,
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.nahash_algs = ARRAY_SIZE(orion_ahash_algs),
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.has_tdma = true,
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};
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static const struct mv_cesa_caps armada_370_caps = {
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.nengines = 1,
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.cipher_algs = armada_370_cipher_algs,
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.ncipher_algs = ARRAY_SIZE(armada_370_cipher_algs),
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.ahash_algs = armada_370_ahash_algs,
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.nahash_algs = ARRAY_SIZE(armada_370_ahash_algs),
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.has_tdma = true,
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};
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static const struct mv_cesa_caps armada_xp_caps = {
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.nengines = 2,
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.cipher_algs = armada_370_cipher_algs,
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.ncipher_algs = ARRAY_SIZE(armada_370_cipher_algs),
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.ahash_algs = armada_370_ahash_algs,
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.nahash_algs = ARRAY_SIZE(armada_370_ahash_algs),
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.has_tdma = true,
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};
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static const struct of_device_id mv_cesa_of_match_table[] = {
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{ .compatible = "marvell,orion-crypto", .data = &orion_caps },
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{ .compatible = "marvell,kirkwood-crypto", .data = &kirkwood_caps },
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{ .compatible = "marvell,dove-crypto", .data = &kirkwood_caps },
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{ .compatible = "marvell,armada-370-crypto", .data = &armada_370_caps },
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{ .compatible = "marvell,armada-xp-crypto", .data = &armada_xp_caps },
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{ .compatible = "marvell,armada-375-crypto", .data = &armada_xp_caps },
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{ .compatible = "marvell,armada-38x-crypto", .data = &armada_xp_caps },
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{}
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};
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MODULE_DEVICE_TABLE(of, mv_cesa_of_match_table);
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static void
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mv_cesa_conf_mbus_windows(struct mv_cesa_engine *engine,
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const struct mbus_dram_target_info *dram)
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{
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void __iomem *iobase = engine->regs;
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int i;
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for (i = 0; i < 4; i++) {
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writel(0, iobase + CESA_TDMA_WINDOW_CTRL(i));
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writel(0, iobase + CESA_TDMA_WINDOW_BASE(i));
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}
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for (i = 0; i < dram->num_cs; i++) {
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const struct mbus_dram_window *cs = dram->cs + i;
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writel(((cs->size - 1) & 0xffff0000) |
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(cs->mbus_attr << 8) |
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(dram->mbus_dram_target_id << 4) | 1,
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iobase + CESA_TDMA_WINDOW_CTRL(i));
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writel(cs->base, iobase + CESA_TDMA_WINDOW_BASE(i));
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}
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}
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static int mv_cesa_dev_dma_init(struct mv_cesa_dev *cesa)
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{
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struct device *dev = cesa->dev;
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struct mv_cesa_dev_dma *dma;
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if (!cesa->caps->has_tdma)
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return 0;
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dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
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if (!dma)
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return -ENOMEM;
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dma->tdma_desc_pool = dmam_pool_create("tdma_desc", dev,
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sizeof(struct mv_cesa_tdma_desc),
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16, 0);
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if (!dma->tdma_desc_pool)
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return -ENOMEM;
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dma->op_pool = dmam_pool_create("cesa_op", dev,
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sizeof(struct mv_cesa_op_ctx), 16, 0);
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if (!dma->op_pool)
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return -ENOMEM;
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dma->cache_pool = dmam_pool_create("cesa_cache", dev,
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CESA_MAX_HASH_BLOCK_SIZE, 1, 0);
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if (!dma->cache_pool)
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return -ENOMEM;
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dma->padding_pool = dmam_pool_create("cesa_padding", dev, 72, 1, 0);
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if (!dma->padding_pool)
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return -ENOMEM;
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cesa->dma = dma;
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return 0;
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}
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static int mv_cesa_get_sram(struct platform_device *pdev, int idx)
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{
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struct mv_cesa_dev *cesa = platform_get_drvdata(pdev);
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struct mv_cesa_engine *engine = &cesa->engines[idx];
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const char *res_name = "sram";
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struct resource *res;
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engine->pool = of_gen_pool_get(cesa->dev->of_node,
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"marvell,crypto-srams", idx);
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if (engine->pool) {
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engine->sram = gen_pool_dma_alloc(engine->pool,
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cesa->sram_size,
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&engine->sram_dma);
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if (engine->sram)
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return 0;
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engine->pool = NULL;
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return -ENOMEM;
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}
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if (cesa->caps->nengines > 1) {
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if (!idx)
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res_name = "sram0";
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else
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res_name = "sram1";
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}
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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res_name);
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if (!res || resource_size(res) < cesa->sram_size)
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return -EINVAL;
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engine->sram = devm_ioremap_resource(cesa->dev, res);
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if (IS_ERR(engine->sram))
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return PTR_ERR(engine->sram);
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engine->sram_dma = dma_map_resource(cesa->dev, res->start,
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cesa->sram_size,
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DMA_BIDIRECTIONAL, 0);
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if (dma_mapping_error(cesa->dev, engine->sram_dma))
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return -ENOMEM;
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return 0;
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}
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static void mv_cesa_put_sram(struct platform_device *pdev, int idx)
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{
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struct mv_cesa_dev *cesa = platform_get_drvdata(pdev);
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struct mv_cesa_engine *engine = &cesa->engines[idx];
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if (engine->pool)
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gen_pool_free(engine->pool, (unsigned long)engine->sram,
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cesa->sram_size);
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else
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dma_unmap_resource(cesa->dev, engine->sram_dma,
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cesa->sram_size, DMA_BIDIRECTIONAL, 0);
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}
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static int mv_cesa_probe(struct platform_device *pdev)
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{
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const struct mv_cesa_caps *caps = &orion_caps;
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const struct mbus_dram_target_info *dram;
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const struct of_device_id *match;
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struct device *dev = &pdev->dev;
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struct mv_cesa_dev *cesa;
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struct mv_cesa_engine *engines;
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struct resource *res;
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int irq, ret, i;
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u32 sram_size;
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if (cesa_dev) {
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dev_err(&pdev->dev, "Only one CESA device authorized\n");
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return -EEXIST;
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}
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if (dev->of_node) {
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match = of_match_node(mv_cesa_of_match_table, dev->of_node);
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if (!match || !match->data)
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return -ENOTSUPP;
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caps = match->data;
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}
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cesa = devm_kzalloc(dev, sizeof(*cesa), GFP_KERNEL);
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if (!cesa)
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return -ENOMEM;
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cesa->caps = caps;
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cesa->dev = dev;
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sram_size = CESA_SA_DEFAULT_SRAM_SIZE;
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of_property_read_u32(cesa->dev->of_node, "marvell,crypto-sram-size",
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&sram_size);
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if (sram_size < CESA_SA_MIN_SRAM_SIZE)
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sram_size = CESA_SA_MIN_SRAM_SIZE;
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cesa->sram_size = sram_size;
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cesa->engines = devm_kzalloc(dev, caps->nengines * sizeof(*engines),
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GFP_KERNEL);
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if (!cesa->engines)
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return -ENOMEM;
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spin_lock_init(&cesa->lock);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
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cesa->regs = devm_ioremap_resource(dev, res);
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if (IS_ERR(cesa->regs))
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return PTR_ERR(cesa->regs);
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ret = mv_cesa_dev_dma_init(cesa);
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if (ret)
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return ret;
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dram = mv_mbus_dram_info_nooverlap();
|
|
|
|
platform_set_drvdata(pdev, cesa);
|
|
|
|
for (i = 0; i < caps->nengines; i++) {
|
|
struct mv_cesa_engine *engine = &cesa->engines[i];
|
|
char res_name[7];
|
|
|
|
engine->id = i;
|
|
spin_lock_init(&engine->lock);
|
|
|
|
ret = mv_cesa_get_sram(pdev, i);
|
|
if (ret)
|
|
goto err_cleanup;
|
|
|
|
irq = platform_get_irq(pdev, i);
|
|
if (irq < 0) {
|
|
ret = irq;
|
|
goto err_cleanup;
|
|
}
|
|
|
|
/*
|
|
* Not all platforms can gate the CESA clocks: do not complain
|
|
* if the clock does not exist.
|
|
*/
|
|
snprintf(res_name, sizeof(res_name), "cesa%d", i);
|
|
engine->clk = devm_clk_get(dev, res_name);
|
|
if (IS_ERR(engine->clk)) {
|
|
engine->clk = devm_clk_get(dev, NULL);
|
|
if (IS_ERR(engine->clk))
|
|
engine->clk = NULL;
|
|
}
|
|
|
|
snprintf(res_name, sizeof(res_name), "cesaz%d", i);
|
|
engine->zclk = devm_clk_get(dev, res_name);
|
|
if (IS_ERR(engine->zclk))
|
|
engine->zclk = NULL;
|
|
|
|
ret = clk_prepare_enable(engine->clk);
|
|
if (ret)
|
|
goto err_cleanup;
|
|
|
|
ret = clk_prepare_enable(engine->zclk);
|
|
if (ret)
|
|
goto err_cleanup;
|
|
|
|
engine->regs = cesa->regs + CESA_ENGINE_OFF(i);
|
|
|
|
if (dram && cesa->caps->has_tdma)
|
|
mv_cesa_conf_mbus_windows(engine, dram);
|
|
|
|
writel(0, engine->regs + CESA_SA_INT_STATUS);
|
|
writel(CESA_SA_CFG_STOP_DIG_ERR,
|
|
engine->regs + CESA_SA_CFG);
|
|
writel(engine->sram_dma & CESA_SA_SRAM_MSK,
|
|
engine->regs + CESA_SA_DESC_P0);
|
|
|
|
ret = devm_request_threaded_irq(dev, irq, NULL, mv_cesa_int,
|
|
IRQF_ONESHOT,
|
|
dev_name(&pdev->dev),
|
|
engine);
|
|
if (ret)
|
|
goto err_cleanup;
|
|
|
|
crypto_init_queue(&engine->queue, CESA_CRYPTO_DEFAULT_MAX_QLEN);
|
|
atomic_set(&engine->load, 0);
|
|
INIT_LIST_HEAD(&engine->complete_queue);
|
|
}
|
|
|
|
cesa_dev = cesa;
|
|
|
|
ret = mv_cesa_add_algs(cesa);
|
|
if (ret) {
|
|
cesa_dev = NULL;
|
|
goto err_cleanup;
|
|
}
|
|
|
|
dev_info(dev, "CESA device successfully registered\n");
|
|
|
|
return 0;
|
|
|
|
err_cleanup:
|
|
for (i = 0; i < caps->nengines; i++) {
|
|
clk_disable_unprepare(cesa->engines[i].zclk);
|
|
clk_disable_unprepare(cesa->engines[i].clk);
|
|
mv_cesa_put_sram(pdev, i);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int mv_cesa_remove(struct platform_device *pdev)
|
|
{
|
|
struct mv_cesa_dev *cesa = platform_get_drvdata(pdev);
|
|
int i;
|
|
|
|
mv_cesa_remove_algs(cesa);
|
|
|
|
for (i = 0; i < cesa->caps->nengines; i++) {
|
|
clk_disable_unprepare(cesa->engines[i].zclk);
|
|
clk_disable_unprepare(cesa->engines[i].clk);
|
|
mv_cesa_put_sram(pdev, i);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct platform_device_id mv_cesa_plat_id_table[] = {
|
|
{ .name = "mv_crypto" },
|
|
{ /* sentinel */ },
|
|
};
|
|
MODULE_DEVICE_TABLE(platform, mv_cesa_plat_id_table);
|
|
|
|
static struct platform_driver marvell_cesa = {
|
|
.probe = mv_cesa_probe,
|
|
.remove = mv_cesa_remove,
|
|
.id_table = mv_cesa_plat_id_table,
|
|
.driver = {
|
|
.name = "marvell-cesa",
|
|
.of_match_table = mv_cesa_of_match_table,
|
|
},
|
|
};
|
|
module_platform_driver(marvell_cesa);
|
|
|
|
MODULE_ALIAS("platform:mv_crypto");
|
|
MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
|
|
MODULE_AUTHOR("Arnaud Ebalard <arno@natisbad.org>");
|
|
MODULE_DESCRIPTION("Support for Marvell's cryptographic engine");
|
|
MODULE_LICENSE("GPL v2");
|