mirror of https://gitee.com/openkylin/linux.git
557 lines
12 KiB
Plaintext
557 lines
12 KiB
Plaintext
/include/ "skeleton.dtsi"
|
|
|
|
/ {
|
|
compatible = "nvidia,tegra20";
|
|
interrupt-parent = <&intc>;
|
|
|
|
aliases {
|
|
serial0 = &uarta;
|
|
serial1 = &uartb;
|
|
serial2 = &uartc;
|
|
serial3 = &uartd;
|
|
serial4 = &uarte;
|
|
};
|
|
|
|
host1x {
|
|
compatible = "nvidia,tegra20-host1x", "simple-bus";
|
|
reg = <0x50000000 0x00024000>;
|
|
interrupts = <0 65 0x04 /* mpcore syncpt */
|
|
0 67 0x04>; /* mpcore general */
|
|
clocks = <&tegra_car 28>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
ranges = <0x54000000 0x54000000 0x04000000>;
|
|
|
|
mpe {
|
|
compatible = "nvidia,tegra20-mpe";
|
|
reg = <0x54040000 0x00040000>;
|
|
interrupts = <0 68 0x04>;
|
|
clocks = <&tegra_car 60>;
|
|
};
|
|
|
|
vi {
|
|
compatible = "nvidia,tegra20-vi";
|
|
reg = <0x54080000 0x00040000>;
|
|
interrupts = <0 69 0x04>;
|
|
clocks = <&tegra_car 100>;
|
|
};
|
|
|
|
epp {
|
|
compatible = "nvidia,tegra20-epp";
|
|
reg = <0x540c0000 0x00040000>;
|
|
interrupts = <0 70 0x04>;
|
|
clocks = <&tegra_car 19>;
|
|
};
|
|
|
|
isp {
|
|
compatible = "nvidia,tegra20-isp";
|
|
reg = <0x54100000 0x00040000>;
|
|
interrupts = <0 71 0x04>;
|
|
clocks = <&tegra_car 23>;
|
|
};
|
|
|
|
gr2d {
|
|
compatible = "nvidia,tegra20-gr2d";
|
|
reg = <0x54140000 0x00040000>;
|
|
interrupts = <0 72 0x04>;
|
|
clocks = <&tegra_car 21>;
|
|
};
|
|
|
|
gr3d {
|
|
compatible = "nvidia,tegra20-gr3d";
|
|
reg = <0x54180000 0x00040000>;
|
|
clocks = <&tegra_car 24>;
|
|
};
|
|
|
|
dc@54200000 {
|
|
compatible = "nvidia,tegra20-dc";
|
|
reg = <0x54200000 0x00040000>;
|
|
interrupts = <0 73 0x04>;
|
|
clocks = <&tegra_car 27>, <&tegra_car 121>;
|
|
clock-names = "disp1", "parent";
|
|
|
|
rgb {
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
dc@54240000 {
|
|
compatible = "nvidia,tegra20-dc";
|
|
reg = <0x54240000 0x00040000>;
|
|
interrupts = <0 74 0x04>;
|
|
clocks = <&tegra_car 26>, <&tegra_car 121>;
|
|
clock-names = "disp2", "parent";
|
|
|
|
rgb {
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
hdmi {
|
|
compatible = "nvidia,tegra20-hdmi";
|
|
reg = <0x54280000 0x00040000>;
|
|
interrupts = <0 75 0x04>;
|
|
clocks = <&tegra_car 51>, <&tegra_car 117>;
|
|
clock-names = "hdmi", "parent";
|
|
status = "disabled";
|
|
};
|
|
|
|
tvo {
|
|
compatible = "nvidia,tegra20-tvo";
|
|
reg = <0x542c0000 0x00040000>;
|
|
interrupts = <0 76 0x04>;
|
|
clocks = <&tegra_car 102>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dsi {
|
|
compatible = "nvidia,tegra20-dsi";
|
|
reg = <0x54300000 0x00040000>;
|
|
clocks = <&tegra_car 48>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timer@50004600 {
|
|
compatible = "arm,cortex-a9-twd-timer";
|
|
reg = <0x50040600 0x20>;
|
|
interrupts = <1 13 0x304>;
|
|
clocks = <&tegra_car 132>;
|
|
};
|
|
|
|
intc: interrupt-controller {
|
|
compatible = "arm,cortex-a9-gic";
|
|
reg = <0x50041000 0x1000
|
|
0x50040100 0x0100>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
};
|
|
|
|
cache-controller {
|
|
compatible = "arm,pl310-cache";
|
|
reg = <0x50043000 0x1000>;
|
|
arm,data-latency = <5 5 2>;
|
|
arm,tag-latency = <4 4 2>;
|
|
cache-unified;
|
|
cache-level = <2>;
|
|
};
|
|
|
|
timer@60005000 {
|
|
compatible = "nvidia,tegra20-timer";
|
|
reg = <0x60005000 0x60>;
|
|
interrupts = <0 0 0x04
|
|
0 1 0x04
|
|
0 41 0x04
|
|
0 42 0x04>;
|
|
clocks = <&tegra_car 5>;
|
|
};
|
|
|
|
tegra_car: clock {
|
|
compatible = "nvidia,tegra20-car";
|
|
reg = <0x60006000 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
apbdma: dma {
|
|
compatible = "nvidia,tegra20-apbdma";
|
|
reg = <0x6000a000 0x1200>;
|
|
interrupts = <0 104 0x04
|
|
0 105 0x04
|
|
0 106 0x04
|
|
0 107 0x04
|
|
0 108 0x04
|
|
0 109 0x04
|
|
0 110 0x04
|
|
0 111 0x04
|
|
0 112 0x04
|
|
0 113 0x04
|
|
0 114 0x04
|
|
0 115 0x04
|
|
0 116 0x04
|
|
0 117 0x04
|
|
0 118 0x04
|
|
0 119 0x04>;
|
|
clocks = <&tegra_car 34>;
|
|
};
|
|
|
|
ahb {
|
|
compatible = "nvidia,tegra20-ahb";
|
|
reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
|
|
};
|
|
|
|
gpio: gpio {
|
|
compatible = "nvidia,tegra20-gpio";
|
|
reg = <0x6000d000 0x1000>;
|
|
interrupts = <0 32 0x04
|
|
0 33 0x04
|
|
0 34 0x04
|
|
0 35 0x04
|
|
0 55 0x04
|
|
0 87 0x04
|
|
0 89 0x04>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
pinmux: pinmux {
|
|
compatible = "nvidia,tegra20-pinmux";
|
|
reg = <0x70000014 0x10 /* Tri-state registers */
|
|
0x70000080 0x20 /* Mux registers */
|
|
0x700000a0 0x14 /* Pull-up/down registers */
|
|
0x70000868 0xa8>; /* Pad control registers */
|
|
};
|
|
|
|
das {
|
|
compatible = "nvidia,tegra20-das";
|
|
reg = <0x70000c00 0x80>;
|
|
};
|
|
|
|
tegra_ac97: ac97 {
|
|
compatible = "nvidia,tegra20-ac97";
|
|
reg = <0x70002000 0x200>;
|
|
interrupts = <0 81 0x04>;
|
|
nvidia,dma-request-selector = <&apbdma 12>;
|
|
clocks = <&tegra_car 3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s1: i2s@70002800 {
|
|
compatible = "nvidia,tegra20-i2s";
|
|
reg = <0x70002800 0x200>;
|
|
interrupts = <0 13 0x04>;
|
|
nvidia,dma-request-selector = <&apbdma 2>;
|
|
clocks = <&tegra_car 11>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s2: i2s@70002a00 {
|
|
compatible = "nvidia,tegra20-i2s";
|
|
reg = <0x70002a00 0x200>;
|
|
interrupts = <0 3 0x04>;
|
|
nvidia,dma-request-selector = <&apbdma 1>;
|
|
clocks = <&tegra_car 18>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/*
|
|
* There are two serial driver i.e. 8250 based simple serial
|
|
* driver and APB DMA based serial driver for higher baudrate
|
|
* and performace. To enable the 8250 based driver, the compatible
|
|
* is "nvidia,tegra20-uart" and to enable the APB DMA based serial
|
|
* driver, the comptible is "nvidia,tegra20-hsuart".
|
|
*/
|
|
uarta: serial@70006000 {
|
|
compatible = "nvidia,tegra20-uart";
|
|
reg = <0x70006000 0x40>;
|
|
reg-shift = <2>;
|
|
interrupts = <0 36 0x04>;
|
|
nvidia,dma-request-selector = <&apbdma 8>;
|
|
clocks = <&tegra_car 6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uartb: serial@70006040 {
|
|
compatible = "nvidia,tegra20-uart";
|
|
reg = <0x70006040 0x40>;
|
|
reg-shift = <2>;
|
|
interrupts = <0 37 0x04>;
|
|
nvidia,dma-request-selector = <&apbdma 9>;
|
|
clocks = <&tegra_car 96>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uartc: serial@70006200 {
|
|
compatible = "nvidia,tegra20-uart";
|
|
reg = <0x70006200 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <0 46 0x04>;
|
|
nvidia,dma-request-selector = <&apbdma 10>;
|
|
clocks = <&tegra_car 55>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uartd: serial@70006300 {
|
|
compatible = "nvidia,tegra20-uart";
|
|
reg = <0x70006300 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <0 90 0x04>;
|
|
nvidia,dma-request-selector = <&apbdma 19>;
|
|
clocks = <&tegra_car 65>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uarte: serial@70006400 {
|
|
compatible = "nvidia,tegra20-uart";
|
|
reg = <0x70006400 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <0 91 0x04>;
|
|
nvidia,dma-request-selector = <&apbdma 20>;
|
|
clocks = <&tegra_car 66>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm: pwm {
|
|
compatible = "nvidia,tegra20-pwm";
|
|
reg = <0x7000a000 0x100>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&tegra_car 17>;
|
|
};
|
|
|
|
rtc {
|
|
compatible = "nvidia,tegra20-rtc";
|
|
reg = <0x7000e000 0x100>;
|
|
interrupts = <0 2 0x04>;
|
|
clocks = <&tegra_car 4>;
|
|
};
|
|
|
|
i2c@7000c000 {
|
|
compatible = "nvidia,tegra20-i2c";
|
|
reg = <0x7000c000 0x100>;
|
|
interrupts = <0 38 0x04>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car 12>, <&tegra_car 124>;
|
|
clock-names = "div-clk", "fast-clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000c380 {
|
|
compatible = "nvidia,tegra20-sflash";
|
|
reg = <0x7000c380 0x80>;
|
|
interrupts = <0 39 0x04>;
|
|
nvidia,dma-request-selector = <&apbdma 11>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car 43>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@7000c400 {
|
|
compatible = "nvidia,tegra20-i2c";
|
|
reg = <0x7000c400 0x100>;
|
|
interrupts = <0 84 0x04>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car 54>, <&tegra_car 124>;
|
|
clock-names = "div-clk", "fast-clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@7000c500 {
|
|
compatible = "nvidia,tegra20-i2c";
|
|
reg = <0x7000c500 0x100>;
|
|
interrupts = <0 92 0x04>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car 67>, <&tegra_car 124>;
|
|
clock-names = "div-clk", "fast-clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@7000d000 {
|
|
compatible = "nvidia,tegra20-i2c-dvc";
|
|
reg = <0x7000d000 0x200>;
|
|
interrupts = <0 53 0x04>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car 47>, <&tegra_car 124>;
|
|
clock-names = "div-clk", "fast-clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000d400 {
|
|
compatible = "nvidia,tegra20-slink";
|
|
reg = <0x7000d400 0x200>;
|
|
interrupts = <0 59 0x04>;
|
|
nvidia,dma-request-selector = <&apbdma 15>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car 41>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000d600 {
|
|
compatible = "nvidia,tegra20-slink";
|
|
reg = <0x7000d600 0x200>;
|
|
interrupts = <0 82 0x04>;
|
|
nvidia,dma-request-selector = <&apbdma 16>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car 44>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000d800 {
|
|
compatible = "nvidia,tegra20-slink";
|
|
reg = <0x7000d800 0x200>;
|
|
interrupts = <0 83 0x04>;
|
|
nvidia,dma-request-selector = <&apbdma 17>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car 46>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000da00 {
|
|
compatible = "nvidia,tegra20-slink";
|
|
reg = <0x7000da00 0x200>;
|
|
interrupts = <0 93 0x04>;
|
|
nvidia,dma-request-selector = <&apbdma 18>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car 68>;
|
|
status = "disabled";
|
|
};
|
|
|
|
kbc {
|
|
compatible = "nvidia,tegra20-kbc";
|
|
reg = <0x7000e200 0x100>;
|
|
interrupts = <0 85 0x04>;
|
|
clocks = <&tegra_car 36>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pmc {
|
|
compatible = "nvidia,tegra20-pmc";
|
|
reg = <0x7000e400 0x400>;
|
|
clocks = <&tegra_car 110>, <&clk32k_in>;
|
|
clock-names = "pclk", "clk32k_in";
|
|
};
|
|
|
|
memory-controller@7000f000 {
|
|
compatible = "nvidia,tegra20-mc";
|
|
reg = <0x7000f000 0x024
|
|
0x7000f03c 0x3c4>;
|
|
interrupts = <0 77 0x04>;
|
|
};
|
|
|
|
iommu {
|
|
compatible = "nvidia,tegra20-gart";
|
|
reg = <0x7000f024 0x00000018 /* controller registers */
|
|
0x58000000 0x02000000>; /* GART aperture */
|
|
};
|
|
|
|
memory-controller@7000f400 {
|
|
compatible = "nvidia,tegra20-emc";
|
|
reg = <0x7000f400 0x200>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
phy1: usb-phy@c5000400 {
|
|
compatible = "nvidia,tegra20-usb-phy";
|
|
reg = <0xc5000400 0x3c00>;
|
|
phy_type = "utmi";
|
|
nvidia,has-legacy-mode;
|
|
clocks = <&tegra_car 22>, <&tegra_car 127>;
|
|
clock-names = "phy", "pll_u";
|
|
};
|
|
|
|
phy2: usb-phy@c5004400 {
|
|
compatible = "nvidia,tegra20-usb-phy";
|
|
reg = <0xc5004400 0x3c00>;
|
|
phy_type = "ulpi";
|
|
clocks = <&tegra_car 94>, <&tegra_car 127>;
|
|
clock-names = "phy", "pll_u";
|
|
};
|
|
|
|
phy3: usb-phy@c5008400 {
|
|
compatible = "nvidia,tegra20-usb-phy";
|
|
reg = <0xc5008400 0x3C00>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car 22>, <&tegra_car 127>;
|
|
clock-names = "phy", "pll_u";
|
|
};
|
|
|
|
usb@c5000000 {
|
|
compatible = "nvidia,tegra20-ehci", "usb-ehci";
|
|
reg = <0xc5000000 0x4000>;
|
|
interrupts = <0 20 0x04>;
|
|
phy_type = "utmi";
|
|
nvidia,has-legacy-mode;
|
|
clocks = <&tegra_car 22>;
|
|
nvidia,needs-double-reset;
|
|
nvidia,phy = <&phy1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb@c5004000 {
|
|
compatible = "nvidia,tegra20-ehci", "usb-ehci";
|
|
reg = <0xc5004000 0x4000>;
|
|
interrupts = <0 21 0x04>;
|
|
phy_type = "ulpi";
|
|
clocks = <&tegra_car 58>;
|
|
nvidia,phy = <&phy2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb@c5008000 {
|
|
compatible = "nvidia,tegra20-ehci", "usb-ehci";
|
|
reg = <0xc5008000 0x4000>;
|
|
interrupts = <0 97 0x04>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car 59>;
|
|
nvidia,phy = <&phy3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@c8000000 {
|
|
compatible = "nvidia,tegra20-sdhci";
|
|
reg = <0xc8000000 0x200>;
|
|
interrupts = <0 14 0x04>;
|
|
clocks = <&tegra_car 14>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@c8000200 {
|
|
compatible = "nvidia,tegra20-sdhci";
|
|
reg = <0xc8000200 0x200>;
|
|
interrupts = <0 15 0x04>;
|
|
clocks = <&tegra_car 9>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@c8000400 {
|
|
compatible = "nvidia,tegra20-sdhci";
|
|
reg = <0xc8000400 0x200>;
|
|
interrupts = <0 19 0x04>;
|
|
clocks = <&tegra_car 69>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@c8000600 {
|
|
compatible = "nvidia,tegra20-sdhci";
|
|
reg = <0xc8000600 0x200>;
|
|
interrupts = <0 31 0x04>;
|
|
clocks = <&tegra_car 15>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
reg = <0>;
|
|
};
|
|
|
|
cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
reg = <1>;
|
|
};
|
|
};
|
|
|
|
pmu {
|
|
compatible = "arm,cortex-a9-pmu";
|
|
interrupts = <0 56 0x04
|
|
0 57 0x04>;
|
|
};
|
|
};
|