mirror of https://gitee.com/openkylin/linux.git
340 lines
10 KiB
C
340 lines
10 KiB
C
/*
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* NAND Flash Controller Device Driver
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* Copyright (c) 2009 - 2010, Intel Corporation and its suppliers.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#ifndef __DENALI_H__
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#define __DENALI_H__
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#include <linux/bitops.h>
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#include <linux/mtd/nand.h>
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#define DEVICE_RESET 0x0
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#define DEVICE_RESET__BANK(bank) BIT(bank)
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#define TRANSFER_SPARE_REG 0x10
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#define TRANSFER_SPARE_REG__FLAG BIT(0)
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#define LOAD_WAIT_CNT 0x20
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#define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
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#define PROGRAM_WAIT_CNT 0x30
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#define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)
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#define ERASE_WAIT_CNT 0x40
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#define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
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#define INT_MON_CYCCNT 0x50
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#define INT_MON_CYCCNT__VALUE GENMASK(15, 0)
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#define RB_PIN_ENABLED 0x60
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#define RB_PIN_ENABLED__BANK(bank) BIT(bank)
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#define MULTIPLANE_OPERATION 0x70
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#define MULTIPLANE_OPERATION__FLAG BIT(0)
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#define MULTIPLANE_READ_ENABLE 0x80
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#define MULTIPLANE_READ_ENABLE__FLAG BIT(0)
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#define COPYBACK_DISABLE 0x90
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#define COPYBACK_DISABLE__FLAG BIT(0)
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#define CACHE_WRITE_ENABLE 0xa0
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#define CACHE_WRITE_ENABLE__FLAG BIT(0)
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#define CACHE_READ_ENABLE 0xb0
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#define CACHE_READ_ENABLE__FLAG BIT(0)
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#define PREFETCH_MODE 0xc0
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#define PREFETCH_MODE__PREFETCH_EN BIT(0)
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#define PREFETCH_MODE__PREFETCH_BURST_LENGTH GENMASK(15, 4)
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#define CHIP_ENABLE_DONT_CARE 0xd0
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#define CHIP_EN_DONT_CARE__FLAG BIT(0)
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#define ECC_ENABLE 0xe0
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#define ECC_ENABLE__FLAG BIT(0)
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#define GLOBAL_INT_ENABLE 0xf0
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#define GLOBAL_INT_EN_FLAG BIT(0)
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#define TWHR2_AND_WE_2_RE 0x100
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#define TWHR2_AND_WE_2_RE__WE_2_RE GENMASK(5, 0)
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#define TWHR2_AND_WE_2_RE__TWHR2 GENMASK(13, 8)
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#define TCWAW_AND_ADDR_2_DATA 0x110
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/* The width of ADDR_2_DATA is 6 bit for old IP, 7 bit for new IP */
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#define TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA GENMASK(6, 0)
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#define TCWAW_AND_ADDR_2_DATA__TCWAW GENMASK(13, 8)
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#define RE_2_WE 0x120
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#define RE_2_WE__VALUE GENMASK(5, 0)
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#define ACC_CLKS 0x130
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#define ACC_CLKS__VALUE GENMASK(3, 0)
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#define NUMBER_OF_PLANES 0x140
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#define NUMBER_OF_PLANES__VALUE GENMASK(2, 0)
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#define PAGES_PER_BLOCK 0x150
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#define PAGES_PER_BLOCK__VALUE GENMASK(15, 0)
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#define DEVICE_WIDTH 0x160
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#define DEVICE_WIDTH__VALUE GENMASK(1, 0)
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#define DEVICE_MAIN_AREA_SIZE 0x170
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#define DEVICE_MAIN_AREA_SIZE__VALUE GENMASK(15, 0)
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#define DEVICE_SPARE_AREA_SIZE 0x180
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#define DEVICE_SPARE_AREA_SIZE__VALUE GENMASK(15, 0)
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#define TWO_ROW_ADDR_CYCLES 0x190
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#define TWO_ROW_ADDR_CYCLES__FLAG BIT(0)
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#define MULTIPLANE_ADDR_RESTRICT 0x1a0
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#define MULTIPLANE_ADDR_RESTRICT__FLAG BIT(0)
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#define ECC_CORRECTION 0x1b0
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#define ECC_CORRECTION__VALUE GENMASK(4, 0)
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#define READ_MODE 0x1c0
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#define READ_MODE__VALUE GENMASK(3, 0)
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#define WRITE_MODE 0x1d0
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#define WRITE_MODE__VALUE GENMASK(3, 0)
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#define COPYBACK_MODE 0x1e0
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#define COPYBACK_MODE__VALUE GENMASK(3, 0)
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#define RDWR_EN_LO_CNT 0x1f0
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#define RDWR_EN_LO_CNT__VALUE GENMASK(4, 0)
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#define RDWR_EN_HI_CNT 0x200
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#define RDWR_EN_HI_CNT__VALUE GENMASK(4, 0)
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#define MAX_RD_DELAY 0x210
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#define MAX_RD_DELAY__VALUE GENMASK(3, 0)
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#define CS_SETUP_CNT 0x220
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#define CS_SETUP_CNT__VALUE GENMASK(4, 0)
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#define CS_SETUP_CNT__TWB GENMASK(17, 12)
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#define SPARE_AREA_SKIP_BYTES 0x230
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#define SPARE_AREA_SKIP_BYTES__VALUE GENMASK(5, 0)
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#define SPARE_AREA_MARKER 0x240
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#define SPARE_AREA_MARKER__VALUE GENMASK(15, 0)
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#define DEVICES_CONNECTED 0x250
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#define DEVICES_CONNECTED__VALUE GENMASK(2, 0)
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#define DIE_MASK 0x260
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#define DIE_MASK__VALUE GENMASK(7, 0)
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#define FIRST_BLOCK_OF_NEXT_PLANE 0x270
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#define FIRST_BLOCK_OF_NEXT_PLANE__VALUE GENMASK(15, 0)
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#define WRITE_PROTECT 0x280
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#define WRITE_PROTECT__FLAG BIT(0)
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#define RE_2_RE 0x290
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#define RE_2_RE__VALUE GENMASK(5, 0)
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#define MANUFACTURER_ID 0x300
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#define MANUFACTURER_ID__VALUE GENMASK(7, 0)
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#define DEVICE_ID 0x310
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#define DEVICE_ID__VALUE GENMASK(7, 0)
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#define DEVICE_PARAM_0 0x320
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#define DEVICE_PARAM_0__VALUE GENMASK(7, 0)
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#define DEVICE_PARAM_1 0x330
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#define DEVICE_PARAM_1__VALUE GENMASK(7, 0)
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#define DEVICE_PARAM_2 0x340
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#define DEVICE_PARAM_2__VALUE GENMASK(7, 0)
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#define LOGICAL_PAGE_DATA_SIZE 0x350
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#define LOGICAL_PAGE_DATA_SIZE__VALUE GENMASK(15, 0)
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#define LOGICAL_PAGE_SPARE_SIZE 0x360
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#define LOGICAL_PAGE_SPARE_SIZE__VALUE GENMASK(15, 0)
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#define REVISION 0x370
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#define REVISION__VALUE GENMASK(15, 0)
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#define ONFI_DEVICE_FEATURES 0x380
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#define ONFI_DEVICE_FEATURES__VALUE GENMASK(5, 0)
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#define ONFI_OPTIONAL_COMMANDS 0x390
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#define ONFI_OPTIONAL_COMMANDS__VALUE GENMASK(5, 0)
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#define ONFI_TIMING_MODE 0x3a0
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#define ONFI_TIMING_MODE__VALUE GENMASK(5, 0)
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#define ONFI_PGM_CACHE_TIMING_MODE 0x3b0
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#define ONFI_PGM_CACHE_TIMING_MODE__VALUE GENMASK(5, 0)
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#define ONFI_DEVICE_NO_OF_LUNS 0x3c0
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#define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS GENMASK(7, 0)
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#define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE BIT(8)
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#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0
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#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE GENMASK(15, 0)
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#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0
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#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE GENMASK(15, 0)
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#define FEATURES 0x3f0
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#define FEATURES__N_BANKS GENMASK(1, 0)
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#define FEATURES__ECC_MAX_ERR GENMASK(5, 2)
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#define FEATURES__DMA BIT(6)
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#define FEATURES__CMD_DMA BIT(7)
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#define FEATURES__PARTITION BIT(8)
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#define FEATURES__XDMA_SIDEBAND BIT(9)
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#define FEATURES__GPREG BIT(10)
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#define FEATURES__INDEX_ADDR BIT(11)
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#define TRANSFER_MODE 0x400
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#define TRANSFER_MODE__VALUE GENMASK(1, 0)
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#define INTR_STATUS(bank) (0x410 + (bank) * 0x50)
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#define INTR_EN(bank) (0x420 + (bank) * 0x50)
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/* bit[1:0] is used differently depending on IP version */
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#define INTR__ECC_UNCOR_ERR BIT(0) /* new IP */
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#define INTR__ECC_TRANSACTION_DONE BIT(0) /* old IP */
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#define INTR__ECC_ERR BIT(1) /* old IP */
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#define INTR__DMA_CMD_COMP BIT(2)
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#define INTR__TIME_OUT BIT(3)
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#define INTR__PROGRAM_FAIL BIT(4)
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#define INTR__ERASE_FAIL BIT(5)
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#define INTR__LOAD_COMP BIT(6)
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#define INTR__PROGRAM_COMP BIT(7)
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#define INTR__ERASE_COMP BIT(8)
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#define INTR__PIPE_CPYBCK_CMD_COMP BIT(9)
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#define INTR__LOCKED_BLK BIT(10)
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#define INTR__UNSUP_CMD BIT(11)
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#define INTR__INT_ACT BIT(12)
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#define INTR__RST_COMP BIT(13)
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#define INTR__PIPE_CMD_ERR BIT(14)
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#define INTR__PAGE_XFER_INC BIT(15)
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#define PAGE_CNT(bank) (0x430 + (bank) * 0x50)
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#define ERR_PAGE_ADDR(bank) (0x440 + (bank) * 0x50)
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#define ERR_BLOCK_ADDR(bank) (0x450 + (bank) * 0x50)
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#define ECC_THRESHOLD 0x600
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#define ECC_THRESHOLD__VALUE GENMASK(9, 0)
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#define ECC_ERROR_BLOCK_ADDRESS 0x610
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#define ECC_ERROR_BLOCK_ADDRESS__VALUE GENMASK(15, 0)
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#define ECC_ERROR_PAGE_ADDRESS 0x620
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#define ECC_ERROR_PAGE_ADDRESS__VALUE GENMASK(11, 0)
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#define ECC_ERROR_PAGE_ADDRESS__BANK GENMASK(15, 12)
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#define ECC_ERROR_ADDRESS 0x630
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#define ECC_ERROR_ADDRESS__OFFSET GENMASK(11, 0)
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#define ECC_ERROR_ADDRESS__SECTOR_NR GENMASK(15, 12)
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#define ERR_CORRECTION_INFO 0x640
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#define ERR_CORRECTION_INFO__BYTEMASK GENMASK(7, 0)
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#define ERR_CORRECTION_INFO__DEVICE_NR GENMASK(11, 8)
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#define ERR_CORRECTION_INFO__ERROR_TYPE BIT(14)
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#define ERR_CORRECTION_INFO__LAST_ERR_INFO BIT(15)
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#define ECC_COR_INFO(bank) (0x650 + (bank) / 2 * 0x10)
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#define ECC_COR_INFO__SHIFT(bank) ((bank) % 2 * 8)
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#define ECC_COR_INFO__MAX_ERRORS GENMASK(6, 0)
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#define ECC_COR_INFO__UNCOR_ERR BIT(7)
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#define CFG_DATA_BLOCK_SIZE 0x6b0
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#define CFG_LAST_DATA_BLOCK_SIZE 0x6c0
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#define CFG_NUM_DATA_BLOCKS 0x6d0
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#define CFG_META_DATA_SIZE 0x6e0
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#define DMA_ENABLE 0x700
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#define DMA_ENABLE__FLAG BIT(0)
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#define IGNORE_ECC_DONE 0x710
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#define IGNORE_ECC_DONE__FLAG BIT(0)
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#define DMA_INTR 0x720
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#define DMA_INTR_EN 0x730
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#define DMA_INTR__TARGET_ERROR BIT(0)
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#define DMA_INTR__DESC_COMP_CHANNEL0 BIT(1)
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#define DMA_INTR__DESC_COMP_CHANNEL1 BIT(2)
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#define DMA_INTR__DESC_COMP_CHANNEL2 BIT(3)
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#define DMA_INTR__DESC_COMP_CHANNEL3 BIT(4)
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#define DMA_INTR__MEMCOPY_DESC_COMP BIT(5)
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#define TARGET_ERR_ADDR_LO 0x740
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#define TARGET_ERR_ADDR_LO__VALUE GENMASK(15, 0)
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#define TARGET_ERR_ADDR_HI 0x750
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#define TARGET_ERR_ADDR_HI__VALUE GENMASK(15, 0)
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#define CHNL_ACTIVE 0x760
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#define CHNL_ACTIVE__CHANNEL0 BIT(0)
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#define CHNL_ACTIVE__CHANNEL1 BIT(1)
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#define CHNL_ACTIVE__CHANNEL2 BIT(2)
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#define CHNL_ACTIVE__CHANNEL3 BIT(3)
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#define MODE_00 0x00000000
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#define MODE_01 0x04000000
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#define MODE_10 0x08000000
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#define MODE_11 0x0C000000
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struct denali_nand_info {
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struct nand_chip nand;
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unsigned long clk_x_rate; /* bus interface clock rate */
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int flash_bank; /* currently selected chip */
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struct device *dev;
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void __iomem *flash_reg; /* Register Interface */
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void __iomem *flash_mem; /* Host Data/Command Interface */
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/* elements used by ISR */
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struct completion complete;
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spinlock_t irq_lock;
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uint32_t irq_mask;
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uint32_t irq_status;
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int irq;
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void *buf;
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dma_addr_t dma_addr;
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int dma_avail;
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int devnum; /* represent how many nands connected */
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int bbtskipbytes;
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int max_banks;
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unsigned int revision;
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unsigned int caps;
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const struct nand_ecc_caps *ecc_caps;
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};
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#define DENALI_CAP_HW_ECC_FIXUP BIT(0)
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#define DENALI_CAP_DMA_64BIT BIT(1)
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int denali_calc_ecc_bytes(int step_size, int strength);
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extern int denali_init(struct denali_nand_info *denali);
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extern void denali_remove(struct denali_nand_info *denali);
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#endif /* __DENALI_H__ */
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