mirror of https://gitee.com/openkylin/linux.git
438 lines
12 KiB
C
438 lines
12 KiB
C
/*
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* ti_hdmi_4xxx_ip.h
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*
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* HDMI header definition for DM81xx, DM38xx, TI OMAP4 etc processors.
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _HDMI_TI_4xxx_H_
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#define _HDMI_TI_4xxx_H_
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#include <linux/string.h>
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#include <video/omapdss.h>
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#include "ti_hdmi.h"
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/* HDMI Wrapper */
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#define HDMI_WP_REVISION 0x0
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#define HDMI_WP_SYSCONFIG 0x10
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#define HDMI_WP_IRQSTATUS_RAW 0x24
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#define HDMI_WP_IRQSTATUS 0x28
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#define HDMI_WP_PWR_CTRL 0x40
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#define HDMI_WP_IRQENABLE_SET 0x2C
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#define HDMI_WP_IRQENABLE_CLR 0x30
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#define HDMI_WP_VIDEO_CFG 0x50
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#define HDMI_WP_VIDEO_SIZE 0x60
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#define HDMI_WP_VIDEO_TIMING_H 0x68
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#define HDMI_WP_VIDEO_TIMING_V 0x6C
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#define HDMI_WP_WP_CLK 0x70
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#define HDMI_WP_AUDIO_CFG 0x80
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#define HDMI_WP_AUDIO_CFG2 0x84
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#define HDMI_WP_AUDIO_CTRL 0x88
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#define HDMI_WP_AUDIO_DATA 0x8C
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/* HDMI IP Core System */
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#define HDMI_CORE_SYS_VND_IDL 0x0
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#define HDMI_CORE_SYS_DEV_IDL 0x8
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#define HDMI_CORE_SYS_DEV_IDH 0xC
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#define HDMI_CORE_SYS_DEV_REV 0x10
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#define HDMI_CORE_SYS_SRST 0x14
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#define HDMI_CORE_CTRL1 0x20
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#define HDMI_CORE_SYS_SYS_STAT 0x24
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#define HDMI_CORE_SYS_DE_DLY 0xC8
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#define HDMI_CORE_SYS_DE_CTRL 0xCC
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#define HDMI_CORE_SYS_DE_TOP 0xD0
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#define HDMI_CORE_SYS_DE_CNTL 0xD8
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#define HDMI_CORE_SYS_DE_CNTH 0xDC
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#define HDMI_CORE_SYS_DE_LINL 0xE0
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#define HDMI_CORE_SYS_DE_LINH_1 0xE4
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#define HDMI_CORE_SYS_VID_ACEN 0x124
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#define HDMI_CORE_SYS_VID_MODE 0x128
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#define HDMI_CORE_SYS_INTR_STATE 0x1C0
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#define HDMI_CORE_SYS_INTR1 0x1C4
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#define HDMI_CORE_SYS_INTR2 0x1C8
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#define HDMI_CORE_SYS_INTR3 0x1CC
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#define HDMI_CORE_SYS_INTR4 0x1D0
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#define HDMI_CORE_SYS_UMASK1 0x1D4
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#define HDMI_CORE_SYS_TMDS_CTRL 0x208
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#define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC 0x1
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#define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC 0x1
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#define HDMI_CORE_CTRL1_BSEL_24BITBUS 0x1
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#define HDMI_CORE_CTRL1_EDGE_RISINGEDGE 0x1
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/* HDMI DDC E-DID */
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#define HDMI_CORE_DDC_ADDR 0x3B4
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#define HDMI_CORE_DDC_SEGM 0x3B8
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#define HDMI_CORE_DDC_OFFSET 0x3BC
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#define HDMI_CORE_DDC_COUNT1 0x3C0
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#define HDMI_CORE_DDC_COUNT2 0x3C4
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#define HDMI_CORE_DDC_STATUS 0x3C8
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#define HDMI_CORE_DDC_CMD 0x3CC
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#define HDMI_CORE_DDC_DATA 0x3D0
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/* HDMI IP Core Audio Video */
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#define HDMI_CORE_AV_ACR_CTRL 0x4
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#define HDMI_CORE_AV_FREQ_SVAL 0x8
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#define HDMI_CORE_AV_N_SVAL1 0xC
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#define HDMI_CORE_AV_N_SVAL2 0x10
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#define HDMI_CORE_AV_N_SVAL3 0x14
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#define HDMI_CORE_AV_CTS_SVAL1 0x18
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#define HDMI_CORE_AV_CTS_SVAL2 0x1C
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#define HDMI_CORE_AV_CTS_SVAL3 0x20
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#define HDMI_CORE_AV_CTS_HVAL1 0x24
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#define HDMI_CORE_AV_CTS_HVAL2 0x28
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#define HDMI_CORE_AV_CTS_HVAL3 0x2C
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#define HDMI_CORE_AV_AUD_MODE 0x50
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#define HDMI_CORE_AV_SPDIF_CTRL 0x54
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#define HDMI_CORE_AV_HW_SPDIF_FS 0x60
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#define HDMI_CORE_AV_SWAP_I2S 0x64
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#define HDMI_CORE_AV_SPDIF_ERTH 0x6C
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#define HDMI_CORE_AV_I2S_IN_MAP 0x70
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#define HDMI_CORE_AV_I2S_IN_CTRL 0x74
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#define HDMI_CORE_AV_I2S_CHST0 0x78
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#define HDMI_CORE_AV_I2S_CHST1 0x7C
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#define HDMI_CORE_AV_I2S_CHST2 0x80
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#define HDMI_CORE_AV_I2S_CHST4 0x84
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#define HDMI_CORE_AV_I2S_CHST5 0x88
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#define HDMI_CORE_AV_ASRC 0x8C
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#define HDMI_CORE_AV_I2S_IN_LEN 0x90
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#define HDMI_CORE_AV_HDMI_CTRL 0xBC
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#define HDMI_CORE_AV_AUDO_TXSTAT 0xC0
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#define HDMI_CORE_AV_AUD_PAR_BUSCLK_1 0xCC
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#define HDMI_CORE_AV_AUD_PAR_BUSCLK_2 0xD0
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#define HDMI_CORE_AV_AUD_PAR_BUSCLK_3 0xD4
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#define HDMI_CORE_AV_TEST_TXCTRL 0xF0
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#define HDMI_CORE_AV_DPD 0xF4
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#define HDMI_CORE_AV_PB_CTRL1 0xF8
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#define HDMI_CORE_AV_PB_CTRL2 0xFC
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#define HDMI_CORE_AV_AVI_TYPE 0x100
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#define HDMI_CORE_AV_AVI_VERS 0x104
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#define HDMI_CORE_AV_AVI_LEN 0x108
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#define HDMI_CORE_AV_AVI_CHSUM 0x10C
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#define HDMI_CORE_AV_AVI_DBYTE(n) (n * 4 + 0x110)
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#define HDMI_CORE_AV_SPD_TYPE 0x180
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#define HDMI_CORE_AV_SPD_VERS 0x184
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#define HDMI_CORE_AV_SPD_LEN 0x188
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#define HDMI_CORE_AV_SPD_CHSUM 0x18C
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#define HDMI_CORE_AV_SPD_DBYTE(n) (n * 4 + 0x190)
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#define HDMI_CORE_AV_AUDIO_TYPE 0x200
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#define HDMI_CORE_AV_AUDIO_VERS 0x204
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#define HDMI_CORE_AV_AUDIO_LEN 0x208
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#define HDMI_CORE_AV_AUDIO_CHSUM 0x20C
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#define HDMI_CORE_AV_AUD_DBYTE(n) (n * 4 + 0x210)
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#define HDMI_CORE_AV_MPEG_TYPE 0x280
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#define HDMI_CORE_AV_MPEG_VERS 0x284
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#define HDMI_CORE_AV_MPEG_LEN 0x288
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#define HDMI_CORE_AV_MPEG_CHSUM 0x28C
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#define HDMI_CORE_AV_MPEG_DBYTE(n) (n * 4 + 0x290)
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#define HDMI_CORE_AV_GEN_DBYTE(n) (n * 4 + 0x300)
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#define HDMI_CORE_AV_CP_BYTE1 0x37C
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#define HDMI_CORE_AV_GEN2_DBYTE(n) (n * 4 + 0x380)
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#define HDMI_CORE_AV_CEC_ADDR_ID 0x3FC
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#define HDMI_CORE_AV_SPD_DBYTE_ELSIZE 0x4
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#define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE 0x4
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#define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE 0x4
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#define HDMI_CORE_AV_GEN_DBYTE_ELSIZE 0x4
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#define HDMI_CORE_AV_AVI_DBYTE_NELEMS 15
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#define HDMI_CORE_AV_SPD_DBYTE_NELEMS 27
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#define HDMI_CORE_AV_AUD_DBYTE_NELEMS 10
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#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS 27
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#define HDMI_CORE_AV_GEN_DBYTE_NELEMS 31
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#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS 31
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/* PLL */
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#define PLLCTRL_PLL_CONTROL 0x0
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#define PLLCTRL_PLL_STATUS 0x4
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#define PLLCTRL_PLL_GO 0x8
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#define PLLCTRL_CFG1 0xC
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#define PLLCTRL_CFG2 0x10
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#define PLLCTRL_CFG3 0x14
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#define PLLCTRL_CFG4 0x20
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/* HDMI PHY */
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#define HDMI_TXPHY_TX_CTRL 0x0
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#define HDMI_TXPHY_DIGITAL_CTRL 0x4
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#define HDMI_TXPHY_POWER_CTRL 0x8
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#define HDMI_TXPHY_PAD_CFG_CTRL 0xC
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#define REG_FLD_MOD(base, idx, val, start, end) \
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hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
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val, start, end))
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#define REG_GET(base, idx, start, end) \
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FLD_GET(hdmi_read_reg(base, idx), start, end)
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enum hdmi_phy_pwr {
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HDMI_PHYPWRCMD_OFF = 0,
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HDMI_PHYPWRCMD_LDOON = 1,
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HDMI_PHYPWRCMD_TXON = 2
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};
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enum hdmi_core_inputbus_width {
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HDMI_INPUT_8BIT = 0,
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HDMI_INPUT_10BIT = 1,
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HDMI_INPUT_12BIT = 2
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};
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enum hdmi_core_dither_trunc {
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HDMI_OUTPUTTRUNCATION_8BIT = 0,
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HDMI_OUTPUTTRUNCATION_10BIT = 1,
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HDMI_OUTPUTTRUNCATION_12BIT = 2,
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HDMI_OUTPUTDITHER_8BIT = 3,
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HDMI_OUTPUTDITHER_10BIT = 4,
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HDMI_OUTPUTDITHER_12BIT = 5
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};
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enum hdmi_core_deepcolor_ed {
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HDMI_DEEPCOLORPACKECTDISABLE = 0,
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HDMI_DEEPCOLORPACKECTENABLE = 1
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};
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enum hdmi_core_packet_mode {
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HDMI_PACKETMODERESERVEDVALUE = 0,
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HDMI_PACKETMODE24BITPERPIXEL = 4,
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HDMI_PACKETMODE30BITPERPIXEL = 5,
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HDMI_PACKETMODE36BITPERPIXEL = 6,
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HDMI_PACKETMODE48BITPERPIXEL = 7
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};
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enum hdmi_core_tclkselclkmult {
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HDMI_FPLL05IDCK = 0,
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HDMI_FPLL10IDCK = 1,
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HDMI_FPLL20IDCK = 2,
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HDMI_FPLL40IDCK = 3
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};
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enum hdmi_core_packet_ctrl {
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HDMI_PACKETENABLE = 1,
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HDMI_PACKETDISABLE = 0,
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HDMI_PACKETREPEATON = 1,
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HDMI_PACKETREPEATOFF = 0
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};
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/* INFOFRAME_AVI_ and INFOFRAME_AUDIO_ definitions */
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enum hdmi_core_infoframe {
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HDMI_INFOFRAME_AVI_DB1Y_RGB = 0,
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HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1,
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HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2,
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HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0,
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HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON = 1,
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HDMI_INFOFRAME_AVI_DB1B_NO = 0,
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HDMI_INFOFRAME_AVI_DB1B_VERT = 1,
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HDMI_INFOFRAME_AVI_DB1B_HORI = 2,
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HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3,
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HDMI_INFOFRAME_AVI_DB1S_0 = 0,
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HDMI_INFOFRAME_AVI_DB1S_1 = 1,
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HDMI_INFOFRAME_AVI_DB1S_2 = 2,
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HDMI_INFOFRAME_AVI_DB2C_NO = 0,
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HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1,
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HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2,
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HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3,
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HDMI_INFOFRAME_AVI_DB2M_NO = 0,
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HDMI_INFOFRAME_AVI_DB2M_43 = 1,
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HDMI_INFOFRAME_AVI_DB2M_169 = 2,
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HDMI_INFOFRAME_AVI_DB2R_SAME = 8,
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HDMI_INFOFRAME_AVI_DB2R_43 = 9,
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HDMI_INFOFRAME_AVI_DB2R_169 = 10,
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HDMI_INFOFRAME_AVI_DB2R_149 = 11,
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HDMI_INFOFRAME_AVI_DB3ITC_NO = 0,
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HDMI_INFOFRAME_AVI_DB3ITC_YES = 1,
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HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0,
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HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1,
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HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0,
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HDMI_INFOFRAME_AVI_DB3Q_LR = 1,
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HDMI_INFOFRAME_AVI_DB3Q_FR = 2,
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HDMI_INFOFRAME_AVI_DB3SC_NO = 0,
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HDMI_INFOFRAME_AVI_DB3SC_HORI = 1,
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HDMI_INFOFRAME_AVI_DB3SC_VERT = 2,
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HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3,
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HDMI_INFOFRAME_AVI_DB5PR_NO = 0,
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HDMI_INFOFRAME_AVI_DB5PR_2 = 1,
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HDMI_INFOFRAME_AVI_DB5PR_3 = 2,
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HDMI_INFOFRAME_AVI_DB5PR_4 = 3,
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HDMI_INFOFRAME_AVI_DB5PR_5 = 4,
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HDMI_INFOFRAME_AVI_DB5PR_6 = 5,
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HDMI_INFOFRAME_AVI_DB5PR_7 = 6,
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HDMI_INFOFRAME_AVI_DB5PR_8 = 7,
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HDMI_INFOFRAME_AVI_DB5PR_9 = 8,
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HDMI_INFOFRAME_AVI_DB5PR_10 = 9,
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};
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enum hdmi_packing_mode {
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HDMI_PACK_10b_RGB_YUV444 = 0,
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HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
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HDMI_PACK_20b_YUV422 = 2,
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HDMI_PACK_ALREADYPACKED = 7
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};
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enum hdmi_core_audio_layout {
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HDMI_AUDIO_LAYOUT_2CH = 0,
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HDMI_AUDIO_LAYOUT_8CH = 1
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};
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enum hdmi_core_cts_mode {
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HDMI_AUDIO_CTS_MODE_HW = 0,
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HDMI_AUDIO_CTS_MODE_SW = 1
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};
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enum hdmi_stereo_channels {
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HDMI_AUDIO_STEREO_NOCHANNELS = 0,
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HDMI_AUDIO_STEREO_ONECHANNEL = 1,
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HDMI_AUDIO_STEREO_TWOCHANNELS = 2,
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HDMI_AUDIO_STEREO_THREECHANNELS = 3,
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HDMI_AUDIO_STEREO_FOURCHANNELS = 4
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};
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enum hdmi_audio_type {
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HDMI_AUDIO_TYPE_LPCM = 0,
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HDMI_AUDIO_TYPE_IEC = 1
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};
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enum hdmi_audio_justify {
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HDMI_AUDIO_JUSTIFY_LEFT = 0,
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HDMI_AUDIO_JUSTIFY_RIGHT = 1
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};
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enum hdmi_audio_sample_order {
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HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,
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HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1
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};
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enum hdmi_audio_samples_perword {
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HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,
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HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1
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};
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enum hdmi_audio_sample_size {
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HDMI_AUDIO_SAMPLE_16BITS = 0,
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HDMI_AUDIO_SAMPLE_24BITS = 1
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};
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enum hdmi_audio_transf_mode {
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HDMI_AUDIO_TRANSF_DMA = 0,
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HDMI_AUDIO_TRANSF_IRQ = 1
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};
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enum hdmi_audio_blk_strt_end_sig {
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HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,
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HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1
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};
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enum hdmi_audio_i2s_config {
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HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST = 0,
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HDMI_AUDIO_I2S_LSB_SHIFTED_FIRST = 1,
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HDMI_AUDIO_I2S_SCK_EDGE_FALLING = 0,
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HDMI_AUDIO_I2S_SCK_EDGE_RISING = 1,
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HDMI_AUDIO_I2S_VBIT_FOR_PCM = 0,
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HDMI_AUDIO_I2S_VBIT_FOR_COMPRESSED = 1,
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HDMI_AUDIO_I2S_FIRST_BIT_SHIFT = 0,
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HDMI_AUDIO_I2S_FIRST_BIT_NO_SHIFT = 1,
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HDMI_AUDIO_I2S_SD0_EN = 1,
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HDMI_AUDIO_I2S_SD1_EN = 1 << 1,
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HDMI_AUDIO_I2S_SD2_EN = 1 << 2,
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HDMI_AUDIO_I2S_SD3_EN = 1 << 3,
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};
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enum hdmi_audio_mclk_mode {
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HDMI_AUDIO_MCLK_128FS = 0,
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HDMI_AUDIO_MCLK_256FS = 1,
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HDMI_AUDIO_MCLK_384FS = 2,
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HDMI_AUDIO_MCLK_512FS = 3,
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HDMI_AUDIO_MCLK_768FS = 4,
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HDMI_AUDIO_MCLK_1024FS = 5,
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HDMI_AUDIO_MCLK_1152FS = 6,
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HDMI_AUDIO_MCLK_192FS = 7
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};
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struct hdmi_core_video_config {
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enum hdmi_core_inputbus_width ip_bus_width;
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enum hdmi_core_dither_trunc op_dither_truc;
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enum hdmi_core_deepcolor_ed deep_color_pkt;
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enum hdmi_core_packet_mode pkt_mode;
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enum hdmi_core_hdmi_dvi hdmi_dvi;
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enum hdmi_core_tclkselclkmult tclk_sel_clkmult;
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};
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struct hdmi_core_packet_enable_repeat {
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u32 audio_pkt;
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u32 audio_pkt_repeat;
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u32 avi_infoframe;
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u32 avi_infoframe_repeat;
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u32 gen_cntrl_pkt;
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u32 gen_cntrl_pkt_repeat;
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u32 generic_pkt;
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u32 generic_pkt_repeat;
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};
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struct hdmi_video_format {
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enum hdmi_packing_mode packing_mode;
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u32 y_res; /* Line per panel */
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u32 x_res; /* pixel per line */
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};
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struct hdmi_audio_format {
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enum hdmi_stereo_channels stereo_channels;
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u8 active_chnnls_msk;
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enum hdmi_audio_type type;
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enum hdmi_audio_justify justification;
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enum hdmi_audio_sample_order sample_order;
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enum hdmi_audio_samples_perword samples_per_word;
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enum hdmi_audio_sample_size sample_size;
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enum hdmi_audio_blk_strt_end_sig en_sig_blk_strt_end;
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};
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struct hdmi_audio_dma {
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u8 transfer_size;
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u8 block_size;
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enum hdmi_audio_transf_mode mode;
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u16 fifo_threshold;
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};
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struct hdmi_core_audio_i2s_config {
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u8 in_length_bits;
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|
u8 justification;
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|
u8 sck_edge_mode;
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u8 vbit;
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|
u8 direction;
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|
u8 shift;
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|
u8 active_sds;
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|
};
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|
|
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struct hdmi_core_audio_config {
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struct hdmi_core_audio_i2s_config i2s_cfg;
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|
struct snd_aes_iec958 *iec60958_cfg;
|
|
bool fs_override;
|
|
u32 n;
|
|
u32 cts;
|
|
u32 aud_par_busclk;
|
|
enum hdmi_core_audio_layout layout;
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|
enum hdmi_core_cts_mode cts_mode;
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|
bool use_mclk;
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|
enum hdmi_audio_mclk_mode mclk_mode;
|
|
bool en_acr_pkt;
|
|
bool en_dsd_audio;
|
|
bool en_parallel_aud_input;
|
|
bool en_spdif;
|
|
};
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#endif
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