mirror of https://gitee.com/openkylin/linux.git
526 lines
13 KiB
C
526 lines
13 KiB
C
/*
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* Register interface file for Samsung Camera Interface (FIMC) driver
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*
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* Copyright (c) 2010 Samsung Electronics
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*
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* Sylwester Nawrocki, s.nawrocki@samsung.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <mach/map.h>
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#include "fimc-core.h"
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void fimc_hw_reset(struct fimc_dev *dev)
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{
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u32 cfg;
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cfg = readl(dev->regs + S5P_CISRCFMT);
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cfg |= S5P_CISRCFMT_ITU601_8BIT;
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writel(cfg, dev->regs + S5P_CISRCFMT);
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/* Software reset. */
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cfg = readl(dev->regs + S5P_CIGCTRL);
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cfg |= (S5P_CIGCTRL_SWRST | S5P_CIGCTRL_IRQ_LEVEL);
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writel(cfg, dev->regs + S5P_CIGCTRL);
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udelay(1000);
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cfg = readl(dev->regs + S5P_CIGCTRL);
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cfg &= ~S5P_CIGCTRL_SWRST;
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writel(cfg, dev->regs + S5P_CIGCTRL);
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}
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static u32 fimc_hw_get_in_flip(u32 ctx_flip)
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{
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u32 flip = S5P_MSCTRL_FLIP_NORMAL;
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switch (ctx_flip) {
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case FLIP_X_AXIS:
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flip = S5P_MSCTRL_FLIP_X_MIRROR;
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break;
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case FLIP_Y_AXIS:
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flip = S5P_MSCTRL_FLIP_Y_MIRROR;
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break;
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case FLIP_XY_AXIS:
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flip = S5P_MSCTRL_FLIP_180;
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break;
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}
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return flip;
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}
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static u32 fimc_hw_get_target_flip(u32 ctx_flip)
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{
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u32 flip = S5P_CITRGFMT_FLIP_NORMAL;
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switch (ctx_flip) {
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case FLIP_X_AXIS:
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flip = S5P_CITRGFMT_FLIP_X_MIRROR;
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break;
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case FLIP_Y_AXIS:
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flip = S5P_CITRGFMT_FLIP_Y_MIRROR;
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break;
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case FLIP_XY_AXIS:
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flip = S5P_CITRGFMT_FLIP_180;
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break;
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case FLIP_NONE:
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break;
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}
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return flip;
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}
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void fimc_hw_set_rotation(struct fimc_ctx *ctx)
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{
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u32 cfg, flip;
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struct fimc_dev *dev = ctx->fimc_dev;
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cfg = readl(dev->regs + S5P_CITRGFMT);
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cfg &= ~(S5P_CITRGFMT_INROT90 | S5P_CITRGFMT_OUTROT90 |
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S5P_CITRGFMT_FLIP_180);
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flip = readl(dev->regs + S5P_MSCTRL);
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flip &= ~S5P_MSCTRL_FLIP_MASK;
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/*
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* The input and output rotator cannot work simultaneously.
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* Use the output rotator in output DMA mode or the input rotator
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* in direct fifo output mode.
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*/
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if (ctx->rotation == 90 || ctx->rotation == 270) {
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if (ctx->out_path == FIMC_LCDFIFO) {
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cfg |= S5P_CITRGFMT_INROT90;
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if (ctx->rotation == 270)
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flip |= S5P_MSCTRL_FLIP_180;
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} else {
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cfg |= S5P_CITRGFMT_OUTROT90;
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if (ctx->rotation == 270)
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cfg |= S5P_CITRGFMT_FLIP_180;
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}
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} else if (ctx->rotation == 180) {
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if (ctx->out_path == FIMC_LCDFIFO)
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flip |= S5P_MSCTRL_FLIP_180;
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else
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cfg |= S5P_CITRGFMT_FLIP_180;
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}
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if (ctx->rotation == 180 || ctx->rotation == 270)
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writel(flip, dev->regs + S5P_MSCTRL);
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cfg |= fimc_hw_get_target_flip(ctx->flip);
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writel(cfg, dev->regs + S5P_CITRGFMT);
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}
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void fimc_hw_set_target_format(struct fimc_ctx *ctx)
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{
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u32 cfg;
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struct fimc_dev *dev = ctx->fimc_dev;
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struct fimc_frame *frame = &ctx->d_frame;
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dbg("w= %d, h= %d color: %d", frame->width,
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frame->height, frame->fmt->color);
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cfg = readl(dev->regs + S5P_CITRGFMT);
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cfg &= ~(S5P_CITRGFMT_FMT_MASK | S5P_CITRGFMT_HSIZE_MASK |
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S5P_CITRGFMT_VSIZE_MASK);
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switch (frame->fmt->color) {
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case S5P_FIMC_RGB565:
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case S5P_FIMC_RGB666:
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case S5P_FIMC_RGB888:
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cfg |= S5P_CITRGFMT_RGB;
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break;
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case S5P_FIMC_YCBCR420:
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cfg |= S5P_CITRGFMT_YCBCR420;
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break;
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case S5P_FIMC_YCBYCR422:
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case S5P_FIMC_YCRYCB422:
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case S5P_FIMC_CBYCRY422:
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case S5P_FIMC_CRYCBY422:
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if (frame->fmt->planes_cnt == 1)
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cfg |= S5P_CITRGFMT_YCBCR422_1P;
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else
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cfg |= S5P_CITRGFMT_YCBCR422;
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break;
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default:
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break;
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}
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if (ctx->rotation == 90 || ctx->rotation == 270) {
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cfg |= S5P_CITRGFMT_HSIZE(frame->height);
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cfg |= S5P_CITRGFMT_VSIZE(frame->width);
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} else {
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cfg |= S5P_CITRGFMT_HSIZE(frame->width);
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cfg |= S5P_CITRGFMT_VSIZE(frame->height);
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}
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writel(cfg, dev->regs + S5P_CITRGFMT);
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cfg = readl(dev->regs + S5P_CITAREA) & ~S5P_CITAREA_MASK;
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cfg |= (frame->width * frame->height);
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writel(cfg, dev->regs + S5P_CITAREA);
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}
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static void fimc_hw_set_out_dma_size(struct fimc_ctx *ctx)
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{
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struct fimc_dev *dev = ctx->fimc_dev;
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struct fimc_frame *frame = &ctx->d_frame;
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u32 cfg;
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cfg = S5P_ORIG_SIZE_HOR(frame->f_width);
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cfg |= S5P_ORIG_SIZE_VER(frame->f_height);
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writel(cfg, dev->regs + S5P_ORGOSIZE);
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}
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void fimc_hw_set_out_dma(struct fimc_ctx *ctx)
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{
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u32 cfg;
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struct fimc_dev *dev = ctx->fimc_dev;
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struct fimc_frame *frame = &ctx->d_frame;
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struct fimc_dma_offset *offset = &frame->dma_offset;
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/* Set the input dma offsets. */
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cfg = 0;
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cfg |= S5P_CIO_OFFS_HOR(offset->y_h);
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cfg |= S5P_CIO_OFFS_VER(offset->y_v);
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writel(cfg, dev->regs + S5P_CIOYOFF);
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cfg = 0;
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cfg |= S5P_CIO_OFFS_HOR(offset->cb_h);
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cfg |= S5P_CIO_OFFS_VER(offset->cb_v);
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writel(cfg, dev->regs + S5P_CIOCBOFF);
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cfg = 0;
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cfg |= S5P_CIO_OFFS_HOR(offset->cr_h);
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cfg |= S5P_CIO_OFFS_VER(offset->cr_v);
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writel(cfg, dev->regs + S5P_CIOCROFF);
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fimc_hw_set_out_dma_size(ctx);
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/* Configure chroma components order. */
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cfg = readl(dev->regs + S5P_CIOCTRL);
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cfg &= ~(S5P_CIOCTRL_ORDER2P_MASK | S5P_CIOCTRL_ORDER422_MASK |
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S5P_CIOCTRL_YCBCR_PLANE_MASK);
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if (frame->fmt->planes_cnt == 1)
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cfg |= ctx->out_order_1p;
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else if (frame->fmt->planes_cnt == 2)
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cfg |= ctx->out_order_2p | S5P_CIOCTRL_YCBCR_2PLANE;
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else if (frame->fmt->planes_cnt == 3)
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cfg |= S5P_CIOCTRL_YCBCR_3PLANE;
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writel(cfg, dev->regs + S5P_CIOCTRL);
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}
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static void fimc_hw_en_autoload(struct fimc_dev *dev, int enable)
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{
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u32 cfg = readl(dev->regs + S5P_ORGISIZE);
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if (enable)
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cfg |= S5P_CIREAL_ISIZE_AUTOLOAD_EN;
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else
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cfg &= ~S5P_CIREAL_ISIZE_AUTOLOAD_EN;
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writel(cfg, dev->regs + S5P_ORGISIZE);
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}
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void fimc_hw_en_lastirq(struct fimc_dev *dev, int enable)
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{
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unsigned long flags;
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u32 cfg;
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spin_lock_irqsave(&dev->slock, flags);
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cfg = readl(dev->regs + S5P_CIOCTRL);
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if (enable)
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cfg |= S5P_CIOCTRL_LASTIRQ_ENABLE;
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else
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cfg &= ~S5P_CIOCTRL_LASTIRQ_ENABLE;
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writel(cfg, dev->regs + S5P_CIOCTRL);
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spin_unlock_irqrestore(&dev->slock, flags);
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}
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static void fimc_hw_set_prescaler(struct fimc_ctx *ctx)
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{
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struct fimc_dev *dev = ctx->fimc_dev;
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struct fimc_scaler *sc = &ctx->scaler;
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u32 cfg, shfactor;
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shfactor = 10 - (sc->hfactor + sc->vfactor);
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cfg = S5P_CISCPRERATIO_SHFACTOR(shfactor);
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cfg |= S5P_CISCPRERATIO_HOR(sc->pre_hratio);
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cfg |= S5P_CISCPRERATIO_VER(sc->pre_vratio);
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writel(cfg, dev->regs + S5P_CISCPRERATIO);
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cfg = S5P_CISCPREDST_WIDTH(sc->pre_dst_width);
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cfg |= S5P_CISCPREDST_HEIGHT(sc->pre_dst_height);
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writel(cfg, dev->regs + S5P_CISCPREDST);
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}
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void fimc_hw_set_scaler(struct fimc_ctx *ctx)
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{
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struct fimc_dev *dev = ctx->fimc_dev;
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struct fimc_scaler *sc = &ctx->scaler;
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struct fimc_frame *src_frame = &ctx->s_frame;
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struct fimc_frame *dst_frame = &ctx->d_frame;
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u32 cfg = 0;
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fimc_hw_set_prescaler(ctx);
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if (!(ctx->flags & FIMC_COLOR_RANGE_NARROW))
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cfg |= (S5P_CISCCTRL_CSCR2Y_WIDE | S5P_CISCCTRL_CSCY2R_WIDE);
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if (!sc->enabled)
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cfg |= S5P_CISCCTRL_SCALERBYPASS;
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if (sc->scaleup_h)
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cfg |= S5P_CISCCTRL_SCALEUP_H;
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if (sc->scaleup_v)
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cfg |= S5P_CISCCTRL_SCALEUP_V;
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if (sc->copy_mode)
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cfg |= S5P_CISCCTRL_ONE2ONE;
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if (ctx->in_path == FIMC_DMA) {
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if (src_frame->fmt->color == S5P_FIMC_RGB565)
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cfg |= S5P_CISCCTRL_INRGB_FMT_RGB565;
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else if (src_frame->fmt->color == S5P_FIMC_RGB666)
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cfg |= S5P_CISCCTRL_INRGB_FMT_RGB666;
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else if (src_frame->fmt->color == S5P_FIMC_RGB888)
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cfg |= S5P_CISCCTRL_INRGB_FMT_RGB888;
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}
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if (ctx->out_path == FIMC_DMA) {
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if (dst_frame->fmt->color == S5P_FIMC_RGB565)
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cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB565;
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else if (dst_frame->fmt->color == S5P_FIMC_RGB666)
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cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB666;
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else if (dst_frame->fmt->color == S5P_FIMC_RGB888)
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cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB888;
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} else {
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cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB888;
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if (ctx->flags & FIMC_SCAN_MODE_INTERLACED)
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cfg |= S5P_CISCCTRL_INTERLACE;
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}
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dbg("main_hratio= 0x%X main_vratio= 0x%X",
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sc->main_hratio, sc->main_vratio);
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cfg |= S5P_CISCCTRL_SC_HORRATIO(sc->main_hratio);
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cfg |= S5P_CISCCTRL_SC_VERRATIO(sc->main_vratio);
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writel(cfg, dev->regs + S5P_CISCCTRL);
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}
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void fimc_hw_en_capture(struct fimc_ctx *ctx)
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{
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struct fimc_dev *dev = ctx->fimc_dev;
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u32 cfg;
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cfg = readl(dev->regs + S5P_CIIMGCPT);
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/* One shot mode for output DMA or freerun for FIFO. */
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if (ctx->out_path == FIMC_DMA)
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cfg |= S5P_CIIMGCPT_CPT_FREN_ENABLE;
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else
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cfg &= ~S5P_CIIMGCPT_CPT_FREN_ENABLE;
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if (ctx->scaler.enabled)
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cfg |= S5P_CIIMGCPT_IMGCPTEN_SC;
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writel(cfg | S5P_CIIMGCPT_IMGCPTEN, dev->regs + S5P_CIIMGCPT);
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}
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void fimc_hw_set_effect(struct fimc_ctx *ctx)
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{
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struct fimc_dev *dev = ctx->fimc_dev;
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struct fimc_effect *effect = &ctx->effect;
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u32 cfg = (S5P_CIIMGEFF_IE_ENABLE | S5P_CIIMGEFF_IE_SC_AFTER);
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cfg |= effect->type;
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if (effect->type == S5P_FIMC_EFFECT_ARBITRARY) {
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cfg |= S5P_CIIMGEFF_PAT_CB(effect->pat_cb);
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cfg |= S5P_CIIMGEFF_PAT_CR(effect->pat_cr);
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}
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writel(cfg, dev->regs + S5P_CIIMGEFF);
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}
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static void fimc_hw_set_in_dma_size(struct fimc_ctx *ctx)
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{
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struct fimc_dev *dev = ctx->fimc_dev;
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struct fimc_frame *frame = &ctx->s_frame;
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u32 cfg_o = 0;
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u32 cfg_r = 0;
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if (FIMC_LCDFIFO == ctx->out_path)
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cfg_r |= S5P_CIREAL_ISIZE_AUTOLOAD_EN;
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cfg_o |= S5P_ORIG_SIZE_HOR(frame->f_width);
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cfg_o |= S5P_ORIG_SIZE_VER(frame->f_height);
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cfg_r |= S5P_CIREAL_ISIZE_WIDTH(frame->width);
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cfg_r |= S5P_CIREAL_ISIZE_HEIGHT(frame->height);
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writel(cfg_o, dev->regs + S5P_ORGISIZE);
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writel(cfg_r, dev->regs + S5P_CIREAL_ISIZE);
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}
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void fimc_hw_set_in_dma(struct fimc_ctx *ctx)
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{
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struct fimc_dev *dev = ctx->fimc_dev;
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struct fimc_frame *frame = &ctx->s_frame;
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struct fimc_dma_offset *offset = &frame->dma_offset;
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u32 cfg;
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/* Set the pixel offsets. */
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cfg = S5P_CIO_OFFS_HOR(offset->y_h);
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cfg |= S5P_CIO_OFFS_VER(offset->y_v);
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writel(cfg, dev->regs + S5P_CIIYOFF);
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cfg = S5P_CIO_OFFS_HOR(offset->cb_h);
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cfg |= S5P_CIO_OFFS_VER(offset->cb_v);
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writel(cfg, dev->regs + S5P_CIICBOFF);
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cfg = S5P_CIO_OFFS_HOR(offset->cr_h);
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cfg |= S5P_CIO_OFFS_VER(offset->cr_v);
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writel(cfg, dev->regs + S5P_CIICROFF);
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/* Input original and real size. */
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fimc_hw_set_in_dma_size(ctx);
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/* Use DMA autoload only in FIFO mode. */
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fimc_hw_en_autoload(dev, ctx->out_path == FIMC_LCDFIFO);
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/* Set the input DMA to process single frame only. */
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cfg = readl(dev->regs + S5P_MSCTRL);
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cfg &= ~(S5P_MSCTRL_FLIP_MASK
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| S5P_MSCTRL_INFORMAT_MASK
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| S5P_MSCTRL_IN_BURST_COUNT_MASK
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| S5P_MSCTRL_INPUT_MASK
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| S5P_MSCTRL_C_INT_IN_MASK
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| S5P_MSCTRL_2P_IN_ORDER_MASK);
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cfg |= (S5P_MSCTRL_FRAME_COUNT(1) | S5P_MSCTRL_INPUT_MEMORY);
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switch (frame->fmt->color) {
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case S5P_FIMC_RGB565:
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case S5P_FIMC_RGB666:
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case S5P_FIMC_RGB888:
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cfg |= S5P_MSCTRL_INFORMAT_RGB;
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break;
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case S5P_FIMC_YCBCR420:
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cfg |= S5P_MSCTRL_INFORMAT_YCBCR420;
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if (frame->fmt->planes_cnt == 2)
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cfg |= ctx->in_order_2p | S5P_MSCTRL_C_INT_IN_2PLANE;
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else
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cfg |= S5P_MSCTRL_C_INT_IN_3PLANE;
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break;
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case S5P_FIMC_YCBYCR422:
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case S5P_FIMC_YCRYCB422:
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case S5P_FIMC_CBYCRY422:
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case S5P_FIMC_CRYCBY422:
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if (frame->fmt->planes_cnt == 1) {
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cfg |= ctx->in_order_1p
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| S5P_MSCTRL_INFORMAT_YCBCR422_1P;
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} else {
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cfg |= S5P_MSCTRL_INFORMAT_YCBCR422;
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if (frame->fmt->planes_cnt == 2)
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cfg |= ctx->in_order_2p
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| S5P_MSCTRL_C_INT_IN_2PLANE;
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else
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cfg |= S5P_MSCTRL_C_INT_IN_3PLANE;
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}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* Input DMA flip mode (and rotation).
|
|
* Do not allow simultaneous rotation and flipping.
|
|
*/
|
|
if (!ctx->rotation && ctx->out_path == FIMC_LCDFIFO)
|
|
cfg |= fimc_hw_get_in_flip(ctx->flip);
|
|
|
|
writel(cfg, dev->regs + S5P_MSCTRL);
|
|
|
|
/* Input/output DMA linear/tiled mode. */
|
|
cfg = readl(dev->regs + S5P_CIDMAPARAM);
|
|
cfg &= ~S5P_CIDMAPARAM_TILE_MASK;
|
|
|
|
if (tiled_fmt(ctx->s_frame.fmt))
|
|
cfg |= S5P_CIDMAPARAM_R_64X32;
|
|
|
|
if (tiled_fmt(ctx->d_frame.fmt))
|
|
cfg |= S5P_CIDMAPARAM_W_64X32;
|
|
|
|
writel(cfg, dev->regs + S5P_CIDMAPARAM);
|
|
}
|
|
|
|
|
|
void fimc_hw_set_input_path(struct fimc_ctx *ctx)
|
|
{
|
|
struct fimc_dev *dev = ctx->fimc_dev;
|
|
|
|
u32 cfg = readl(dev->regs + S5P_MSCTRL);
|
|
cfg &= ~S5P_MSCTRL_INPUT_MASK;
|
|
|
|
if (ctx->in_path == FIMC_DMA)
|
|
cfg |= S5P_MSCTRL_INPUT_MEMORY;
|
|
else
|
|
cfg |= S5P_MSCTRL_INPUT_EXTCAM;
|
|
|
|
writel(cfg, dev->regs + S5P_MSCTRL);
|
|
}
|
|
|
|
void fimc_hw_set_output_path(struct fimc_ctx *ctx)
|
|
{
|
|
struct fimc_dev *dev = ctx->fimc_dev;
|
|
|
|
u32 cfg = readl(dev->regs + S5P_CISCCTRL);
|
|
cfg &= ~S5P_CISCCTRL_LCDPATHEN_FIFO;
|
|
if (ctx->out_path == FIMC_LCDFIFO)
|
|
cfg |= S5P_CISCCTRL_LCDPATHEN_FIFO;
|
|
writel(cfg, dev->regs + S5P_CISCCTRL);
|
|
}
|
|
|
|
void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *paddr)
|
|
{
|
|
u32 cfg = readl(dev->regs + S5P_CIREAL_ISIZE);
|
|
cfg |= S5P_CIREAL_ISIZE_ADDR_CH_DIS;
|
|
writel(cfg, dev->regs + S5P_CIREAL_ISIZE);
|
|
|
|
writel(paddr->y, dev->regs + S5P_CIIYSA(0));
|
|
writel(paddr->cb, dev->regs + S5P_CIICBSA(0));
|
|
writel(paddr->cr, dev->regs + S5P_CIICRSA(0));
|
|
|
|
cfg &= ~S5P_CIREAL_ISIZE_ADDR_CH_DIS;
|
|
writel(cfg, dev->regs + S5P_CIREAL_ISIZE);
|
|
}
|
|
|
|
void fimc_hw_set_output_addr(struct fimc_dev *dev,
|
|
struct fimc_addr *paddr, int index)
|
|
{
|
|
int i = (index == -1) ? 0 : index;
|
|
do {
|
|
writel(paddr->y, dev->regs + S5P_CIOYSA(i));
|
|
writel(paddr->cb, dev->regs + S5P_CIOCBSA(i));
|
|
writel(paddr->cr, dev->regs + S5P_CIOCRSA(i));
|
|
dbg("dst_buf[%d]: 0x%X, cb: 0x%X, cr: 0x%X",
|
|
i, paddr->y, paddr->cb, paddr->cr);
|
|
} while (index == -1 && ++i < FIMC_MAX_OUT_BUFS);
|
|
}
|