mirror of https://gitee.com/openkylin/linux.git
1016 lines
27 KiB
C
1016 lines
27 KiB
C
/*
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* Copyright (C) 1991, 1992 Linus Torvalds
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* Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
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*
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* Pentium III FXSR, SSE support
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* Gareth Hughes <gareth@valinux.com>, May 2000
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*/
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/*
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* Handle hardware traps and faults.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/context_tracking.h>
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#include <linux/interrupt.h>
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#include <linux/kallsyms.h>
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#include <linux/spinlock.h>
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#include <linux/kprobes.h>
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#include <linux/uaccess.h>
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#include <linux/kdebug.h>
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#include <linux/kgdb.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/ptrace.h>
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#include <linux/uprobes.h>
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#include <linux/string.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/kexec.h>
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#include <linux/sched.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/bug.h>
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#include <linux/nmi.h>
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#include <linux/mm.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#ifdef CONFIG_EISA
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#include <linux/ioport.h>
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#include <linux/eisa.h>
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#endif
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#if defined(CONFIG_EDAC)
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#include <linux/edac.h>
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#endif
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#include <asm/kmemcheck.h>
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#include <asm/stacktrace.h>
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#include <asm/processor.h>
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#include <asm/debugreg.h>
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#include <linux/atomic.h>
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#include <asm/ftrace.h>
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#include <asm/traps.h>
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#include <asm/desc.h>
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#include <asm/i387.h>
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#include <asm/fpu-internal.h>
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#include <asm/mce.h>
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#include <asm/fixmap.h>
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#include <asm/mach_traps.h>
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#include <asm/alternative.h>
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#include <asm/mpx.h>
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#ifdef CONFIG_X86_64
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#include <asm/x86_init.h>
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#include <asm/pgalloc.h>
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#include <asm/proto.h>
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/* No need to be aligned, but done to keep all IDTs defined the same way. */
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gate_desc debug_idt_table[NR_VECTORS] __page_aligned_bss;
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#else
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#include <asm/processor-flags.h>
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#include <asm/setup.h>
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asmlinkage int system_call(void);
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#endif
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/* Must be page-aligned because the real IDT is used in a fixmap. */
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gate_desc idt_table[NR_VECTORS] __page_aligned_bss;
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DECLARE_BITMAP(used_vectors, NR_VECTORS);
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EXPORT_SYMBOL_GPL(used_vectors);
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static inline void conditional_sti(struct pt_regs *regs)
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{
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if (regs->flags & X86_EFLAGS_IF)
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local_irq_enable();
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}
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static inline void preempt_conditional_sti(struct pt_regs *regs)
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{
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preempt_count_inc();
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if (regs->flags & X86_EFLAGS_IF)
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local_irq_enable();
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}
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static inline void conditional_cli(struct pt_regs *regs)
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{
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if (regs->flags & X86_EFLAGS_IF)
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local_irq_disable();
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}
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static inline void preempt_conditional_cli(struct pt_regs *regs)
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{
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if (regs->flags & X86_EFLAGS_IF)
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local_irq_disable();
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preempt_count_dec();
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}
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enum ctx_state ist_enter(struct pt_regs *regs)
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{
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enum ctx_state prev_state;
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if (user_mode_vm(regs)) {
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/* Other than that, we're just an exception. */
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prev_state = exception_enter();
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} else {
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/*
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* We might have interrupted pretty much anything. In
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* fact, if we're a machine check, we can even interrupt
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* NMI processing. We don't want in_nmi() to return true,
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* but we need to notify RCU.
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*/
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rcu_nmi_enter();
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prev_state = IN_KERNEL; /* the value is irrelevant. */
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}
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/*
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* We are atomic because we're on the IST stack (or we're on x86_32,
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* in which case we still shouldn't schedule).
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*
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* This must be after exception_enter(), because exception_enter()
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* won't do anything if in_interrupt() returns true.
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*/
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preempt_count_add(HARDIRQ_OFFSET);
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/* This code is a bit fragile. Test it. */
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rcu_lockdep_assert(rcu_is_watching(), "ist_enter didn't work");
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return prev_state;
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}
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void ist_exit(struct pt_regs *regs, enum ctx_state prev_state)
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{
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/* Must be before exception_exit. */
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preempt_count_sub(HARDIRQ_OFFSET);
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if (user_mode_vm(regs))
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return exception_exit(prev_state);
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else
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rcu_nmi_exit();
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}
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/**
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* ist_begin_non_atomic() - begin a non-atomic section in an IST exception
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* @regs: regs passed to the IST exception handler
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*
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* IST exception handlers normally cannot schedule. As a special
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* exception, if the exception interrupted userspace code (i.e.
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* user_mode_vm(regs) would return true) and the exception was not
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* a double fault, it can be safe to schedule. ist_begin_non_atomic()
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* begins a non-atomic section within an ist_enter()/ist_exit() region.
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* Callers are responsible for enabling interrupts themselves inside
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* the non-atomic section, and callers must call is_end_non_atomic()
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* before ist_exit().
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*/
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void ist_begin_non_atomic(struct pt_regs *regs)
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{
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BUG_ON(!user_mode_vm(regs));
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/*
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* Sanity check: we need to be on the normal thread stack. This
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* will catch asm bugs and any attempt to use ist_preempt_enable
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* from double_fault.
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*/
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BUG_ON(((current_stack_pointer() ^ this_cpu_read_stable(kernel_stack))
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& ~(THREAD_SIZE - 1)) != 0);
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preempt_count_sub(HARDIRQ_OFFSET);
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}
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/**
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* ist_end_non_atomic() - begin a non-atomic section in an IST exception
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*
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* Ends a non-atomic section started with ist_begin_non_atomic().
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*/
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void ist_end_non_atomic(void)
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{
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preempt_count_add(HARDIRQ_OFFSET);
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}
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static nokprobe_inline int
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do_trap_no_signal(struct task_struct *tsk, int trapnr, char *str,
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struct pt_regs *regs, long error_code)
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{
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#ifdef CONFIG_X86_32
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if (regs->flags & X86_VM_MASK) {
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/*
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* Traps 0, 1, 3, 4, and 5 should be forwarded to vm86.
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* On nmi (interrupt 2), do_trap should not be called.
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*/
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if (trapnr < X86_TRAP_UD) {
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if (!handle_vm86_trap((struct kernel_vm86_regs *) regs,
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error_code, trapnr))
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return 0;
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}
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return -1;
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}
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#endif
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if (!user_mode(regs)) {
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if (!fixup_exception(regs)) {
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tsk->thread.error_code = error_code;
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tsk->thread.trap_nr = trapnr;
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die(str, regs, error_code);
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}
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return 0;
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}
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return -1;
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}
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static siginfo_t *fill_trap_info(struct pt_regs *regs, int signr, int trapnr,
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siginfo_t *info)
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{
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unsigned long siaddr;
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int sicode;
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switch (trapnr) {
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default:
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return SEND_SIG_PRIV;
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case X86_TRAP_DE:
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sicode = FPE_INTDIV;
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siaddr = uprobe_get_trap_addr(regs);
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break;
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case X86_TRAP_UD:
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sicode = ILL_ILLOPN;
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siaddr = uprobe_get_trap_addr(regs);
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break;
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case X86_TRAP_AC:
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sicode = BUS_ADRALN;
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siaddr = 0;
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break;
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}
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info->si_signo = signr;
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info->si_errno = 0;
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info->si_code = sicode;
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info->si_addr = (void __user *)siaddr;
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return info;
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}
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static void
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do_trap(int trapnr, int signr, char *str, struct pt_regs *regs,
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long error_code, siginfo_t *info)
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{
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struct task_struct *tsk = current;
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if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code))
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return;
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/*
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* We want error_code and trap_nr set for userspace faults and
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* kernelspace faults which result in die(), but not
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* kernelspace faults which are fixed up. die() gives the
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* process no chance to handle the signal and notice the
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* kernel fault information, so that won't result in polluting
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* the information about previously queued, but not yet
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* delivered, faults. See also do_general_protection below.
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*/
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tsk->thread.error_code = error_code;
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tsk->thread.trap_nr = trapnr;
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#ifdef CONFIG_X86_64
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if (show_unhandled_signals && unhandled_signal(tsk, signr) &&
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printk_ratelimit()) {
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pr_info("%s[%d] trap %s ip:%lx sp:%lx error:%lx",
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tsk->comm, tsk->pid, str,
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regs->ip, regs->sp, error_code);
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print_vma_addr(" in ", regs->ip);
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pr_cont("\n");
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}
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#endif
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force_sig_info(signr, info ?: SEND_SIG_PRIV, tsk);
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}
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NOKPROBE_SYMBOL(do_trap);
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static void do_error_trap(struct pt_regs *regs, long error_code, char *str,
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unsigned long trapnr, int signr)
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{
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enum ctx_state prev_state = exception_enter();
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siginfo_t info;
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if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) !=
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NOTIFY_STOP) {
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conditional_sti(regs);
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do_trap(trapnr, signr, str, regs, error_code,
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fill_trap_info(regs, signr, trapnr, &info));
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}
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exception_exit(prev_state);
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}
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#define DO_ERROR(trapnr, signr, str, name) \
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dotraplinkage void do_##name(struct pt_regs *regs, long error_code) \
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{ \
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do_error_trap(regs, error_code, str, trapnr, signr); \
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}
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DO_ERROR(X86_TRAP_DE, SIGFPE, "divide error", divide_error)
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DO_ERROR(X86_TRAP_OF, SIGSEGV, "overflow", overflow)
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DO_ERROR(X86_TRAP_UD, SIGILL, "invalid opcode", invalid_op)
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DO_ERROR(X86_TRAP_OLD_MF, SIGFPE, "coprocessor segment overrun",coprocessor_segment_overrun)
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DO_ERROR(X86_TRAP_TS, SIGSEGV, "invalid TSS", invalid_TSS)
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DO_ERROR(X86_TRAP_NP, SIGBUS, "segment not present", segment_not_present)
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DO_ERROR(X86_TRAP_SS, SIGBUS, "stack segment", stack_segment)
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DO_ERROR(X86_TRAP_AC, SIGBUS, "alignment check", alignment_check)
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#ifdef CONFIG_X86_64
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/* Runs on IST stack */
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dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code)
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{
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static const char str[] = "double fault";
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struct task_struct *tsk = current;
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#ifdef CONFIG_X86_ESPFIX64
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extern unsigned char native_irq_return_iret[];
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/*
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* If IRET takes a non-IST fault on the espfix64 stack, then we
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* end up promoting it to a doublefault. In that case, modify
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* the stack to make it look like we just entered the #GP
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* handler from user space, similar to bad_iret.
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*
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* No need for ist_enter here because we don't use RCU.
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*/
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if (((long)regs->sp >> PGDIR_SHIFT) == ESPFIX_PGD_ENTRY &&
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regs->cs == __KERNEL_CS &&
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regs->ip == (unsigned long)native_irq_return_iret)
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{
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struct pt_regs *normal_regs = task_pt_regs(current);
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/* Fake a #GP(0) from userspace. */
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memmove(&normal_regs->ip, (void *)regs->sp, 5*8);
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normal_regs->orig_ax = 0; /* Missing (lost) #GP error code */
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regs->ip = (unsigned long)general_protection;
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regs->sp = (unsigned long)&normal_regs->orig_ax;
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return;
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}
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#endif
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ist_enter(regs); /* Discard prev_state because we won't return. */
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notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV);
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tsk->thread.error_code = error_code;
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tsk->thread.trap_nr = X86_TRAP_DF;
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#ifdef CONFIG_DOUBLEFAULT
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df_debug(regs, error_code);
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#endif
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/*
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* This is always a kernel trap and never fixable (and thus must
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* never return).
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*/
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for (;;)
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die(str, regs, error_code);
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}
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#endif
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dotraplinkage void do_bounds(struct pt_regs *regs, long error_code)
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{
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struct task_struct *tsk = current;
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struct xsave_struct *xsave_buf;
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enum ctx_state prev_state;
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struct bndcsr *bndcsr;
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siginfo_t *info;
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prev_state = exception_enter();
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if (notify_die(DIE_TRAP, "bounds", regs, error_code,
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X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP)
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goto exit;
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conditional_sti(regs);
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if (!user_mode(regs))
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die("bounds", regs, error_code);
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if (!cpu_feature_enabled(X86_FEATURE_MPX)) {
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/* The exception is not from Intel MPX */
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goto exit_trap;
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}
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/*
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* We need to look at BNDSTATUS to resolve this exception.
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* It is not directly accessible, though, so we need to
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* do an xsave and then pull it out of the xsave buffer.
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*/
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fpu_save_init(&tsk->thread.fpu);
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xsave_buf = &(tsk->thread.fpu.state->xsave);
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bndcsr = get_xsave_addr(xsave_buf, XSTATE_BNDCSR);
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if (!bndcsr)
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goto exit_trap;
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/*
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* The error code field of the BNDSTATUS register communicates status
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* information of a bound range exception #BR or operation involving
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* bound directory.
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*/
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switch (bndcsr->bndstatus & MPX_BNDSTA_ERROR_CODE) {
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case 2: /* Bound directory has invalid entry. */
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if (mpx_handle_bd_fault(xsave_buf))
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goto exit_trap;
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break; /* Success, it was handled */
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case 1: /* Bound violation. */
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info = mpx_generate_siginfo(regs, xsave_buf);
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if (IS_ERR(info)) {
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/*
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* We failed to decode the MPX instruction. Act as if
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* the exception was not caused by MPX.
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*/
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goto exit_trap;
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}
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/*
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* Success, we decoded the instruction and retrieved
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* an 'info' containing the address being accessed
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* which caused the exception. This information
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* allows and application to possibly handle the
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* #BR exception itself.
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*/
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do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, error_code, info);
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kfree(info);
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break;
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case 0: /* No exception caused by Intel MPX operations. */
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goto exit_trap;
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default:
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die("bounds", regs, error_code);
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}
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exit:
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exception_exit(prev_state);
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return;
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exit_trap:
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/*
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* This path out is for all the cases where we could not
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* handle the exception in some way (like allocating a
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* table or telling userspace about it. We will also end
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* up here if the kernel has MPX turned off at compile
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* time..
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*/
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do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, error_code, NULL);
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exception_exit(prev_state);
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}
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dotraplinkage void
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do_general_protection(struct pt_regs *regs, long error_code)
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{
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struct task_struct *tsk;
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enum ctx_state prev_state;
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prev_state = exception_enter();
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conditional_sti(regs);
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#ifdef CONFIG_X86_32
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if (regs->flags & X86_VM_MASK) {
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local_irq_enable();
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handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code);
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goto exit;
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}
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#endif
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tsk = current;
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if (!user_mode(regs)) {
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if (fixup_exception(regs))
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goto exit;
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tsk->thread.error_code = error_code;
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tsk->thread.trap_nr = X86_TRAP_GP;
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if (notify_die(DIE_GPF, "general protection fault", regs, error_code,
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X86_TRAP_GP, SIGSEGV) != NOTIFY_STOP)
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die("general protection fault", regs, error_code);
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goto exit;
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}
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tsk->thread.error_code = error_code;
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tsk->thread.trap_nr = X86_TRAP_GP;
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if (show_unhandled_signals && unhandled_signal(tsk, SIGSEGV) &&
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printk_ratelimit()) {
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pr_info("%s[%d] general protection ip:%lx sp:%lx error:%lx",
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tsk->comm, task_pid_nr(tsk),
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regs->ip, regs->sp, error_code);
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print_vma_addr(" in ", regs->ip);
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pr_cont("\n");
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}
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force_sig_info(SIGSEGV, SEND_SIG_PRIV, tsk);
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exit:
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exception_exit(prev_state);
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}
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|
NOKPROBE_SYMBOL(do_general_protection);
|
|
|
|
/* May run on IST stack. */
|
|
dotraplinkage void notrace do_int3(struct pt_regs *regs, long error_code)
|
|
{
|
|
enum ctx_state prev_state;
|
|
|
|
#ifdef CONFIG_DYNAMIC_FTRACE
|
|
/*
|
|
* ftrace must be first, everything else may cause a recursive crash.
|
|
* See note by declaration of modifying_ftrace_code in ftrace.c
|
|
*/
|
|
if (unlikely(atomic_read(&modifying_ftrace_code)) &&
|
|
ftrace_int3_handler(regs))
|
|
return;
|
|
#endif
|
|
if (poke_int3_handler(regs))
|
|
return;
|
|
|
|
prev_state = ist_enter(regs);
|
|
#ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
|
|
if (kgdb_ll_trap(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP,
|
|
SIGTRAP) == NOTIFY_STOP)
|
|
goto exit;
|
|
#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
|
|
|
|
#ifdef CONFIG_KPROBES
|
|
if (kprobe_int3_handler(regs))
|
|
goto exit;
|
|
#endif
|
|
|
|
if (notify_die(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP,
|
|
SIGTRAP) == NOTIFY_STOP)
|
|
goto exit;
|
|
|
|
/*
|
|
* Let others (NMI) know that the debug stack is in use
|
|
* as we may switch to the interrupt stack.
|
|
*/
|
|
debug_stack_usage_inc();
|
|
preempt_conditional_sti(regs);
|
|
do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, error_code, NULL);
|
|
preempt_conditional_cli(regs);
|
|
debug_stack_usage_dec();
|
|
exit:
|
|
ist_exit(regs, prev_state);
|
|
}
|
|
NOKPROBE_SYMBOL(do_int3);
|
|
|
|
#ifdef CONFIG_X86_64
|
|
/*
|
|
* Help handler running on IST stack to switch off the IST stack if the
|
|
* interrupted code was in user mode. The actual stack switch is done in
|
|
* entry_64.S
|
|
*/
|
|
asmlinkage __visible notrace struct pt_regs *sync_regs(struct pt_regs *eregs)
|
|
{
|
|
struct pt_regs *regs = task_pt_regs(current);
|
|
*regs = *eregs;
|
|
return regs;
|
|
}
|
|
NOKPROBE_SYMBOL(sync_regs);
|
|
|
|
struct bad_iret_stack {
|
|
void *error_entry_ret;
|
|
struct pt_regs regs;
|
|
};
|
|
|
|
asmlinkage __visible notrace
|
|
struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s)
|
|
{
|
|
/*
|
|
* This is called from entry_64.S early in handling a fault
|
|
* caused by a bad iret to user mode. To handle the fault
|
|
* correctly, we want move our stack frame to task_pt_regs
|
|
* and we want to pretend that the exception came from the
|
|
* iret target.
|
|
*/
|
|
struct bad_iret_stack *new_stack =
|
|
container_of(task_pt_regs(current),
|
|
struct bad_iret_stack, regs);
|
|
|
|
/* Copy the IRET target to the new stack. */
|
|
memmove(&new_stack->regs.ip, (void *)s->regs.sp, 5*8);
|
|
|
|
/* Copy the remainder of the stack from the current stack. */
|
|
memmove(new_stack, s, offsetof(struct bad_iret_stack, regs.ip));
|
|
|
|
BUG_ON(!user_mode_vm(&new_stack->regs));
|
|
return new_stack;
|
|
}
|
|
NOKPROBE_SYMBOL(fixup_bad_iret);
|
|
#endif
|
|
|
|
/*
|
|
* Our handling of the processor debug registers is non-trivial.
|
|
* We do not clear them on entry and exit from the kernel. Therefore
|
|
* it is possible to get a watchpoint trap here from inside the kernel.
|
|
* However, the code in ./ptrace.c has ensured that the user can
|
|
* only set watchpoints on userspace addresses. Therefore the in-kernel
|
|
* watchpoint trap can only occur in code which is reading/writing
|
|
* from user space. Such code must not hold kernel locks (since it
|
|
* can equally take a page fault), therefore it is safe to call
|
|
* force_sig_info even though that claims and releases locks.
|
|
*
|
|
* Code in ./signal.c ensures that the debug control register
|
|
* is restored before we deliver any signal, and therefore that
|
|
* user code runs with the correct debug control register even though
|
|
* we clear it here.
|
|
*
|
|
* Being careful here means that we don't have to be as careful in a
|
|
* lot of more complicated places (task switching can be a bit lazy
|
|
* about restoring all the debug state, and ptrace doesn't have to
|
|
* find every occurrence of the TF bit that could be saved away even
|
|
* by user code)
|
|
*
|
|
* May run on IST stack.
|
|
*/
|
|
dotraplinkage void do_debug(struct pt_regs *regs, long error_code)
|
|
{
|
|
struct task_struct *tsk = current;
|
|
enum ctx_state prev_state;
|
|
int user_icebp = 0;
|
|
unsigned long dr6;
|
|
int si_code;
|
|
|
|
prev_state = ist_enter(regs);
|
|
|
|
get_debugreg(dr6, 6);
|
|
|
|
/* Filter out all the reserved bits which are preset to 1 */
|
|
dr6 &= ~DR6_RESERVED;
|
|
|
|
/*
|
|
* If dr6 has no reason to give us about the origin of this trap,
|
|
* then it's very likely the result of an icebp/int01 trap.
|
|
* User wants a sigtrap for that.
|
|
*/
|
|
if (!dr6 && user_mode(regs))
|
|
user_icebp = 1;
|
|
|
|
/* Catch kmemcheck conditions first of all! */
|
|
if ((dr6 & DR_STEP) && kmemcheck_trap(regs))
|
|
goto exit;
|
|
|
|
/* DR6 may or may not be cleared by the CPU */
|
|
set_debugreg(0, 6);
|
|
|
|
/*
|
|
* The processor cleared BTF, so don't mark that we need it set.
|
|
*/
|
|
clear_tsk_thread_flag(tsk, TIF_BLOCKSTEP);
|
|
|
|
/* Store the virtualized DR6 value */
|
|
tsk->thread.debugreg6 = dr6;
|
|
|
|
#ifdef CONFIG_KPROBES
|
|
if (kprobe_debug_handler(regs))
|
|
goto exit;
|
|
#endif
|
|
|
|
if (notify_die(DIE_DEBUG, "debug", regs, (long)&dr6, error_code,
|
|
SIGTRAP) == NOTIFY_STOP)
|
|
goto exit;
|
|
|
|
/*
|
|
* Let others (NMI) know that the debug stack is in use
|
|
* as we may switch to the interrupt stack.
|
|
*/
|
|
debug_stack_usage_inc();
|
|
|
|
/* It's safe to allow irq's after DR6 has been saved */
|
|
preempt_conditional_sti(regs);
|
|
|
|
if (regs->flags & X86_VM_MASK) {
|
|
handle_vm86_trap((struct kernel_vm86_regs *) regs, error_code,
|
|
X86_TRAP_DB);
|
|
preempt_conditional_cli(regs);
|
|
debug_stack_usage_dec();
|
|
goto exit;
|
|
}
|
|
|
|
/*
|
|
* Single-stepping through system calls: ignore any exceptions in
|
|
* kernel space, but re-enable TF when returning to user mode.
|
|
*
|
|
* We already checked v86 mode above, so we can check for kernel mode
|
|
* by just checking the CPL of CS.
|
|
*/
|
|
if ((dr6 & DR_STEP) && !user_mode(regs)) {
|
|
tsk->thread.debugreg6 &= ~DR_STEP;
|
|
set_tsk_thread_flag(tsk, TIF_SINGLESTEP);
|
|
regs->flags &= ~X86_EFLAGS_TF;
|
|
}
|
|
si_code = get_si_code(tsk->thread.debugreg6);
|
|
if (tsk->thread.debugreg6 & (DR_STEP | DR_TRAP_BITS) || user_icebp)
|
|
send_sigtrap(tsk, regs, error_code, si_code);
|
|
preempt_conditional_cli(regs);
|
|
debug_stack_usage_dec();
|
|
|
|
exit:
|
|
ist_exit(regs, prev_state);
|
|
}
|
|
NOKPROBE_SYMBOL(do_debug);
|
|
|
|
/*
|
|
* Note that we play around with the 'TS' bit in an attempt to get
|
|
* the correct behaviour even in the presence of the asynchronous
|
|
* IRQ13 behaviour
|
|
*/
|
|
static void math_error(struct pt_regs *regs, int error_code, int trapnr)
|
|
{
|
|
struct task_struct *task = current;
|
|
siginfo_t info;
|
|
unsigned short err;
|
|
char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" :
|
|
"simd exception";
|
|
|
|
if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, SIGFPE) == NOTIFY_STOP)
|
|
return;
|
|
conditional_sti(regs);
|
|
|
|
if (!user_mode_vm(regs))
|
|
{
|
|
if (!fixup_exception(regs)) {
|
|
task->thread.error_code = error_code;
|
|
task->thread.trap_nr = trapnr;
|
|
die(str, regs, error_code);
|
|
}
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Save the info for the exception handler and clear the error.
|
|
*/
|
|
save_init_fpu(task);
|
|
task->thread.trap_nr = trapnr;
|
|
task->thread.error_code = error_code;
|
|
info.si_signo = SIGFPE;
|
|
info.si_errno = 0;
|
|
info.si_addr = (void __user *)uprobe_get_trap_addr(regs);
|
|
if (trapnr == X86_TRAP_MF) {
|
|
unsigned short cwd, swd;
|
|
/*
|
|
* (~cwd & swd) will mask out exceptions that are not set to unmasked
|
|
* status. 0x3f is the exception bits in these regs, 0x200 is the
|
|
* C1 reg you need in case of a stack fault, 0x040 is the stack
|
|
* fault bit. We should only be taking one exception at a time,
|
|
* so if this combination doesn't produce any single exception,
|
|
* then we have a bad program that isn't synchronizing its FPU usage
|
|
* and it will suffer the consequences since we won't be able to
|
|
* fully reproduce the context of the exception
|
|
*/
|
|
cwd = get_fpu_cwd(task);
|
|
swd = get_fpu_swd(task);
|
|
|
|
err = swd & ~cwd;
|
|
} else {
|
|
/*
|
|
* The SIMD FPU exceptions are handled a little differently, as there
|
|
* is only a single status/control register. Thus, to determine which
|
|
* unmasked exception was caught we must mask the exception mask bits
|
|
* at 0x1f80, and then use these to mask the exception bits at 0x3f.
|
|
*/
|
|
unsigned short mxcsr = get_fpu_mxcsr(task);
|
|
err = ~(mxcsr >> 7) & mxcsr;
|
|
}
|
|
|
|
if (err & 0x001) { /* Invalid op */
|
|
/*
|
|
* swd & 0x240 == 0x040: Stack Underflow
|
|
* swd & 0x240 == 0x240: Stack Overflow
|
|
* User must clear the SF bit (0x40) if set
|
|
*/
|
|
info.si_code = FPE_FLTINV;
|
|
} else if (err & 0x004) { /* Divide by Zero */
|
|
info.si_code = FPE_FLTDIV;
|
|
} else if (err & 0x008) { /* Overflow */
|
|
info.si_code = FPE_FLTOVF;
|
|
} else if (err & 0x012) { /* Denormal, Underflow */
|
|
info.si_code = FPE_FLTUND;
|
|
} else if (err & 0x020) { /* Precision */
|
|
info.si_code = FPE_FLTRES;
|
|
} else {
|
|
/*
|
|
* If we're using IRQ 13, or supposedly even some trap
|
|
* X86_TRAP_MF implementations, it's possible
|
|
* we get a spurious trap, which is not an error.
|
|
*/
|
|
return;
|
|
}
|
|
force_sig_info(SIGFPE, &info, task);
|
|
}
|
|
|
|
dotraplinkage void do_coprocessor_error(struct pt_regs *regs, long error_code)
|
|
{
|
|
enum ctx_state prev_state;
|
|
|
|
prev_state = exception_enter();
|
|
math_error(regs, error_code, X86_TRAP_MF);
|
|
exception_exit(prev_state);
|
|
}
|
|
|
|
dotraplinkage void
|
|
do_simd_coprocessor_error(struct pt_regs *regs, long error_code)
|
|
{
|
|
enum ctx_state prev_state;
|
|
|
|
prev_state = exception_enter();
|
|
math_error(regs, error_code, X86_TRAP_XF);
|
|
exception_exit(prev_state);
|
|
}
|
|
|
|
dotraplinkage void
|
|
do_spurious_interrupt_bug(struct pt_regs *regs, long error_code)
|
|
{
|
|
conditional_sti(regs);
|
|
#if 0
|
|
/* No need to warn about this any longer. */
|
|
pr_info("Ignoring P6 Local APIC Spurious Interrupt Bug...\n");
|
|
#endif
|
|
}
|
|
|
|
asmlinkage __visible void __attribute__((weak)) smp_thermal_interrupt(void)
|
|
{
|
|
}
|
|
|
|
asmlinkage __visible void __attribute__((weak)) smp_threshold_interrupt(void)
|
|
{
|
|
}
|
|
|
|
/*
|
|
* 'math_state_restore()' saves the current math information in the
|
|
* old math state array, and gets the new ones from the current task
|
|
*
|
|
* Careful.. There are problems with IBM-designed IRQ13 behaviour.
|
|
* Don't touch unless you *really* know how it works.
|
|
*
|
|
* Must be called with kernel preemption disabled (eg with local
|
|
* local interrupts as in the case of do_device_not_available).
|
|
*/
|
|
void math_state_restore(void)
|
|
{
|
|
struct task_struct *tsk = current;
|
|
|
|
if (!tsk_used_math(tsk)) {
|
|
local_irq_enable();
|
|
/*
|
|
* does a slab alloc which can sleep
|
|
*/
|
|
if (init_fpu(tsk)) {
|
|
/*
|
|
* ran out of memory!
|
|
*/
|
|
do_group_exit(SIGKILL);
|
|
return;
|
|
}
|
|
local_irq_disable();
|
|
}
|
|
|
|
/* Avoid __kernel_fpu_begin() right after __thread_fpu_begin() */
|
|
kernel_fpu_disable();
|
|
__thread_fpu_begin(tsk);
|
|
if (unlikely(restore_fpu_checking(tsk))) {
|
|
drop_init_fpu(tsk);
|
|
force_sig_info(SIGSEGV, SEND_SIG_PRIV, tsk);
|
|
} else {
|
|
tsk->thread.fpu_counter++;
|
|
}
|
|
kernel_fpu_enable();
|
|
}
|
|
EXPORT_SYMBOL_GPL(math_state_restore);
|
|
|
|
dotraplinkage void
|
|
do_device_not_available(struct pt_regs *regs, long error_code)
|
|
{
|
|
enum ctx_state prev_state;
|
|
|
|
prev_state = exception_enter();
|
|
BUG_ON(use_eager_fpu());
|
|
|
|
#ifdef CONFIG_MATH_EMULATION
|
|
if (read_cr0() & X86_CR0_EM) {
|
|
struct math_emu_info info = { };
|
|
|
|
conditional_sti(regs);
|
|
|
|
info.regs = regs;
|
|
math_emulate(&info);
|
|
exception_exit(prev_state);
|
|
return;
|
|
}
|
|
#endif
|
|
math_state_restore(); /* interrupts still off */
|
|
#ifdef CONFIG_X86_32
|
|
conditional_sti(regs);
|
|
#endif
|
|
exception_exit(prev_state);
|
|
}
|
|
NOKPROBE_SYMBOL(do_device_not_available);
|
|
|
|
#ifdef CONFIG_X86_32
|
|
dotraplinkage void do_iret_error(struct pt_regs *regs, long error_code)
|
|
{
|
|
siginfo_t info;
|
|
enum ctx_state prev_state;
|
|
|
|
prev_state = exception_enter();
|
|
local_irq_enable();
|
|
|
|
info.si_signo = SIGILL;
|
|
info.si_errno = 0;
|
|
info.si_code = ILL_BADSTK;
|
|
info.si_addr = NULL;
|
|
if (notify_die(DIE_TRAP, "iret exception", regs, error_code,
|
|
X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) {
|
|
do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, error_code,
|
|
&info);
|
|
}
|
|
exception_exit(prev_state);
|
|
}
|
|
#endif
|
|
|
|
/* Set of traps needed for early debugging. */
|
|
void __init early_trap_init(void)
|
|
{
|
|
set_intr_gate_ist(X86_TRAP_DB, &debug, DEBUG_STACK);
|
|
/* int3 can be called from all */
|
|
set_system_intr_gate_ist(X86_TRAP_BP, &int3, DEBUG_STACK);
|
|
#ifdef CONFIG_X86_32
|
|
set_intr_gate(X86_TRAP_PF, page_fault);
|
|
#endif
|
|
load_idt(&idt_descr);
|
|
}
|
|
|
|
void __init early_trap_pf_init(void)
|
|
{
|
|
#ifdef CONFIG_X86_64
|
|
set_intr_gate(X86_TRAP_PF, page_fault);
|
|
#endif
|
|
}
|
|
|
|
void __init trap_init(void)
|
|
{
|
|
int i;
|
|
|
|
#ifdef CONFIG_EISA
|
|
void __iomem *p = early_ioremap(0x0FFFD9, 4);
|
|
|
|
if (readl(p) == 'E' + ('I'<<8) + ('S'<<16) + ('A'<<24))
|
|
EISA_bus = 1;
|
|
early_iounmap(p, 4);
|
|
#endif
|
|
|
|
set_intr_gate(X86_TRAP_DE, divide_error);
|
|
set_intr_gate_ist(X86_TRAP_NMI, &nmi, NMI_STACK);
|
|
/* int4 can be called from all */
|
|
set_system_intr_gate(X86_TRAP_OF, &overflow);
|
|
set_intr_gate(X86_TRAP_BR, bounds);
|
|
set_intr_gate(X86_TRAP_UD, invalid_op);
|
|
set_intr_gate(X86_TRAP_NM, device_not_available);
|
|
#ifdef CONFIG_X86_32
|
|
set_task_gate(X86_TRAP_DF, GDT_ENTRY_DOUBLEFAULT_TSS);
|
|
#else
|
|
set_intr_gate_ist(X86_TRAP_DF, &double_fault, DOUBLEFAULT_STACK);
|
|
#endif
|
|
set_intr_gate(X86_TRAP_OLD_MF, coprocessor_segment_overrun);
|
|
set_intr_gate(X86_TRAP_TS, invalid_TSS);
|
|
set_intr_gate(X86_TRAP_NP, segment_not_present);
|
|
set_intr_gate(X86_TRAP_SS, stack_segment);
|
|
set_intr_gate(X86_TRAP_GP, general_protection);
|
|
set_intr_gate(X86_TRAP_SPURIOUS, spurious_interrupt_bug);
|
|
set_intr_gate(X86_TRAP_MF, coprocessor_error);
|
|
set_intr_gate(X86_TRAP_AC, alignment_check);
|
|
#ifdef CONFIG_X86_MCE
|
|
set_intr_gate_ist(X86_TRAP_MC, &machine_check, MCE_STACK);
|
|
#endif
|
|
set_intr_gate(X86_TRAP_XF, simd_coprocessor_error);
|
|
|
|
/* Reserve all the builtin and the syscall vector: */
|
|
for (i = 0; i < FIRST_EXTERNAL_VECTOR; i++)
|
|
set_bit(i, used_vectors);
|
|
|
|
#ifdef CONFIG_IA32_EMULATION
|
|
set_system_intr_gate(IA32_SYSCALL_VECTOR, ia32_syscall);
|
|
set_bit(IA32_SYSCALL_VECTOR, used_vectors);
|
|
#endif
|
|
|
|
#ifdef CONFIG_X86_32
|
|
set_system_trap_gate(SYSCALL_VECTOR, &system_call);
|
|
set_bit(SYSCALL_VECTOR, used_vectors);
|
|
#endif
|
|
|
|
/*
|
|
* Set the IDT descriptor to a fixed read-only location, so that the
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* "sidt" instruction will not leak the location of the kernel, and
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* to defend the IDT against arbitrary memory write vulnerabilities.
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* It will be reloaded in cpu_init() */
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__set_fixmap(FIX_RO_IDT, __pa_symbol(idt_table), PAGE_KERNEL_RO);
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idt_descr.address = fix_to_virt(FIX_RO_IDT);
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|
|
/*
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* Should be a barrier for any external CPU state:
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|
*/
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|
cpu_init();
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|
|
|
x86_init.irqs.trap_init();
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|
|
|
#ifdef CONFIG_X86_64
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|
memcpy(&debug_idt_table, &idt_table, IDT_ENTRIES * 16);
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|
set_nmi_gate(X86_TRAP_DB, &debug);
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|
set_nmi_gate(X86_TRAP_BP, &int3);
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|
#endif
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}
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