mirror of https://gitee.com/openkylin/linux.git
145 lines
3.5 KiB
C
145 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2000 Ani Joshi <ajoshi@unixbox.com>
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* Copyright (C) 2000, 2001, 06 Ralf Baechle <ralf@linux-mips.org>
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* swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
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*/
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#include <linux/dma-direct.h>
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#include <linux/dma-map-ops.h>
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#include <linux/highmem.h>
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#include <asm/cache.h>
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#include <asm/cpu-type.h>
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#include <asm/io.h>
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/*
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* The affected CPUs below in 'cpu_needs_post_dma_flush()' can speculatively
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* fill random cachelines with stale data at any time, requiring an extra
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* flush post-DMA.
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*
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* Warning on the terminology - Linux calls an uncached area coherent; MIPS
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* terminology calls memory areas with hardware maintained coherency coherent.
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*
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* Note that the R14000 and R16000 should also be checked for in this condition.
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* However this function is only called on non-I/O-coherent systems and only the
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* R10000 and R12000 are used in such systems, the SGI IP28 Indigo² rsp.
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* SGI IP32 aka O2.
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*/
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static inline bool cpu_needs_post_dma_flush(void)
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{
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switch (boot_cpu_type()) {
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case CPU_R10000:
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case CPU_R12000:
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case CPU_BMIPS5000:
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case CPU_LOONGSON2EF:
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return true;
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default:
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/*
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* Presence of MAARs suggests that the CPU supports
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* speculatively prefetching data, and therefore requires
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* the post-DMA flush/invalidate.
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*/
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return cpu_has_maar;
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}
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}
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void arch_dma_prep_coherent(struct page *page, size_t size)
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{
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dma_cache_wback_inv((unsigned long)page_address(page), size);
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}
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void *arch_dma_set_uncached(void *addr, size_t size)
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{
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return (void *)(__pa(addr) + UNCAC_BASE);
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}
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static inline void dma_sync_virt_for_device(void *addr, size_t size,
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enum dma_data_direction dir)
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{
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switch (dir) {
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case DMA_TO_DEVICE:
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dma_cache_wback((unsigned long)addr, size);
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break;
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case DMA_FROM_DEVICE:
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dma_cache_inv((unsigned long)addr, size);
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break;
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case DMA_BIDIRECTIONAL:
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dma_cache_wback_inv((unsigned long)addr, size);
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break;
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default:
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BUG();
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}
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}
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static inline void dma_sync_virt_for_cpu(void *addr, size_t size,
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enum dma_data_direction dir)
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{
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switch (dir) {
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case DMA_TO_DEVICE:
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break;
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case DMA_FROM_DEVICE:
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case DMA_BIDIRECTIONAL:
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dma_cache_inv((unsigned long)addr, size);
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break;
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default:
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BUG();
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}
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}
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/*
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* A single sg entry may refer to multiple physically contiguous pages. But
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* we still need to process highmem pages individually. If highmem is not
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* configured then the bulk of this loop gets optimized out.
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*/
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static inline void dma_sync_phys(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir, bool for_device)
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{
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struct page *page = pfn_to_page(paddr >> PAGE_SHIFT);
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unsigned long offset = paddr & ~PAGE_MASK;
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size_t left = size;
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do {
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size_t len = left;
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void *addr;
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if (PageHighMem(page)) {
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if (offset + len > PAGE_SIZE)
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len = PAGE_SIZE - offset;
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}
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addr = kmap_atomic(page);
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if (for_device)
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dma_sync_virt_for_device(addr + offset, len, dir);
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else
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dma_sync_virt_for_cpu(addr + offset, len, dir);
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kunmap_atomic(addr);
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offset = 0;
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page++;
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left -= len;
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} while (left);
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}
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void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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{
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dma_sync_phys(paddr, size, dir, true);
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}
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#ifdef CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU
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void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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{
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if (cpu_needs_post_dma_flush())
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dma_sync_phys(paddr, size, dir, false);
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}
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#endif
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#ifdef CONFIG_ARCH_HAS_SETUP_DMA_OPS
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void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
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const struct iommu_ops *iommu, bool coherent)
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{
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dev->dma_coherent = coherent;
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}
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#endif
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