mirror of https://gitee.com/openkylin/linux.git
868 lines
27 KiB
C
868 lines
27 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef _ASM_POWERPC_IO_H
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#define _ASM_POWERPC_IO_H
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#ifdef __KERNEL__
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#define ARCH_HAS_IOREMAP_WC
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#ifdef CONFIG_PPC32
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#define ARCH_HAS_IOREMAP_WT
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#endif
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/*
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*/
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/* Check of existence of legacy devices */
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extern int check_legacy_ioport(unsigned long base_port);
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#define I8042_DATA_REG 0x60
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#define FDC_BASE 0x3f0
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#if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
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extern struct pci_dev *isa_bridge_pcidev;
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/*
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* has legacy ISA devices ?
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*/
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#define arch_has_dev_port() (isa_bridge_pcidev != NULL || isa_io_special)
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#endif
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#include <linux/device.h>
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#include <linux/compiler.h>
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#include <linux/mm.h>
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#include <asm/page.h>
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#include <asm/byteorder.h>
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#include <asm/synch.h>
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#include <asm/delay.h>
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#include <asm/mmiowb.h>
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#include <asm/mmu.h>
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#include <asm/ppc_asm.h>
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#include <asm/pgtable.h>
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#define SIO_CONFIG_RA 0x398
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#define SIO_CONFIG_RD 0x399
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#define SLOW_DOWN_IO
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/* 32 bits uses slightly different variables for the various IO
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* bases. Most of this file only uses _IO_BASE though which we
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* define properly based on the platform
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*/
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#ifndef CONFIG_PCI
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#define _IO_BASE 0
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#define _ISA_MEM_BASE 0
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#define PCI_DRAM_OFFSET 0
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#elif defined(CONFIG_PPC32)
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#define _IO_BASE isa_io_base
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#define _ISA_MEM_BASE isa_mem_base
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#define PCI_DRAM_OFFSET pci_dram_offset
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#else
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#define _IO_BASE pci_io_base
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#define _ISA_MEM_BASE isa_mem_base
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#define PCI_DRAM_OFFSET 0
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#endif
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extern unsigned long isa_io_base;
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extern unsigned long pci_io_base;
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extern unsigned long pci_dram_offset;
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extern resource_size_t isa_mem_base;
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/* Boolean set by platform if PIO accesses are suppored while _IO_BASE
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* is not set or addresses cannot be translated to MMIO. This is typically
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* set when the platform supports "special" PIO accesses via a non memory
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* mapped mechanism, and allows things like the early udbg UART code to
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* function.
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*/
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extern bool isa_io_special;
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#ifdef CONFIG_PPC32
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#if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
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#error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits
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#endif
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#endif
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/*
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*
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* Low level MMIO accessors
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*
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* This provides the non-bus specific accessors to MMIO. Those are PowerPC
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* specific and thus shouldn't be used in generic code. The accessors
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* provided here are:
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*
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* in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
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* out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
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* _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
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*
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* Those operate directly on a kernel virtual address. Note that the prototype
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* for the out_* accessors has the arguments in opposite order from the usual
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* linux PCI accessors. Unlike those, they take the address first and the value
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* next.
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*
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* Note: I might drop the _ns suffix on the stream operations soon as it is
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* simply normal for stream operations to not swap in the first place.
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*
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*/
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#define DEF_MMIO_IN_X(name, size, insn) \
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static inline u##size name(const volatile u##size __iomem *addr) \
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{ \
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u##size ret; \
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__asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \
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: "=r" (ret) : "Z" (*addr) : "memory"); \
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return ret; \
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}
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#define DEF_MMIO_OUT_X(name, size, insn) \
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static inline void name(volatile u##size __iomem *addr, u##size val) \
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{ \
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__asm__ __volatile__("sync;"#insn" %1,%y0" \
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: "=Z" (*addr) : "r" (val) : "memory"); \
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mmiowb_set_pending(); \
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}
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#define DEF_MMIO_IN_D(name, size, insn) \
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static inline u##size name(const volatile u##size __iomem *addr) \
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{ \
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u##size ret; \
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__asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
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: "=r" (ret) : "m" (*addr) : "memory"); \
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return ret; \
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}
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#define DEF_MMIO_OUT_D(name, size, insn) \
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static inline void name(volatile u##size __iomem *addr, u##size val) \
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{ \
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__asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \
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: "=m" (*addr) : "r" (val) : "memory"); \
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mmiowb_set_pending(); \
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}
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DEF_MMIO_IN_D(in_8, 8, lbz);
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DEF_MMIO_OUT_D(out_8, 8, stb);
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#ifdef __BIG_ENDIAN__
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DEF_MMIO_IN_D(in_be16, 16, lhz);
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DEF_MMIO_IN_D(in_be32, 32, lwz);
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DEF_MMIO_IN_X(in_le16, 16, lhbrx);
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DEF_MMIO_IN_X(in_le32, 32, lwbrx);
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DEF_MMIO_OUT_D(out_be16, 16, sth);
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DEF_MMIO_OUT_D(out_be32, 32, stw);
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DEF_MMIO_OUT_X(out_le16, 16, sthbrx);
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DEF_MMIO_OUT_X(out_le32, 32, stwbrx);
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#else
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DEF_MMIO_IN_X(in_be16, 16, lhbrx);
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DEF_MMIO_IN_X(in_be32, 32, lwbrx);
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DEF_MMIO_IN_D(in_le16, 16, lhz);
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DEF_MMIO_IN_D(in_le32, 32, lwz);
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DEF_MMIO_OUT_X(out_be16, 16, sthbrx);
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DEF_MMIO_OUT_X(out_be32, 32, stwbrx);
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DEF_MMIO_OUT_D(out_le16, 16, sth);
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DEF_MMIO_OUT_D(out_le32, 32, stw);
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#endif /* __BIG_ENDIAN */
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#ifdef __powerpc64__
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#ifdef __BIG_ENDIAN__
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DEF_MMIO_OUT_D(out_be64, 64, std);
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DEF_MMIO_IN_D(in_be64, 64, ld);
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/* There is no asm instructions for 64 bits reverse loads and stores */
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static inline u64 in_le64(const volatile u64 __iomem *addr)
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{
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return swab64(in_be64(addr));
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}
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static inline void out_le64(volatile u64 __iomem *addr, u64 val)
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{
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out_be64(addr, swab64(val));
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}
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#else
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DEF_MMIO_OUT_D(out_le64, 64, std);
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DEF_MMIO_IN_D(in_le64, 64, ld);
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/* There is no asm instructions for 64 bits reverse loads and stores */
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static inline u64 in_be64(const volatile u64 __iomem *addr)
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{
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return swab64(in_le64(addr));
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}
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static inline void out_be64(volatile u64 __iomem *addr, u64 val)
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{
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out_le64(addr, swab64(val));
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}
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#endif
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#endif /* __powerpc64__ */
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/*
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* Low level IO stream instructions are defined out of line for now
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*/
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extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
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extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
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extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
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extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
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extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
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extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
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/* The _ns naming is historical and will be removed. For now, just #define
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* the non _ns equivalent names
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*/
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#define _insw _insw_ns
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#define _insl _insl_ns
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#define _outsw _outsw_ns
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#define _outsl _outsl_ns
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/*
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* memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
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*/
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extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
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extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
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unsigned long n);
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extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
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unsigned long n);
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/*
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*
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* PCI and standard ISA accessors
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*
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* Those are globally defined linux accessors for devices on PCI or ISA
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* busses. They follow the Linux defined semantics. The current implementation
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* for PowerPC is as close as possible to the x86 version of these, and thus
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* provides fairly heavy weight barriers for the non-raw versions
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*
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* In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO
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* or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its
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* own implementation of some or all of the accessors.
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*/
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/*
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* Include the EEH definitions when EEH is enabled only so they don't get
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* in the way when building for 32 bits
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*/
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#ifdef CONFIG_EEH
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#include <asm/eeh.h>
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#endif
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/* Shortcut to the MMIO argument pointer */
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#define PCI_IO_ADDR volatile void __iomem *
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/* Indirect IO address tokens:
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*
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* When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks
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* on all MMIOs. (Note that this is all 64 bits only for now)
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*
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* To help platforms who may need to differentiate MMIO addresses in
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* their hooks, a bitfield is reserved for use by the platform near the
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* top of MMIO addresses (not PIO, those have to cope the hard way).
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*
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* The highest address in the kernel virtual space are:
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*
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* d0003fffffffffff # with Hash MMU
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* c00fffffffffffff # with Radix MMU
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*
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* The top 4 bits are reserved as the region ID on hash, leaving us 8 bits
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* that can be used for the field.
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*
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* The direct IO mapping operations will then mask off those bits
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* before doing the actual access, though that only happen when
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* CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that
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* mechanism
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*
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* For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes
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* all PIO functions call through a hook.
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*/
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#ifdef CONFIG_PPC_INDIRECT_MMIO
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#define PCI_IO_IND_TOKEN_SHIFT 52
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#define PCI_IO_IND_TOKEN_MASK (0xfful << PCI_IO_IND_TOKEN_SHIFT)
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#define PCI_FIX_ADDR(addr) \
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((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
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#define PCI_GET_ADDR_TOKEN(addr) \
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(((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \
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PCI_IO_IND_TOKEN_SHIFT)
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#define PCI_SET_ADDR_TOKEN(addr, token) \
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do { \
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unsigned long __a = (unsigned long)(addr); \
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__a &= ~PCI_IO_IND_TOKEN_MASK; \
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__a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \
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(addr) = (void __iomem *)__a; \
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} while(0)
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#else
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#define PCI_FIX_ADDR(addr) (addr)
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#endif
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/*
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* Non ordered and non-swapping "raw" accessors
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*/
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static inline unsigned char __raw_readb(const volatile void __iomem *addr)
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{
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return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
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}
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static inline unsigned short __raw_readw(const volatile void __iomem *addr)
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{
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return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
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}
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static inline unsigned int __raw_readl(const volatile void __iomem *addr)
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{
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return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
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}
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static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
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{
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*(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
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}
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static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
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{
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*(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
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}
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static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
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{
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*(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
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}
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#ifdef __powerpc64__
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static inline unsigned long __raw_readq(const volatile void __iomem *addr)
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{
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return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
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}
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static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
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{
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*(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
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}
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static inline void __raw_writeq_be(unsigned long v, volatile void __iomem *addr)
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{
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__raw_writeq((__force unsigned long)cpu_to_be64(v), addr);
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}
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/*
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* Real mode versions of the above. Those instructions are only supposed
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* to be used in hypervisor real mode as per the architecture spec.
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*/
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static inline void __raw_rm_writeb(u8 val, volatile void __iomem *paddr)
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{
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__asm__ __volatile__("stbcix %0,0,%1"
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: : "r" (val), "r" (paddr) : "memory");
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}
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static inline void __raw_rm_writew(u16 val, volatile void __iomem *paddr)
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{
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__asm__ __volatile__("sthcix %0,0,%1"
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: : "r" (val), "r" (paddr) : "memory");
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}
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static inline void __raw_rm_writel(u32 val, volatile void __iomem *paddr)
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{
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__asm__ __volatile__("stwcix %0,0,%1"
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: : "r" (val), "r" (paddr) : "memory");
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}
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static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
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{
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__asm__ __volatile__("stdcix %0,0,%1"
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: : "r" (val), "r" (paddr) : "memory");
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}
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static inline void __raw_rm_writeq_be(u64 val, volatile void __iomem *paddr)
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{
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__raw_rm_writeq((__force u64)cpu_to_be64(val), paddr);
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}
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static inline u8 __raw_rm_readb(volatile void __iomem *paddr)
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{
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u8 ret;
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__asm__ __volatile__("lbzcix %0,0, %1"
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: "=r" (ret) : "r" (paddr) : "memory");
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return ret;
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}
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static inline u16 __raw_rm_readw(volatile void __iomem *paddr)
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{
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u16 ret;
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__asm__ __volatile__("lhzcix %0,0, %1"
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: "=r" (ret) : "r" (paddr) : "memory");
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return ret;
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}
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static inline u32 __raw_rm_readl(volatile void __iomem *paddr)
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{
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u32 ret;
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__asm__ __volatile__("lwzcix %0,0, %1"
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: "=r" (ret) : "r" (paddr) : "memory");
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return ret;
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}
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static inline u64 __raw_rm_readq(volatile void __iomem *paddr)
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{
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u64 ret;
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__asm__ __volatile__("ldcix %0,0, %1"
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: "=r" (ret) : "r" (paddr) : "memory");
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return ret;
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}
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#endif /* __powerpc64__ */
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/*
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*
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* PCI PIO and MMIO accessors.
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*
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*
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* On 32 bits, PIO operations have a recovery mechanism in case they trigger
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* machine checks (which they occasionally do when probing non existing
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* IO ports on some platforms, like PowerMac and 8xx).
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* I always found it to be of dubious reliability and I am tempted to get
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* rid of it one of these days. So if you think it's important to keep it,
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* please voice up asap. We never had it for 64 bits and I do not intend
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* to port it over
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*/
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#ifdef CONFIG_PPC32
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#define __do_in_asm(name, op) \
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static inline unsigned int name(unsigned int port) \
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{ \
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unsigned int x; \
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__asm__ __volatile__( \
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"sync\n" \
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"0:" op " %0,0,%1\n" \
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"1: twi 0,%0,0\n" \
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"2: isync\n" \
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"3: nop\n" \
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"4:\n" \
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".section .fixup,\"ax\"\n" \
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"5: li %0,-1\n" \
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" b 4b\n" \
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".previous\n" \
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EX_TABLE(0b, 5b) \
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EX_TABLE(1b, 5b) \
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EX_TABLE(2b, 5b) \
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EX_TABLE(3b, 5b) \
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: "=&r" (x) \
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: "r" (port + _IO_BASE) \
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: "memory"); \
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return x; \
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}
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#define __do_out_asm(name, op) \
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static inline void name(unsigned int val, unsigned int port) \
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{ \
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__asm__ __volatile__( \
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"sync\n" \
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"0:" op " %0,0,%1\n" \
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"1: sync\n" \
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"2:\n" \
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EX_TABLE(0b, 2b) \
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EX_TABLE(1b, 2b) \
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: : "r" (val), "r" (port + _IO_BASE) \
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: "memory"); \
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}
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__do_in_asm(_rec_inb, "lbzx")
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__do_in_asm(_rec_inw, "lhbrx")
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__do_in_asm(_rec_inl, "lwbrx")
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__do_out_asm(_rec_outb, "stbx")
|
|
__do_out_asm(_rec_outw, "sthbrx")
|
|
__do_out_asm(_rec_outl, "stwbrx")
|
|
|
|
#endif /* CONFIG_PPC32 */
|
|
|
|
/* The "__do_*" operations below provide the actual "base" implementation
|
|
* for each of the defined accessors. Some of them use the out_* functions
|
|
* directly, some of them still use EEH, though we might change that in the
|
|
* future. Those macros below provide the necessary argument swapping and
|
|
* handling of the IO base for PIO.
|
|
*
|
|
* They are themselves used by the macros that define the actual accessors
|
|
* and can be used by the hooks if any.
|
|
*
|
|
* Note that PIO operations are always defined in terms of their corresonding
|
|
* MMIO operations. That allows platforms like iSeries who want to modify the
|
|
* behaviour of both to only hook on the MMIO version and get both. It's also
|
|
* possible to hook directly at the toplevel PIO operation if they have to
|
|
* be handled differently
|
|
*/
|
|
#define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val)
|
|
#define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val)
|
|
#define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val)
|
|
#define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val)
|
|
#define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
|
|
#define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
|
|
#define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
|
|
|
|
#ifdef CONFIG_EEH
|
|
#define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr))
|
|
#define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr))
|
|
#define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr))
|
|
#define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr))
|
|
#define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr))
|
|
#define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr))
|
|
#define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr))
|
|
#else /* CONFIG_EEH */
|
|
#define __do_readb(addr) in_8(PCI_FIX_ADDR(addr))
|
|
#define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr))
|
|
#define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr))
|
|
#define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr))
|
|
#define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr))
|
|
#define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr))
|
|
#define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr))
|
|
#endif /* !defined(CONFIG_EEH) */
|
|
|
|
#ifdef CONFIG_PPC32
|
|
#define __do_outb(val, port) _rec_outb(val, port)
|
|
#define __do_outw(val, port) _rec_outw(val, port)
|
|
#define __do_outl(val, port) _rec_outl(val, port)
|
|
#define __do_inb(port) _rec_inb(port)
|
|
#define __do_inw(port) _rec_inw(port)
|
|
#define __do_inl(port) _rec_inl(port)
|
|
#else /* CONFIG_PPC32 */
|
|
#define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
|
|
#define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port);
|
|
#define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port);
|
|
#define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port);
|
|
#define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port);
|
|
#define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port);
|
|
#endif /* !CONFIG_PPC32 */
|
|
|
|
#ifdef CONFIG_EEH
|
|
#define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
|
|
#define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
|
|
#define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
|
|
#else /* CONFIG_EEH */
|
|
#define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n))
|
|
#define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n))
|
|
#define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n))
|
|
#endif /* !CONFIG_EEH */
|
|
#define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n))
|
|
#define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n))
|
|
#define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n))
|
|
|
|
#define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
|
|
#define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
|
|
#define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
|
|
#define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
|
|
#define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
|
|
#define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
|
|
|
|
#define __do_memset_io(addr, c, n) \
|
|
_memset_io(PCI_FIX_ADDR(addr), c, n)
|
|
#define __do_memcpy_toio(dst, src, n) \
|
|
_memcpy_toio(PCI_FIX_ADDR(dst), src, n)
|
|
|
|
#ifdef CONFIG_EEH
|
|
#define __do_memcpy_fromio(dst, src, n) \
|
|
eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
|
|
#else /* CONFIG_EEH */
|
|
#define __do_memcpy_fromio(dst, src, n) \
|
|
_memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
|
|
#endif /* !CONFIG_EEH */
|
|
|
|
#ifdef CONFIG_PPC_INDIRECT_PIO
|
|
#define DEF_PCI_HOOK_pio(x) x
|
|
#else
|
|
#define DEF_PCI_HOOK_pio(x) NULL
|
|
#endif
|
|
|
|
#ifdef CONFIG_PPC_INDIRECT_MMIO
|
|
#define DEF_PCI_HOOK_mem(x) x
|
|
#else
|
|
#define DEF_PCI_HOOK_mem(x) NULL
|
|
#endif
|
|
|
|
/* Structure containing all the hooks */
|
|
extern struct ppc_pci_io {
|
|
|
|
#define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at;
|
|
#define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at;
|
|
|
|
#include <asm/io-defs.h>
|
|
|
|
#undef DEF_PCI_AC_RET
|
|
#undef DEF_PCI_AC_NORET
|
|
|
|
} ppc_pci_io;
|
|
|
|
/* The inline wrappers */
|
|
#define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
|
|
static inline ret name at \
|
|
{ \
|
|
if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
|
|
return ppc_pci_io.name al; \
|
|
return __do_##name al; \
|
|
}
|
|
|
|
#define DEF_PCI_AC_NORET(name, at, al, space, aa) \
|
|
static inline void name at \
|
|
{ \
|
|
if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
|
|
ppc_pci_io.name al; \
|
|
else \
|
|
__do_##name al; \
|
|
}
|
|
|
|
#include <asm/io-defs.h>
|
|
|
|
#undef DEF_PCI_AC_RET
|
|
#undef DEF_PCI_AC_NORET
|
|
|
|
/* Some drivers check for the presence of readq & writeq with
|
|
* a #ifdef, so we make them happy here.
|
|
*/
|
|
#ifdef __powerpc64__
|
|
#define readq readq
|
|
#define writeq writeq
|
|
#endif
|
|
|
|
/*
|
|
* Convert a physical pointer to a virtual kernel pointer for /dev/mem
|
|
* access
|
|
*/
|
|
#define xlate_dev_mem_ptr(p) __va(p)
|
|
|
|
/*
|
|
* Convert a virtual cached pointer to an uncached pointer
|
|
*/
|
|
#define xlate_dev_kmem_ptr(p) p
|
|
|
|
/*
|
|
* We don't do relaxed operations yet, at least not with this semantic
|
|
*/
|
|
#define readb_relaxed(addr) readb(addr)
|
|
#define readw_relaxed(addr) readw(addr)
|
|
#define readl_relaxed(addr) readl(addr)
|
|
#define readq_relaxed(addr) readq(addr)
|
|
#define writeb_relaxed(v, addr) writeb(v, addr)
|
|
#define writew_relaxed(v, addr) writew(v, addr)
|
|
#define writel_relaxed(v, addr) writel(v, addr)
|
|
#define writeq_relaxed(v, addr) writeq(v, addr)
|
|
|
|
#include <asm-generic/iomap.h>
|
|
|
|
static inline void iosync(void)
|
|
{
|
|
__asm__ __volatile__ ("sync" : : : "memory");
|
|
}
|
|
|
|
/* Enforce in-order execution of data I/O.
|
|
* No distinction between read/write on PPC; use eieio for all three.
|
|
* Those are fairly week though. They don't provide a barrier between
|
|
* MMIO and cacheable storage nor do they provide a barrier vs. locks,
|
|
* they only provide barriers between 2 __raw MMIO operations and
|
|
* possibly break write combining.
|
|
*/
|
|
#define iobarrier_rw() eieio()
|
|
#define iobarrier_r() eieio()
|
|
#define iobarrier_w() eieio()
|
|
|
|
|
|
/*
|
|
* output pause versions need a delay at least for the
|
|
* w83c105 ide controller in a p610.
|
|
*/
|
|
#define inb_p(port) inb(port)
|
|
#define outb_p(val, port) (udelay(1), outb((val), (port)))
|
|
#define inw_p(port) inw(port)
|
|
#define outw_p(val, port) (udelay(1), outw((val), (port)))
|
|
#define inl_p(port) inl(port)
|
|
#define outl_p(val, port) (udelay(1), outl((val), (port)))
|
|
|
|
|
|
#define IO_SPACE_LIMIT ~(0UL)
|
|
|
|
|
|
/**
|
|
* ioremap - map bus memory into CPU space
|
|
* @address: bus address of the memory
|
|
* @size: size of the resource to map
|
|
*
|
|
* ioremap performs a platform specific sequence of operations to
|
|
* make bus memory CPU accessible via the readb/readw/readl/writeb/
|
|
* writew/writel functions and the other mmio helpers. The returned
|
|
* address is not guaranteed to be usable directly as a virtual
|
|
* address.
|
|
*
|
|
* We provide a few variations of it:
|
|
*
|
|
* * ioremap is the standard one and provides non-cacheable guarded mappings
|
|
* and can be hooked by the platform via ppc_md
|
|
*
|
|
* * ioremap_prot allows to specify the page flags as an argument and can
|
|
* also be hooked by the platform via ppc_md.
|
|
*
|
|
* * ioremap_wc enables write combining
|
|
*
|
|
* * ioremap_wt enables write through
|
|
*
|
|
* * ioremap_coherent maps coherent cached memory
|
|
*
|
|
* * iounmap undoes such a mapping and can be hooked
|
|
*
|
|
* * __ioremap_at (and the pending __iounmap_at) are low level functions to
|
|
* create hand-made mappings for use only by the PCI code and cannot
|
|
* currently be hooked. Must be page aligned.
|
|
*
|
|
* * __ioremap_caller is the same as above but takes an explicit caller
|
|
* reference rather than using __builtin_return_address(0)
|
|
*
|
|
*/
|
|
extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
|
|
extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
|
|
unsigned long flags);
|
|
extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
|
|
void __iomem *ioremap_wt(phys_addr_t address, unsigned long size);
|
|
void __iomem *ioremap_coherent(phys_addr_t address, unsigned long size);
|
|
#define ioremap_uc(addr, size) ioremap((addr), (size))
|
|
#define ioremap_cache(addr, size) \
|
|
ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL))
|
|
|
|
extern void iounmap(volatile void __iomem *addr);
|
|
|
|
int early_ioremap_range(unsigned long ea, phys_addr_t pa,
|
|
unsigned long size, pgprot_t prot);
|
|
void __iomem *do_ioremap(phys_addr_t pa, phys_addr_t offset, unsigned long size,
|
|
pgprot_t prot, void *caller);
|
|
|
|
extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
|
|
pgprot_t prot, void *caller);
|
|
|
|
extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea,
|
|
unsigned long size, pgprot_t prot);
|
|
extern void __iounmap_at(void *ea, unsigned long size);
|
|
|
|
/*
|
|
* When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation
|
|
* which needs some additional definitions here. They basically allow PIO
|
|
* space overall to be 1GB. This will work as long as we never try to use
|
|
* iomap to map MMIO below 1GB which should be fine on ppc64
|
|
*/
|
|
#define HAVE_ARCH_PIO_SIZE 1
|
|
#define PIO_OFFSET 0x00000000UL
|
|
#define PIO_MASK (FULL_IO_SIZE - 1)
|
|
#define PIO_RESERVED (FULL_IO_SIZE)
|
|
|
|
#define mmio_read16be(addr) readw_be(addr)
|
|
#define mmio_read32be(addr) readl_be(addr)
|
|
#define mmio_read64be(addr) readq_be(addr)
|
|
#define mmio_write16be(val, addr) writew_be(val, addr)
|
|
#define mmio_write32be(val, addr) writel_be(val, addr)
|
|
#define mmio_write64be(val, addr) writeq_be(val, addr)
|
|
#define mmio_insb(addr, dst, count) readsb(addr, dst, count)
|
|
#define mmio_insw(addr, dst, count) readsw(addr, dst, count)
|
|
#define mmio_insl(addr, dst, count) readsl(addr, dst, count)
|
|
#define mmio_outsb(addr, src, count) writesb(addr, src, count)
|
|
#define mmio_outsw(addr, src, count) writesw(addr, src, count)
|
|
#define mmio_outsl(addr, src, count) writesl(addr, src, count)
|
|
|
|
/**
|
|
* virt_to_phys - map virtual addresses to physical
|
|
* @address: address to remap
|
|
*
|
|
* The returned physical address is the physical (CPU) mapping for
|
|
* the memory address given. It is only valid to use this function on
|
|
* addresses directly mapped or allocated via kmalloc.
|
|
*
|
|
* This function does not give bus mappings for DMA transfers. In
|
|
* almost all conceivable cases a device driver should not be using
|
|
* this function
|
|
*/
|
|
static inline unsigned long virt_to_phys(volatile void * address)
|
|
{
|
|
WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !virt_addr_valid(address));
|
|
|
|
return __pa((unsigned long)address);
|
|
}
|
|
|
|
/**
|
|
* phys_to_virt - map physical address to virtual
|
|
* @address: address to remap
|
|
*
|
|
* The returned virtual address is a current CPU mapping for
|
|
* the memory address given. It is only valid to use this function on
|
|
* addresses that have a kernel mapping
|
|
*
|
|
* This function does not handle bus mappings for DMA transfers. In
|
|
* almost all conceivable cases a device driver should not be using
|
|
* this function
|
|
*/
|
|
static inline void * phys_to_virt(unsigned long address)
|
|
{
|
|
return (void *)__va(address);
|
|
}
|
|
|
|
/*
|
|
* Change "struct page" to physical address.
|
|
*/
|
|
static inline phys_addr_t page_to_phys(struct page *page)
|
|
{
|
|
unsigned long pfn = page_to_pfn(page);
|
|
|
|
WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !pfn_valid(pfn));
|
|
|
|
return PFN_PHYS(pfn);
|
|
}
|
|
|
|
/*
|
|
* 32 bits still uses virt_to_bus() for it's implementation of DMA
|
|
* mappings se we have to keep it defined here. We also have some old
|
|
* drivers (shame shame shame) that use bus_to_virt() and haven't been
|
|
* fixed yet so I need to define it here.
|
|
*/
|
|
#ifdef CONFIG_PPC32
|
|
|
|
static inline unsigned long virt_to_bus(volatile void * address)
|
|
{
|
|
if (address == NULL)
|
|
return 0;
|
|
return __pa(address) + PCI_DRAM_OFFSET;
|
|
}
|
|
|
|
static inline void * bus_to_virt(unsigned long address)
|
|
{
|
|
if (address == 0)
|
|
return NULL;
|
|
return __va(address - PCI_DRAM_OFFSET);
|
|
}
|
|
|
|
#define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
|
|
|
|
#endif /* CONFIG_PPC32 */
|
|
|
|
/* access ports */
|
|
#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
|
|
#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
|
|
|
|
#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
|
|
#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
|
|
|
|
#define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v))
|
|
#define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
|
|
|
|
/* Clear and set bits in one shot. These macros can be used to clear and
|
|
* set multiple bits in a register using a single read-modify-write. These
|
|
* macros can also be used to set a multiple-bit bit pattern using a mask,
|
|
* by specifying the mask in the 'clear' parameter and the new bit pattern
|
|
* in the 'set' parameter.
|
|
*/
|
|
|
|
#define clrsetbits(type, addr, clear, set) \
|
|
out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
|
|
|
|
#ifdef __powerpc64__
|
|
#define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
|
|
#define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
|
|
#endif
|
|
|
|
#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
|
|
#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
|
|
|
|
#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
|
|
#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
|
|
|
|
#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
|
|
|
|
#endif /* __KERNEL__ */
|
|
|
|
#endif /* _ASM_POWERPC_IO_H */
|