mirror of https://gitee.com/openkylin/linux.git
467 lines
10 KiB
C
467 lines
10 KiB
C
/*
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* Copyright (C) ST-Ericsson SA 2010
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*
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* License Terms: GNU General Public License v2
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* Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
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* Author: Rabin Vincent <rabin.vincent@stericsson.com>
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*/
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/ab8500.h>
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#include <linux/regulator/ab8500.h>
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/*
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* Interrupt register offsets
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* Bank : 0x0E
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*/
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#define AB8500_IT_SOURCE1_REG 0x0E00
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#define AB8500_IT_SOURCE2_REG 0x0E01
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#define AB8500_IT_SOURCE3_REG 0x0E02
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#define AB8500_IT_SOURCE4_REG 0x0E03
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#define AB8500_IT_SOURCE5_REG 0x0E04
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#define AB8500_IT_SOURCE6_REG 0x0E05
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#define AB8500_IT_SOURCE7_REG 0x0E06
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#define AB8500_IT_SOURCE8_REG 0x0E07
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#define AB8500_IT_SOURCE19_REG 0x0E12
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#define AB8500_IT_SOURCE20_REG 0x0E13
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#define AB8500_IT_SOURCE21_REG 0x0E14
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#define AB8500_IT_SOURCE22_REG 0x0E15
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#define AB8500_IT_SOURCE23_REG 0x0E16
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#define AB8500_IT_SOURCE24_REG 0x0E17
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/*
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* latch registers
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*/
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#define AB8500_IT_LATCH1_REG 0x0E20
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#define AB8500_IT_LATCH2_REG 0x0E21
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#define AB8500_IT_LATCH3_REG 0x0E22
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#define AB8500_IT_LATCH4_REG 0x0E23
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#define AB8500_IT_LATCH5_REG 0x0E24
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#define AB8500_IT_LATCH6_REG 0x0E25
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#define AB8500_IT_LATCH7_REG 0x0E26
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#define AB8500_IT_LATCH8_REG 0x0E27
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#define AB8500_IT_LATCH9_REG 0x0E28
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#define AB8500_IT_LATCH10_REG 0x0E29
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#define AB8500_IT_LATCH19_REG 0x0E32
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#define AB8500_IT_LATCH20_REG 0x0E33
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#define AB8500_IT_LATCH21_REG 0x0E34
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#define AB8500_IT_LATCH22_REG 0x0E35
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#define AB8500_IT_LATCH23_REG 0x0E36
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#define AB8500_IT_LATCH24_REG 0x0E37
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/*
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* mask registers
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*/
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#define AB8500_IT_MASK1_REG 0x0E40
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#define AB8500_IT_MASK2_REG 0x0E41
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#define AB8500_IT_MASK3_REG 0x0E42
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#define AB8500_IT_MASK4_REG 0x0E43
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#define AB8500_IT_MASK5_REG 0x0E44
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#define AB8500_IT_MASK6_REG 0x0E45
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#define AB8500_IT_MASK7_REG 0x0E46
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#define AB8500_IT_MASK8_REG 0x0E47
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#define AB8500_IT_MASK9_REG 0x0E48
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#define AB8500_IT_MASK10_REG 0x0E49
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#define AB8500_IT_MASK11_REG 0x0E4A
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#define AB8500_IT_MASK12_REG 0x0E4B
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#define AB8500_IT_MASK13_REG 0x0E4C
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#define AB8500_IT_MASK14_REG 0x0E4D
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#define AB8500_IT_MASK15_REG 0x0E4E
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#define AB8500_IT_MASK16_REG 0x0E4F
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#define AB8500_IT_MASK17_REG 0x0E50
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#define AB8500_IT_MASK18_REG 0x0E51
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#define AB8500_IT_MASK19_REG 0x0E52
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#define AB8500_IT_MASK20_REG 0x0E53
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#define AB8500_IT_MASK21_REG 0x0E54
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#define AB8500_IT_MASK22_REG 0x0E55
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#define AB8500_IT_MASK23_REG 0x0E56
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#define AB8500_IT_MASK24_REG 0x0E57
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#define AB8500_REV_REG 0x1080
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/*
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* Map interrupt numbers to the LATCH and MASK register offsets, Interrupt
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* numbers are indexed into this array with (num / 8).
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*
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* This is one off from the register names, i.e. AB8500_IT_MASK1_REG is at
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* offset 0.
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*/
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static const int ab8500_irq_regoffset[AB8500_NUM_IRQ_REGS] = {
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0, 1, 2, 3, 4, 6, 7, 8, 9, 18, 19, 20, 21,
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};
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static int __ab8500_write(struct ab8500 *ab8500, u16 addr, u8 data)
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{
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int ret;
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dev_vdbg(ab8500->dev, "wr: addr %#x <= %#x\n", addr, data);
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ret = ab8500->write(ab8500, addr, data);
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if (ret < 0)
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dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
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addr, ret);
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return ret;
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}
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/**
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* ab8500_write() - write an AB8500 register
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* @ab8500: device to write to
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* @addr: address of the register
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* @data: value to write
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*/
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int ab8500_write(struct ab8500 *ab8500, u16 addr, u8 data)
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{
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int ret;
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mutex_lock(&ab8500->lock);
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ret = __ab8500_write(ab8500, addr, data);
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mutex_unlock(&ab8500->lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(ab8500_write);
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static int __ab8500_read(struct ab8500 *ab8500, u16 addr)
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{
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int ret;
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ret = ab8500->read(ab8500, addr);
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if (ret < 0)
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dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
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addr, ret);
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dev_vdbg(ab8500->dev, "rd: addr %#x => data %#x\n", addr, ret);
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return ret;
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}
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/**
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* ab8500_read() - read an AB8500 register
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* @ab8500: device to read from
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* @addr: address of the register
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*/
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int ab8500_read(struct ab8500 *ab8500, u16 addr)
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{
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int ret;
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mutex_lock(&ab8500->lock);
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ret = __ab8500_read(ab8500, addr);
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mutex_unlock(&ab8500->lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(ab8500_read);
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/**
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* ab8500_set_bits() - set a bitfield in an AB8500 register
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* @ab8500: device to read from
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* @addr: address of the register
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* @mask: mask of the bitfield to modify
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* @data: value to set to the bitfield
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*/
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int ab8500_set_bits(struct ab8500 *ab8500, u16 addr, u8 mask, u8 data)
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{
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int ret;
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mutex_lock(&ab8500->lock);
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ret = __ab8500_read(ab8500, addr);
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if (ret < 0)
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goto out;
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ret &= ~mask;
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ret |= data;
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ret = __ab8500_write(ab8500, addr, ret);
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out:
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mutex_unlock(&ab8500->lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(ab8500_set_bits);
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static void ab8500_irq_lock(unsigned int irq)
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{
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struct ab8500 *ab8500 = get_irq_chip_data(irq);
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mutex_lock(&ab8500->irq_lock);
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}
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static void ab8500_irq_sync_unlock(unsigned int irq)
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{
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struct ab8500 *ab8500 = get_irq_chip_data(irq);
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int i;
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for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) {
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u8 old = ab8500->oldmask[i];
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u8 new = ab8500->mask[i];
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int reg;
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if (new == old)
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continue;
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ab8500->oldmask[i] = new;
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reg = AB8500_IT_MASK1_REG + ab8500_irq_regoffset[i];
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ab8500_write(ab8500, reg, new);
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}
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mutex_unlock(&ab8500->irq_lock);
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}
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static void ab8500_irq_mask(unsigned int irq)
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{
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struct ab8500 *ab8500 = get_irq_chip_data(irq);
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int offset = irq - ab8500->irq_base;
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int index = offset / 8;
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int mask = 1 << (offset % 8);
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ab8500->mask[index] |= mask;
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}
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static void ab8500_irq_unmask(unsigned int irq)
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{
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struct ab8500 *ab8500 = get_irq_chip_data(irq);
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int offset = irq - ab8500->irq_base;
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int index = offset / 8;
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int mask = 1 << (offset % 8);
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ab8500->mask[index] &= ~mask;
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}
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static struct irq_chip ab8500_irq_chip = {
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.name = "ab8500",
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.bus_lock = ab8500_irq_lock,
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.bus_sync_unlock = ab8500_irq_sync_unlock,
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.mask = ab8500_irq_mask,
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.unmask = ab8500_irq_unmask,
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};
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static irqreturn_t ab8500_irq(int irq, void *dev)
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{
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struct ab8500 *ab8500 = dev;
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int i;
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dev_vdbg(ab8500->dev, "interrupt\n");
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for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) {
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int regoffset = ab8500_irq_regoffset[i];
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int status;
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status = ab8500_read(ab8500, AB8500_IT_LATCH1_REG + regoffset);
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if (status <= 0)
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continue;
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do {
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int bit = __ffs(status);
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int line = i * 8 + bit;
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handle_nested_irq(ab8500->irq_base + line);
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status &= ~(1 << bit);
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} while (status);
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}
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return IRQ_HANDLED;
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}
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static int ab8500_irq_init(struct ab8500 *ab8500)
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{
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int base = ab8500->irq_base;
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int irq;
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for (irq = base; irq < base + AB8500_NR_IRQS; irq++) {
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set_irq_chip_data(irq, ab8500);
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set_irq_chip_and_handler(irq, &ab8500_irq_chip,
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handle_simple_irq);
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set_irq_nested_thread(irq, 1);
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#ifdef CONFIG_ARM
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set_irq_flags(irq, IRQF_VALID);
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#else
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set_irq_noprobe(irq);
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#endif
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}
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return 0;
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}
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static void ab8500_irq_remove(struct ab8500 *ab8500)
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{
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int base = ab8500->irq_base;
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int irq;
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for (irq = base; irq < base + AB8500_NR_IRQS; irq++) {
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#ifdef CONFIG_ARM
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set_irq_flags(irq, 0);
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#endif
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set_irq_chip_and_handler(irq, NULL, NULL);
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set_irq_chip_data(irq, NULL);
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}
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}
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static struct resource ab8500_gpadc_resources[] = {
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{
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.name = "HW_CONV_END",
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.start = AB8500_INT_GP_HW_ADC_CONV_END,
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.end = AB8500_INT_GP_HW_ADC_CONV_END,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "SW_CONV_END",
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.start = AB8500_INT_GP_SW_ADC_CONV_END,
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.end = AB8500_INT_GP_SW_ADC_CONV_END,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource ab8500_rtc_resources[] = {
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{
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.name = "60S",
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.start = AB8500_INT_RTC_60S,
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.end = AB8500_INT_RTC_60S,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "ALARM",
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.start = AB8500_INT_RTC_ALARM,
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.end = AB8500_INT_RTC_ALARM,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource ab8500_poweronkey_db_resources[] = {
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{
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.name = "ONKEY_DBF",
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.start = AB8500_INT_PON_KEY1DB_F,
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.end = AB8500_INT_PON_KEY1DB_F,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "ONKEY_DBR",
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.start = AB8500_INT_PON_KEY1DB_R,
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.end = AB8500_INT_PON_KEY1DB_R,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct mfd_cell ab8500_devs[] = {
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{
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.name = "ab8500-gpadc",
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.num_resources = ARRAY_SIZE(ab8500_gpadc_resources),
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.resources = ab8500_gpadc_resources,
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},
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{
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.name = "ab8500-rtc",
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.num_resources = ARRAY_SIZE(ab8500_rtc_resources),
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.resources = ab8500_rtc_resources,
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},
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{ .name = "ab8500-charger", },
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{ .name = "ab8500-audio", },
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{ .name = "ab8500-usb", },
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{ .name = "ab8500-pwm", },
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{ .name = "ab8500-regulator", },
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{
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.name = "ab8500-poweron-key",
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.num_resources = ARRAY_SIZE(ab8500_poweronkey_db_resources),
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.resources = ab8500_poweronkey_db_resources,
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},
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};
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int __devinit ab8500_init(struct ab8500 *ab8500)
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{
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struct ab8500_platform_data *plat = dev_get_platdata(ab8500->dev);
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int ret;
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int i;
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if (plat)
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ab8500->irq_base = plat->irq_base;
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mutex_init(&ab8500->lock);
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mutex_init(&ab8500->irq_lock);
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ret = ab8500_read(ab8500, AB8500_REV_REG);
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if (ret < 0)
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return ret;
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/*
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* 0x0 - Early Drop
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* 0x10 - Cut 1.0
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* 0x11 - Cut 1.1
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*/
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if (ret == 0x0 || ret == 0x10 || ret == 0x11) {
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ab8500->revision = ret;
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dev_info(ab8500->dev, "detected chip, revision: %#x\n", ret);
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} else {
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dev_err(ab8500->dev, "unknown chip, revision: %#x\n", ret);
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return -EINVAL;
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}
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if (plat && plat->init)
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plat->init(ab8500);
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/* Clear and mask all interrupts */
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for (i = 0; i < 10; i++) {
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ab8500_read(ab8500, AB8500_IT_LATCH1_REG + i);
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ab8500_write(ab8500, AB8500_IT_MASK1_REG + i, 0xff);
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}
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for (i = 18; i < 24; i++) {
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ab8500_read(ab8500, AB8500_IT_LATCH1_REG + i);
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ab8500_write(ab8500, AB8500_IT_MASK1_REG + i, 0xff);
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}
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for (i = 0; i < AB8500_NUM_IRQ_REGS; i++)
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ab8500->mask[i] = ab8500->oldmask[i] = 0xff;
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if (ab8500->irq_base) {
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ret = ab8500_irq_init(ab8500);
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if (ret)
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return ret;
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ret = request_threaded_irq(ab8500->irq, NULL, ab8500_irq,
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IRQF_ONESHOT, "ab8500", ab8500);
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if (ret)
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goto out_removeirq;
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}
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ret = mfd_add_devices(ab8500->dev, 0, ab8500_devs,
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ARRAY_SIZE(ab8500_devs), NULL,
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ab8500->irq_base);
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if (ret)
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goto out_freeirq;
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return ret;
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out_freeirq:
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if (ab8500->irq_base) {
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free_irq(ab8500->irq, ab8500);
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out_removeirq:
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ab8500_irq_remove(ab8500);
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}
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return ret;
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}
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int __devexit ab8500_exit(struct ab8500 *ab8500)
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{
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mfd_remove_devices(ab8500->dev);
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if (ab8500->irq_base) {
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free_irq(ab8500->irq, ab8500);
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ab8500_irq_remove(ab8500);
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}
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return 0;
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}
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MODULE_AUTHOR("Srinidhi Kasagar, Rabin Vincent");
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MODULE_DESCRIPTION("AB8500 MFD core");
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MODULE_LICENSE("GPL v2");
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