mirror of https://gitee.com/openkylin/linux.git
732 lines
20 KiB
C
732 lines
20 KiB
C
/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Zhi Wang <zhi.a.wang@intel.com>
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*
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* Contributors:
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* Ping Gao <ping.a.gao@intel.com>
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* Tina Zhang <tina.zhang@intel.com>
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* Chanbin Du <changbin.du@intel.com>
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* Min He <min.he@intel.com>
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* Bing Niu <bing.niu@intel.com>
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* Zhenyu Wang <zhenyuw@linux.intel.com>
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*
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*/
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#include <linux/kthread.h>
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#include "i915_drv.h"
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#include "gvt.h"
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#define RING_CTX_OFF(x) \
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offsetof(struct execlist_ring_context, x)
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static void set_context_pdp_root_pointer(
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struct execlist_ring_context *ring_context,
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u32 pdp[8])
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{
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struct execlist_mmio_pair *pdp_pair = &ring_context->pdp3_UDW;
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int i;
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for (i = 0; i < 8; i++)
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pdp_pair[i].val = pdp[7 - i];
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}
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static int populate_shadow_context(struct intel_vgpu_workload *workload)
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{
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struct intel_vgpu *vgpu = workload->vgpu;
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struct intel_gvt *gvt = vgpu->gvt;
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int ring_id = workload->ring_id;
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struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
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struct drm_i915_gem_object *ctx_obj =
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shadow_ctx->engine[ring_id].state->obj;
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struct execlist_ring_context *shadow_ring_context;
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struct page *page;
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void *dst;
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unsigned long context_gpa, context_page_num;
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int i;
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gvt_dbg_sched("ring id %d workload lrca %x", ring_id,
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workload->ctx_desc.lrca);
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context_page_num = gvt->dev_priv->engine[ring_id]->context_size;
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context_page_num = context_page_num >> PAGE_SHIFT;
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if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS)
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context_page_num = 19;
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i = 2;
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while (i < context_page_num) {
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context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
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(u32)((workload->ctx_desc.lrca + i) <<
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GTT_PAGE_SHIFT));
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if (context_gpa == INTEL_GVT_INVALID_ADDR) {
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gvt_vgpu_err("Invalid guest context descriptor\n");
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return -EINVAL;
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}
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page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
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dst = kmap(page);
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intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst,
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GTT_PAGE_SIZE);
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kunmap(page);
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i++;
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}
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page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
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shadow_ring_context = kmap(page);
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#define COPY_REG(name) \
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intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
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+ RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
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COPY_REG(ctx_ctrl);
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COPY_REG(ctx_timestamp);
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if (ring_id == RCS) {
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COPY_REG(bb_per_ctx_ptr);
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COPY_REG(rcs_indirect_ctx);
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COPY_REG(rcs_indirect_ctx_offset);
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}
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#undef COPY_REG
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set_context_pdp_root_pointer(shadow_ring_context,
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workload->shadow_mm->shadow_page_table);
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intel_gvt_hypervisor_read_gpa(vgpu,
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workload->ring_context_gpa +
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sizeof(*shadow_ring_context),
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(void *)shadow_ring_context +
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sizeof(*shadow_ring_context),
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GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
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kunmap(page);
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return 0;
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}
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static inline bool is_gvt_request(struct drm_i915_gem_request *req)
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{
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return i915_gem_context_force_single_submission(req->ctx);
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}
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static int shadow_context_status_change(struct notifier_block *nb,
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unsigned long action, void *data)
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{
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struct drm_i915_gem_request *req = (struct drm_i915_gem_request *)data;
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struct intel_gvt *gvt = container_of(nb, struct intel_gvt,
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shadow_ctx_notifier_block[req->engine->id]);
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struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
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enum intel_engine_id ring_id = req->engine->id;
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struct intel_vgpu_workload *workload;
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if (!is_gvt_request(req)) {
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spin_lock_bh(&scheduler->mmio_context_lock);
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if (action == INTEL_CONTEXT_SCHEDULE_IN &&
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scheduler->engine_owner[ring_id]) {
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/* Switch ring from vGPU to host. */
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intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
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NULL, ring_id);
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scheduler->engine_owner[ring_id] = NULL;
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}
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spin_unlock_bh(&scheduler->mmio_context_lock);
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return NOTIFY_OK;
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}
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workload = scheduler->current_workload[ring_id];
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if (unlikely(!workload))
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return NOTIFY_OK;
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switch (action) {
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case INTEL_CONTEXT_SCHEDULE_IN:
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spin_lock_bh(&scheduler->mmio_context_lock);
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if (workload->vgpu != scheduler->engine_owner[ring_id]) {
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/* Switch ring from host to vGPU or vGPU to vGPU. */
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intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
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workload->vgpu, ring_id);
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scheduler->engine_owner[ring_id] = workload->vgpu;
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} else
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gvt_dbg_sched("skip ring %d mmio switch for vgpu%d\n",
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ring_id, workload->vgpu->id);
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spin_unlock_bh(&scheduler->mmio_context_lock);
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atomic_set(&workload->shadow_ctx_active, 1);
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break;
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case INTEL_CONTEXT_SCHEDULE_OUT:
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case INTEL_CONTEXT_SCHEDULE_PREEMPTED:
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atomic_set(&workload->shadow_ctx_active, 0);
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break;
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default:
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WARN_ON(1);
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return NOTIFY_OK;
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}
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wake_up(&workload->shadow_ctx_status_wq);
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return NOTIFY_OK;
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}
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static void shadow_context_descriptor_update(struct i915_gem_context *ctx,
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struct intel_engine_cs *engine)
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{
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struct intel_context *ce = &ctx->engine[engine->id];
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u64 desc = 0;
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desc = ce->lrc_desc;
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/* Update bits 0-11 of the context descriptor which includes flags
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* like GEN8_CTX_* cached in desc_template
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*/
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desc &= U64_MAX << 12;
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desc |= ctx->desc_template & ((1ULL << 12) - 1);
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ce->lrc_desc = desc;
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}
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static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload)
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{
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struct intel_vgpu *vgpu = workload->vgpu;
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void *shadow_ring_buffer_va;
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u32 *cs;
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/* allocate shadow ring buffer */
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cs = intel_ring_begin(workload->req, workload->rb_len / sizeof(u32));
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if (IS_ERR(cs)) {
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gvt_vgpu_err("fail to alloc size =%ld shadow ring buffer\n",
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workload->rb_len);
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return PTR_ERR(cs);
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}
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shadow_ring_buffer_va = workload->shadow_ring_buffer_va;
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/* get shadow ring buffer va */
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workload->shadow_ring_buffer_va = cs;
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memcpy(cs, shadow_ring_buffer_va,
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workload->rb_len);
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cs += workload->rb_len / sizeof(u32);
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intel_ring_advance(workload->req, cs);
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return 0;
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}
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void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
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{
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if (!wa_ctx->indirect_ctx.obj)
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return;
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i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj);
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i915_gem_object_put(wa_ctx->indirect_ctx.obj);
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}
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/**
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* intel_gvt_scan_and_shadow_workload - audit the workload by scanning and
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* shadow it as well, include ringbuffer,wa_ctx and ctx.
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* @workload: an abstract entity for each execlist submission.
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*
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* This function is called before the workload submitting to i915, to make
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* sure the content of the workload is valid.
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*/
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int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
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{
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int ring_id = workload->ring_id;
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struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
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struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
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struct intel_engine_cs *engine = dev_priv->engine[ring_id];
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struct drm_i915_gem_request *rq;
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struct intel_vgpu *vgpu = workload->vgpu;
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struct intel_ring *ring;
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int ret;
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lockdep_assert_held(&dev_priv->drm.struct_mutex);
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if (workload->shadowed)
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return 0;
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shadow_ctx->desc_template &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT);
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shadow_ctx->desc_template |= workload->ctx_desc.addressing_mode <<
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GEN8_CTX_ADDRESSING_MODE_SHIFT;
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if (!test_and_set_bit(ring_id, vgpu->shadow_ctx_desc_updated))
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shadow_context_descriptor_update(shadow_ctx,
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dev_priv->engine[ring_id]);
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ret = intel_gvt_scan_and_shadow_ringbuffer(workload);
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if (ret)
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goto err_scan;
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if ((workload->ring_id == RCS) &&
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(workload->wa_ctx.indirect_ctx.size != 0)) {
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ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx);
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if (ret)
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goto err_scan;
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}
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/* pin shadow context by gvt even the shadow context will be pinned
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* when i915 alloc request. That is because gvt will update the guest
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* context from shadow context when workload is completed, and at that
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* moment, i915 may already unpined the shadow context to make the
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* shadow_ctx pages invalid. So gvt need to pin itself. After update
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* the guest context, gvt can unpin the shadow_ctx safely.
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*/
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ring = engine->context_pin(engine, shadow_ctx);
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if (IS_ERR(ring)) {
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ret = PTR_ERR(ring);
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gvt_vgpu_err("fail to pin shadow context\n");
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goto err_shadow;
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}
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ret = populate_shadow_context(workload);
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if (ret)
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goto err_unpin;
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rq = i915_gem_request_alloc(dev_priv->engine[ring_id], shadow_ctx);
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if (IS_ERR(rq)) {
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gvt_vgpu_err("fail to allocate gem request\n");
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ret = PTR_ERR(rq);
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goto err_unpin;
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}
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gvt_dbg_sched("ring id %d get i915 gem request %p\n", ring_id, rq);
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workload->req = i915_gem_request_get(rq);
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ret = copy_workload_to_ring_buffer(workload);
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if (ret)
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goto err_unpin;
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workload->shadowed = true;
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return 0;
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err_unpin:
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engine->context_unpin(engine, shadow_ctx);
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err_shadow:
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release_shadow_wa_ctx(&workload->wa_ctx);
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err_scan:
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return ret;
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}
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static int dispatch_workload(struct intel_vgpu_workload *workload)
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{
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int ring_id = workload->ring_id;
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struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
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struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
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struct intel_engine_cs *engine = dev_priv->engine[ring_id];
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int ret = 0;
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gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n",
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ring_id, workload);
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mutex_lock(&dev_priv->drm.struct_mutex);
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ret = intel_gvt_scan_and_shadow_workload(workload);
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if (ret)
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goto out;
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if (workload->prepare) {
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ret = workload->prepare(workload);
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if (ret) {
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engine->context_unpin(engine, shadow_ctx);
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goto out;
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}
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}
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out:
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if (ret)
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workload->status = ret;
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if (!IS_ERR_OR_NULL(workload->req)) {
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gvt_dbg_sched("ring id %d submit workload to i915 %p\n",
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ring_id, workload->req);
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i915_add_request(workload->req);
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workload->dispatched = true;
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}
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mutex_unlock(&dev_priv->drm.struct_mutex);
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return ret;
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}
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static struct intel_vgpu_workload *pick_next_workload(
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struct intel_gvt *gvt, int ring_id)
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{
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struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
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struct intel_vgpu_workload *workload = NULL;
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mutex_lock(&gvt->lock);
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/*
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* no current vgpu / will be scheduled out / no workload
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* bail out
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*/
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if (!scheduler->current_vgpu) {
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gvt_dbg_sched("ring id %d stop - no current vgpu\n", ring_id);
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goto out;
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}
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if (scheduler->need_reschedule) {
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gvt_dbg_sched("ring id %d stop - will reschedule\n", ring_id);
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goto out;
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}
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if (list_empty(workload_q_head(scheduler->current_vgpu, ring_id)))
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goto out;
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/*
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* still have current workload, maybe the workload disptacher
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* fail to submit it for some reason, resubmit it.
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*/
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if (scheduler->current_workload[ring_id]) {
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workload = scheduler->current_workload[ring_id];
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gvt_dbg_sched("ring id %d still have current workload %p\n",
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ring_id, workload);
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goto out;
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}
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/*
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* pick a workload as current workload
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* once current workload is set, schedule policy routines
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* will wait the current workload is finished when trying to
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* schedule out a vgpu.
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*/
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scheduler->current_workload[ring_id] = container_of(
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workload_q_head(scheduler->current_vgpu, ring_id)->next,
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struct intel_vgpu_workload, list);
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workload = scheduler->current_workload[ring_id];
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gvt_dbg_sched("ring id %d pick new workload %p\n", ring_id, workload);
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atomic_inc(&workload->vgpu->running_workload_num);
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out:
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mutex_unlock(&gvt->lock);
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return workload;
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}
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static void update_guest_context(struct intel_vgpu_workload *workload)
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{
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struct intel_vgpu *vgpu = workload->vgpu;
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struct intel_gvt *gvt = vgpu->gvt;
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int ring_id = workload->ring_id;
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struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
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struct drm_i915_gem_object *ctx_obj =
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shadow_ctx->engine[ring_id].state->obj;
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struct execlist_ring_context *shadow_ring_context;
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struct page *page;
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void *src;
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unsigned long context_gpa, context_page_num;
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int i;
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gvt_dbg_sched("ring id %d workload lrca %x\n", ring_id,
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workload->ctx_desc.lrca);
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context_page_num = gvt->dev_priv->engine[ring_id]->context_size;
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context_page_num = context_page_num >> PAGE_SHIFT;
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if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS)
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context_page_num = 19;
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i = 2;
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while (i < context_page_num) {
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context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
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(u32)((workload->ctx_desc.lrca + i) <<
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GTT_PAGE_SHIFT));
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if (context_gpa == INTEL_GVT_INVALID_ADDR) {
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gvt_vgpu_err("invalid guest context descriptor\n");
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return;
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}
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page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
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src = kmap(page);
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intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src,
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GTT_PAGE_SIZE);
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kunmap(page);
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i++;
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}
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intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa +
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RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4);
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page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
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shadow_ring_context = kmap(page);
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#define COPY_REG(name) \
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intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \
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RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
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COPY_REG(ctx_ctrl);
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COPY_REG(ctx_timestamp);
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#undef COPY_REG
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intel_gvt_hypervisor_write_gpa(vgpu,
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workload->ring_context_gpa +
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sizeof(*shadow_ring_context),
|
|
(void *)shadow_ring_context +
|
|
sizeof(*shadow_ring_context),
|
|
GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
|
|
|
|
kunmap(page);
|
|
}
|
|
|
|
static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
|
|
{
|
|
struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
|
|
struct intel_vgpu_workload *workload;
|
|
struct intel_vgpu *vgpu;
|
|
int event;
|
|
|
|
mutex_lock(&gvt->lock);
|
|
|
|
workload = scheduler->current_workload[ring_id];
|
|
vgpu = workload->vgpu;
|
|
|
|
/* For the workload w/ request, needs to wait for the context
|
|
* switch to make sure request is completed.
|
|
* For the workload w/o request, directly complete the workload.
|
|
*/
|
|
if (workload->req) {
|
|
struct drm_i915_private *dev_priv =
|
|
workload->vgpu->gvt->dev_priv;
|
|
struct intel_engine_cs *engine =
|
|
dev_priv->engine[workload->ring_id];
|
|
wait_event(workload->shadow_ctx_status_wq,
|
|
!atomic_read(&workload->shadow_ctx_active));
|
|
|
|
/* If this request caused GPU hang, req->fence.error will
|
|
* be set to -EIO. Use -EIO to set workload status so
|
|
* that when this request caused GPU hang, didn't trigger
|
|
* context switch interrupt to guest.
|
|
*/
|
|
if (likely(workload->status == -EINPROGRESS)) {
|
|
if (workload->req->fence.error == -EIO)
|
|
workload->status = -EIO;
|
|
else
|
|
workload->status = 0;
|
|
}
|
|
|
|
i915_gem_request_put(fetch_and_zero(&workload->req));
|
|
|
|
if (!workload->status && !(vgpu->resetting_eng &
|
|
ENGINE_MASK(ring_id))) {
|
|
update_guest_context(workload);
|
|
|
|
for_each_set_bit(event, workload->pending_events,
|
|
INTEL_GVT_EVENT_MAX)
|
|
intel_vgpu_trigger_virtual_event(vgpu, event);
|
|
}
|
|
mutex_lock(&dev_priv->drm.struct_mutex);
|
|
/* unpin shadow ctx as the shadow_ctx update is done */
|
|
engine->context_unpin(engine, workload->vgpu->shadow_ctx);
|
|
mutex_unlock(&dev_priv->drm.struct_mutex);
|
|
}
|
|
|
|
gvt_dbg_sched("ring id %d complete workload %p status %d\n",
|
|
ring_id, workload, workload->status);
|
|
|
|
scheduler->current_workload[ring_id] = NULL;
|
|
|
|
list_del_init(&workload->list);
|
|
workload->complete(workload);
|
|
|
|
atomic_dec(&vgpu->running_workload_num);
|
|
wake_up(&scheduler->workload_complete_wq);
|
|
|
|
if (gvt->scheduler.need_reschedule)
|
|
intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EVENT_SCHED);
|
|
|
|
mutex_unlock(&gvt->lock);
|
|
}
|
|
|
|
struct workload_thread_param {
|
|
struct intel_gvt *gvt;
|
|
int ring_id;
|
|
};
|
|
|
|
static int workload_thread(void *priv)
|
|
{
|
|
struct workload_thread_param *p = (struct workload_thread_param *)priv;
|
|
struct intel_gvt *gvt = p->gvt;
|
|
int ring_id = p->ring_id;
|
|
struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
|
|
struct intel_vgpu_workload *workload = NULL;
|
|
struct intel_vgpu *vgpu = NULL;
|
|
int ret;
|
|
bool need_force_wake = IS_SKYLAKE(gvt->dev_priv)
|
|
|| IS_KABYLAKE(gvt->dev_priv);
|
|
DEFINE_WAIT_FUNC(wait, woken_wake_function);
|
|
|
|
kfree(p);
|
|
|
|
gvt_dbg_core("workload thread for ring %d started\n", ring_id);
|
|
|
|
while (!kthread_should_stop()) {
|
|
add_wait_queue(&scheduler->waitq[ring_id], &wait);
|
|
do {
|
|
workload = pick_next_workload(gvt, ring_id);
|
|
if (workload)
|
|
break;
|
|
wait_woken(&wait, TASK_INTERRUPTIBLE,
|
|
MAX_SCHEDULE_TIMEOUT);
|
|
} while (!kthread_should_stop());
|
|
remove_wait_queue(&scheduler->waitq[ring_id], &wait);
|
|
|
|
if (!workload)
|
|
break;
|
|
|
|
gvt_dbg_sched("ring id %d next workload %p vgpu %d\n",
|
|
workload->ring_id, workload,
|
|
workload->vgpu->id);
|
|
|
|
intel_runtime_pm_get(gvt->dev_priv);
|
|
|
|
gvt_dbg_sched("ring id %d will dispatch workload %p\n",
|
|
workload->ring_id, workload);
|
|
|
|
if (need_force_wake)
|
|
intel_uncore_forcewake_get(gvt->dev_priv,
|
|
FORCEWAKE_ALL);
|
|
|
|
mutex_lock(&gvt->lock);
|
|
ret = dispatch_workload(workload);
|
|
mutex_unlock(&gvt->lock);
|
|
|
|
if (ret) {
|
|
vgpu = workload->vgpu;
|
|
gvt_vgpu_err("fail to dispatch workload, skip\n");
|
|
goto complete;
|
|
}
|
|
|
|
gvt_dbg_sched("ring id %d wait workload %p\n",
|
|
workload->ring_id, workload);
|
|
i915_wait_request(workload->req, 0, MAX_SCHEDULE_TIMEOUT);
|
|
|
|
complete:
|
|
gvt_dbg_sched("will complete workload %p, status: %d\n",
|
|
workload, workload->status);
|
|
|
|
complete_current_workload(gvt, ring_id);
|
|
|
|
if (need_force_wake)
|
|
intel_uncore_forcewake_put(gvt->dev_priv,
|
|
FORCEWAKE_ALL);
|
|
|
|
intel_runtime_pm_put(gvt->dev_priv);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu)
|
|
{
|
|
struct intel_gvt *gvt = vgpu->gvt;
|
|
struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
|
|
|
|
if (atomic_read(&vgpu->running_workload_num)) {
|
|
gvt_dbg_sched("wait vgpu idle\n");
|
|
|
|
wait_event(scheduler->workload_complete_wq,
|
|
!atomic_read(&vgpu->running_workload_num));
|
|
}
|
|
}
|
|
|
|
void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt)
|
|
{
|
|
struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
|
|
struct intel_engine_cs *engine;
|
|
enum intel_engine_id i;
|
|
|
|
gvt_dbg_core("clean workload scheduler\n");
|
|
|
|
for_each_engine(engine, gvt->dev_priv, i) {
|
|
atomic_notifier_chain_unregister(
|
|
&engine->context_status_notifier,
|
|
&gvt->shadow_ctx_notifier_block[i]);
|
|
kthread_stop(scheduler->thread[i]);
|
|
}
|
|
}
|
|
|
|
int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt)
|
|
{
|
|
struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
|
|
struct workload_thread_param *param = NULL;
|
|
struct intel_engine_cs *engine;
|
|
enum intel_engine_id i;
|
|
int ret;
|
|
|
|
gvt_dbg_core("init workload scheduler\n");
|
|
|
|
init_waitqueue_head(&scheduler->workload_complete_wq);
|
|
|
|
for_each_engine(engine, gvt->dev_priv, i) {
|
|
init_waitqueue_head(&scheduler->waitq[i]);
|
|
|
|
param = kzalloc(sizeof(*param), GFP_KERNEL);
|
|
if (!param) {
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
param->gvt = gvt;
|
|
param->ring_id = i;
|
|
|
|
scheduler->thread[i] = kthread_run(workload_thread, param,
|
|
"gvt workload %d", i);
|
|
if (IS_ERR(scheduler->thread[i])) {
|
|
gvt_err("fail to create workload thread\n");
|
|
ret = PTR_ERR(scheduler->thread[i]);
|
|
goto err;
|
|
}
|
|
|
|
gvt->shadow_ctx_notifier_block[i].notifier_call =
|
|
shadow_context_status_change;
|
|
atomic_notifier_chain_register(&engine->context_status_notifier,
|
|
&gvt->shadow_ctx_notifier_block[i]);
|
|
}
|
|
return 0;
|
|
err:
|
|
intel_gvt_clean_workload_scheduler(gvt);
|
|
kfree(param);
|
|
param = NULL;
|
|
return ret;
|
|
}
|
|
|
|
void intel_vgpu_clean_gvt_context(struct intel_vgpu *vgpu)
|
|
{
|
|
i915_gem_context_put(vgpu->shadow_ctx);
|
|
}
|
|
|
|
int intel_vgpu_init_gvt_context(struct intel_vgpu *vgpu)
|
|
{
|
|
atomic_set(&vgpu->running_workload_num, 0);
|
|
|
|
vgpu->shadow_ctx = i915_gem_context_create_gvt(
|
|
&vgpu->gvt->dev_priv->drm);
|
|
if (IS_ERR(vgpu->shadow_ctx))
|
|
return PTR_ERR(vgpu->shadow_ctx);
|
|
|
|
vgpu->shadow_ctx->engine[RCS].initialised = true;
|
|
|
|
bitmap_zero(vgpu->shadow_ctx_desc_updated, I915_NUM_ENGINES);
|
|
|
|
return 0;
|
|
}
|