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Jason Gunthorpe 340c0c53ea fpga zynq: Fix incorrect ISR state on bootup 
It is best practice to clear and mask all interrupts before
associating the IRQ, and this should be done after the clock
is enabled.

This corrects a bad result from zynq_fpga_ops_state on bootup
where left over latched values in INT_STS_OFFSET caused it to
report an unconfigured FPGA as configured.

After this change the boot up operating state for an unconfigured
FPGA reports 'unknown'.

Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Acked-by: Alan Tull <atull@opensource.altera.com>
Acked-by: Moritz Fischer <moritz.fischer@ettus.com>
 		2016-11-29 15:51:48 -06:00
..
Kconfig fpga: Add COMPILE_TEST to all drivers 2016-11-29 15:51:44 -06:00
Makefile fpga-manager: Add Socfpga Arria10 support 2016-11-10 17:03:36 +01:00
altera-fpga2sdram.c ARM: socfpga: checking the wrong variable 2016-11-17 08:14:55 +01:00
altera-freeze-bridge.c fpga: add altera freeze bridge support 2016-11-10 17:03:36 +01:00
altera-hps2fpga.c ARM: socfpga: fpga bridge driver support 2016-11-10 17:03:36 +01:00
fpga-bridge.c fpga: add fpga bridge framework 2016-11-10 17:03:35 +01:00
fpga-mgr.c fpga-mgr: add fpga image information struct 2016-11-10 17:03:35 +01:00
fpga-region.c fpga: fpga-region: device tree control for FPGA 2016-11-10 17:03:35 +01:00
socfpga-a10.c fpga-manager: Add Socfpga Arria10 support 2016-11-10 17:03:36 +01:00
socfpga.c fpga-mgr: add fpga image information struct 2016-11-10 17:03:35 +01:00
zynq-fpga.c fpga zynq: Fix incorrect ISR state on bootup 2016-11-29 15:51:48 -06:00